2
* Copyright (c) 2017-2019 Lima Project
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
9
* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
27
#include "util/ralloc.h"
28
#include "util/u_debug.h"
29
#include "util/u_screen.h"
30
#include "renderonly/renderonly.h"
32
#include "drm-uapi/drm_fourcc.h"
33
#include "drm-uapi/lima_drm.h"
35
#include "lima_screen.h"
36
#include "lima_context.h"
37
#include "lima_resource.h"
38
#include "lima_program.h"
40
#include "lima_fence.h"
41
#include "lima_format.h"
42
#include "lima_disk_cache.h"
43
#include "ir/lima_ir.h"
47
int lima_plb_max_blk = 0;
48
int lima_plb_pp_stream_cache_size = 0;
51
lima_screen_destroy(struct pipe_screen *pscreen)
53
struct lima_screen *screen = lima_screen(pscreen);
55
slab_destroy_parent(&screen->transfer_pool);
58
screen->ro->destroy(screen->ro);
60
if (screen->pp_buffer)
61
lima_bo_unreference(screen->pp_buffer);
63
lima_bo_cache_fini(screen);
64
lima_bo_table_fini(screen);
65
disk_cache_destroy(screen->disk_cache);
70
lima_screen_get_name(struct pipe_screen *pscreen)
72
struct lima_screen *screen = lima_screen(pscreen);
74
switch (screen->gpu_type) {
75
case DRM_LIMA_PARAM_GPU_ID_MALI400:
77
case DRM_LIMA_PARAM_GPU_ID_MALI450:
85
lima_screen_get_vendor(struct pipe_screen *pscreen)
91
lima_screen_get_device_vendor(struct pipe_screen *pscreen)
97
lima_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
100
case PIPE_CAP_NPOT_TEXTURES:
101
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
102
case PIPE_CAP_ACCELERATED:
104
case PIPE_CAP_CLIP_HALFZ:
105
case PIPE_CAP_NATIVE_FENCE_FD:
106
case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
107
case PIPE_CAP_TEXTURE_SWIZZLE:
108
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
111
/* Unimplemented, but for exporting OpenGL 2.0 */
112
case PIPE_CAP_POINT_SPRITE:
115
/* not clear supported */
116
case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
117
case PIPE_CAP_FS_COORD_ORIGIN_LOWER_LEFT:
118
case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
119
case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
122
case PIPE_CAP_FS_POSITION_IS_SYSVAL:
123
case PIPE_CAP_FS_POINT_IS_SYSVAL:
124
case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
127
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
130
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
131
return 1 << (LIMA_MAX_MIP_LEVELS - 1);
132
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
133
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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return LIMA_MAX_MIP_LEVELS;
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case PIPE_CAP_VENDOR_ID:
139
case PIPE_CAP_VIDEO_MEMORY:
142
case PIPE_CAP_PCI_GROUP:
143
case PIPE_CAP_PCI_BUS:
144
case PIPE_CAP_PCI_DEVICE:
145
case PIPE_CAP_PCI_FUNCTION:
148
case PIPE_CAP_TEXTURE_TRANSFER_MODES:
149
case PIPE_CAP_SHAREABLE_SHADERS:
152
case PIPE_CAP_ALPHA_TEST:
155
case PIPE_CAP_FLATSHADE:
156
case PIPE_CAP_TWO_SIDED_COLOR:
157
case PIPE_CAP_CLIP_PLANES:
160
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
163
/* Mali4x0 PP doesn't have a swizzle for load_input, so use POT-aligned
164
* varyings to avoid unnecessary movs for vec3 and precision downgrade
165
* in case if this vec3 is coordinates for a sampler
167
case PIPE_CAP_PREFER_POT_ALIGNED_VARYINGS:
170
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
174
return u_pipe_screen_get_param_defaults(pscreen, param);
179
lima_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
182
case PIPE_CAPF_MIN_LINE_WIDTH:
183
case PIPE_CAPF_MIN_LINE_WIDTH_AA:
184
case PIPE_CAPF_MIN_POINT_SIZE:
185
case PIPE_CAPF_MIN_POINT_SIZE_AA:
187
case PIPE_CAPF_POINT_SIZE_GRANULARITY:
188
case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
190
case PIPE_CAPF_MAX_LINE_WIDTH:
191
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
192
case PIPE_CAPF_MAX_POINT_SIZE:
193
case PIPE_CAPF_MAX_POINT_SIZE_AA:
195
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
197
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
206
get_vertex_shader_param(struct lima_screen *screen,
207
enum pipe_shader_cap param)
210
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
211
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
212
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
213
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
214
return 16384; /* need investigate */
216
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
219
case PIPE_SHADER_CAP_MAX_INPUTS:
220
return 16; /* attributes */
222
case PIPE_SHADER_CAP_MAX_OUTPUTS:
223
return LIMA_MAX_VARYING_NUM; /* varying */
225
/* Mali-400 GP provides space for 304 vec4 uniforms, globals and
226
* temporary variables. */
227
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
228
return 304 * 4 * sizeof(float);
230
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
233
case PIPE_SHADER_CAP_PREFERRED_IR:
234
return PIPE_SHADER_IR_NIR;
236
case PIPE_SHADER_CAP_MAX_TEMPS:
237
return 256; /* need investigate */
239
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
248
get_fragment_shader_param(struct lima_screen *screen,
249
enum pipe_shader_cap param)
252
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
253
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
254
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
255
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
256
return 16384; /* need investigate */
258
case PIPE_SHADER_CAP_MAX_INPUTS:
259
return LIMA_MAX_VARYING_NUM - 1; /* varying, minus gl_Position */
261
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
264
/* The Mali-PP supports a uniform table up to size 32768 total.
265
* However, indirect access to an uniform only supports indices up
266
* to 8192 (a 2048 vec4 array). To prevent indices bigger than that,
267
* limit max const buffer size to 8192 for now. */
268
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
269
return 2048 * 4 * sizeof(float);
271
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
274
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
275
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
276
return 16; /* need investigate */
278
case PIPE_SHADER_CAP_PREFERRED_IR:
279
return PIPE_SHADER_IR_NIR;
281
case PIPE_SHADER_CAP_MAX_TEMPS:
282
return 256; /* need investigate */
284
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
285
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
288
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
289
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
292
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
301
lima_screen_get_shader_param(struct pipe_screen *pscreen,
302
enum pipe_shader_type shader,
303
enum pipe_shader_cap param)
305
struct lima_screen *screen = lima_screen(pscreen);
308
case PIPE_SHADER_FRAGMENT:
309
return get_fragment_shader_param(screen, param);
310
case PIPE_SHADER_VERTEX:
311
return get_vertex_shader_param(screen, param);
319
lima_screen_is_format_supported(struct pipe_screen *pscreen,
320
enum pipe_format format,
321
enum pipe_texture_target target,
322
unsigned sample_count,
323
unsigned storage_sample_count,
328
case PIPE_TEXTURE_1D:
329
case PIPE_TEXTURE_2D:
330
case PIPE_TEXTURE_3D:
331
case PIPE_TEXTURE_RECT:
332
case PIPE_TEXTURE_CUBE:
338
if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
341
/* be able to support 16, now limit to 4 */
342
if (sample_count > 1 && sample_count != 4)
345
if (usage & PIPE_BIND_RENDER_TARGET) {
346
if (!lima_format_pixel_supported(format))
349
/* multisample unsupported with half float target */
350
if (sample_count > 1 && util_format_is_float(format))
354
if (usage & PIPE_BIND_DEPTH_STENCIL) {
356
case PIPE_FORMAT_Z16_UNORM:
357
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
358
case PIPE_FORMAT_Z24X8_UNORM:
365
if (usage & PIPE_BIND_VERTEX_BUFFER) {
367
case PIPE_FORMAT_R32_FLOAT:
368
case PIPE_FORMAT_R32G32_FLOAT:
369
case PIPE_FORMAT_R32G32B32_FLOAT:
370
case PIPE_FORMAT_R32G32B32A32_FLOAT:
371
case PIPE_FORMAT_R32_FIXED:
372
case PIPE_FORMAT_R32G32_FIXED:
373
case PIPE_FORMAT_R32G32B32_FIXED:
374
case PIPE_FORMAT_R32G32B32A32_FIXED:
375
case PIPE_FORMAT_R16_FLOAT:
376
case PIPE_FORMAT_R16G16_FLOAT:
377
case PIPE_FORMAT_R16G16B16_FLOAT:
378
case PIPE_FORMAT_R16G16B16A16_FLOAT:
379
case PIPE_FORMAT_R32_UNORM:
380
case PIPE_FORMAT_R32G32_UNORM:
381
case PIPE_FORMAT_R32G32B32_UNORM:
382
case PIPE_FORMAT_R32G32B32A32_UNORM:
383
case PIPE_FORMAT_R32_SNORM:
384
case PIPE_FORMAT_R32G32_SNORM:
385
case PIPE_FORMAT_R32G32B32_SNORM:
386
case PIPE_FORMAT_R32G32B32A32_SNORM:
387
case PIPE_FORMAT_R32_USCALED:
388
case PIPE_FORMAT_R32G32_USCALED:
389
case PIPE_FORMAT_R32G32B32_USCALED:
390
case PIPE_FORMAT_R32G32B32A32_USCALED:
391
case PIPE_FORMAT_R32_SSCALED:
392
case PIPE_FORMAT_R32G32_SSCALED:
393
case PIPE_FORMAT_R32G32B32_SSCALED:
394
case PIPE_FORMAT_R32G32B32A32_SSCALED:
395
case PIPE_FORMAT_R16_UNORM:
396
case PIPE_FORMAT_R16G16_UNORM:
397
case PIPE_FORMAT_R16G16B16_UNORM:
398
case PIPE_FORMAT_R16G16B16A16_UNORM:
399
case PIPE_FORMAT_R16_SNORM:
400
case PIPE_FORMAT_R16G16_SNORM:
401
case PIPE_FORMAT_R16G16B16_SNORM:
402
case PIPE_FORMAT_R16G16B16A16_SNORM:
403
case PIPE_FORMAT_R16_USCALED:
404
case PIPE_FORMAT_R16G16_USCALED:
405
case PIPE_FORMAT_R16G16B16_USCALED:
406
case PIPE_FORMAT_R16G16B16A16_USCALED:
407
case PIPE_FORMAT_R16_SSCALED:
408
case PIPE_FORMAT_R16G16_SSCALED:
409
case PIPE_FORMAT_R16G16B16_SSCALED:
410
case PIPE_FORMAT_R16G16B16A16_SSCALED:
411
case PIPE_FORMAT_R8_UNORM:
412
case PIPE_FORMAT_R8G8_UNORM:
413
case PIPE_FORMAT_R8G8B8_UNORM:
414
case PIPE_FORMAT_R8G8B8A8_UNORM:
415
case PIPE_FORMAT_R8_SNORM:
416
case PIPE_FORMAT_R8G8_SNORM:
417
case PIPE_FORMAT_R8G8B8_SNORM:
418
case PIPE_FORMAT_R8G8B8A8_SNORM:
419
case PIPE_FORMAT_R8_USCALED:
420
case PIPE_FORMAT_R8G8_USCALED:
421
case PIPE_FORMAT_R8G8B8_USCALED:
422
case PIPE_FORMAT_R8G8B8A8_USCALED:
423
case PIPE_FORMAT_R8_SSCALED:
424
case PIPE_FORMAT_R8G8_SSCALED:
425
case PIPE_FORMAT_R8G8B8_SSCALED:
426
case PIPE_FORMAT_R8G8B8A8_SSCALED:
433
if (usage & PIPE_BIND_INDEX_BUFFER) {
435
case PIPE_FORMAT_R8_UINT:
436
case PIPE_FORMAT_R16_UINT:
437
case PIPE_FORMAT_R32_UINT:
444
if (usage & PIPE_BIND_SAMPLER_VIEW)
445
return lima_format_texel_supported(format);
451
lima_screen_get_compiler_options(struct pipe_screen *pscreen,
452
enum pipe_shader_ir ir,
453
enum pipe_shader_type shader)
455
return lima_program_get_compiler_options(shader);
459
lima_screen_set_plb_max_blk(struct lima_screen *screen)
461
if (lima_plb_max_blk) {
462
screen->plb_max_blk = lima_plb_max_blk;
466
if (screen->gpu_type == DRM_LIMA_PARAM_GPU_ID_MALI450)
467
screen->plb_max_blk = 4096;
469
screen->plb_max_blk = 512;
471
drmDevicePtr devinfo;
473
if (drmGetDevice2(screen->fd, 0, &devinfo))
476
if (devinfo->bustype == DRM_BUS_PLATFORM && devinfo->deviceinfo.platform) {
477
char **compatible = devinfo->deviceinfo.platform->compatible;
479
if (compatible && *compatible)
480
if (!strcmp("allwinner,sun50i-h5-mali", *compatible))
481
screen->plb_max_blk = 2048;
484
drmFreeDevice(&devinfo);
490
lima_screen_query_info(struct lima_screen *screen)
492
drmVersionPtr version = drmGetVersion(screen->fd);
496
if (version->version_major > 1 || version->version_minor > 0)
497
screen->has_growable_heap_buffer = true;
499
drmFreeVersion(version);
501
if (lima_debug & LIMA_DEBUG_NO_GROW_HEAP)
502
screen->has_growable_heap_buffer = false;
504
struct drm_lima_get_param param;
506
memset(¶m, 0, sizeof(param));
507
param.param = DRM_LIMA_PARAM_GPU_ID;
508
if (drmIoctl(screen->fd, DRM_IOCTL_LIMA_GET_PARAM, ¶m))
511
switch (param.value) {
512
case DRM_LIMA_PARAM_GPU_ID_MALI400:
513
case DRM_LIMA_PARAM_GPU_ID_MALI450:
514
screen->gpu_type = param.value;
520
memset(¶m, 0, sizeof(param));
521
param.param = DRM_LIMA_PARAM_NUM_PP;
522
if (drmIoctl(screen->fd, DRM_IOCTL_LIMA_GET_PARAM, ¶m))
525
screen->num_pp = param.value;
527
lima_screen_set_plb_max_blk(screen);
532
static const uint64_t lima_available_modifiers[] = {
533
DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED,
534
DRM_FORMAT_MOD_LINEAR,
537
static bool lima_is_modifier_external_only(enum pipe_format format)
539
return util_format_is_yuv(format);
543
lima_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
544
enum pipe_format format, int max,
546
unsigned int *external_only,
549
int num_modifiers = ARRAY_SIZE(lima_available_modifiers);
552
*count = num_modifiers;
556
*count = MIN2(max, num_modifiers);
557
for (int i = 0; i < *count; i++) {
558
modifiers[i] = lima_available_modifiers[i];
560
external_only[i] = lima_is_modifier_external_only(format);
565
lima_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
567
enum pipe_format format,
570
for (int i = 0; i < ARRAY_SIZE(lima_available_modifiers); i++) {
571
if (lima_available_modifiers[i] == modifier) {
573
*external_only = lima_is_modifier_external_only(format);
582
static const struct debug_named_value lima_debug_options[] = {
583
{ "gp", LIMA_DEBUG_GP,
584
"print GP shader compiler result of each stage" },
585
{ "pp", LIMA_DEBUG_PP,
586
"print PP shader compiler result of each stage" },
587
{ "dump", LIMA_DEBUG_DUMP,
588
"dump GPU command stream to $PWD/lima.dump" },
589
{ "shaderdb", LIMA_DEBUG_SHADERDB,
590
"print shader information for shaderdb" },
591
{ "nobocache", LIMA_DEBUG_NO_BO_CACHE,
592
"disable BO cache" },
593
{ "bocache", LIMA_DEBUG_BO_CACHE,
594
"print debug info for BO cache" },
595
{ "notiling", LIMA_DEBUG_NO_TILING,
596
"don't use tiled buffers" },
597
{ "nogrowheap", LIMA_DEBUG_NO_GROW_HEAP,
598
"disable growable heap buffer" },
599
{ "singlejob", LIMA_DEBUG_SINGLE_JOB,
600
"disable multi job optimization" },
601
{ "precompile", LIMA_DEBUG_PRECOMPILE,
602
"Precompile shaders for shader-db" },
603
{ "diskcache", LIMA_DEBUG_DISK_CACHE,
604
"print debug info for shader disk cache" },
608
DEBUG_GET_ONCE_FLAGS_OPTION(lima_debug, "LIMA_DEBUG", lima_debug_options, 0)
612
lima_screen_parse_env(void)
614
lima_debug = debug_get_option_lima_debug();
616
lima_ctx_num_plb = debug_get_num_option("LIMA_CTX_NUM_PLB", LIMA_CTX_PLB_DEF_NUM);
617
if (lima_ctx_num_plb > LIMA_CTX_PLB_MAX_NUM ||
618
lima_ctx_num_plb < LIMA_CTX_PLB_MIN_NUM) {
619
fprintf(stderr, "lima: LIMA_CTX_NUM_PLB %d out of range [%d %d], "
620
"reset to default %d\n", lima_ctx_num_plb, LIMA_CTX_PLB_MIN_NUM,
621
LIMA_CTX_PLB_MAX_NUM, LIMA_CTX_PLB_DEF_NUM);
622
lima_ctx_num_plb = LIMA_CTX_PLB_DEF_NUM;
625
lima_plb_max_blk = debug_get_num_option("LIMA_PLB_MAX_BLK", 0);
626
if (lima_plb_max_blk < 0 || lima_plb_max_blk > 65536) {
627
fprintf(stderr, "lima: LIMA_PLB_MAX_BLK %d out of range [%d %d], "
628
"reset to default %d\n", lima_plb_max_blk, 0, 65536, 0);
629
lima_plb_max_blk = 0;
632
lima_ppir_force_spilling = debug_get_num_option("LIMA_PPIR_FORCE_SPILLING", 0);
633
if (lima_ppir_force_spilling < 0) {
634
fprintf(stderr, "lima: LIMA_PPIR_FORCE_SPILLING %d less than 0, "
635
"reset to default 0\n", lima_ppir_force_spilling);
636
lima_ppir_force_spilling = 0;
639
lima_plb_pp_stream_cache_size = debug_get_num_option("LIMA_PLB_PP_STREAM_CACHE_SIZE", 0);
640
if (lima_plb_pp_stream_cache_size < 0) {
641
fprintf(stderr, "lima: LIMA_PLB_PP_STREAM_CACHE_SIZE %d less than 0, "
642
"reset to default 0\n", lima_plb_pp_stream_cache_size);
643
lima_plb_pp_stream_cache_size = 0;
647
static struct disk_cache *
648
lima_get_disk_shader_cache (struct pipe_screen *pscreen)
650
struct lima_screen *screen = lima_screen(pscreen);
652
return screen->disk_cache;
656
lima_screen_create(int fd, struct renderonly *ro)
658
uint64_t system_memory;
659
struct lima_screen *screen;
661
screen = rzalloc(NULL, struct lima_screen);
668
lima_screen_parse_env();
670
/* Limit PP PLB stream cache size to 0.1% of system memory */
671
if (!lima_plb_pp_stream_cache_size &&
672
os_get_total_physical_memory(&system_memory))
673
lima_plb_pp_stream_cache_size = system_memory >> 10;
675
/* Set lower limit on PP PLB cache size */
676
lima_plb_pp_stream_cache_size = MAX2(128 * 1024 * lima_ctx_num_plb,
677
lima_plb_pp_stream_cache_size);
679
if (!lima_screen_query_info(screen))
682
if (!lima_bo_cache_init(screen))
685
if (!lima_bo_table_init(screen))
688
screen->pp_ra = ppir_regalloc_init(screen);
692
screen->pp_buffer = lima_bo_create(screen, pp_buffer_size, 0);
693
if (!screen->pp_buffer)
695
screen->pp_buffer->cacheable = false;
697
/* fs program for clear buffer?
698
* const0 1 0 0 -1.67773, mov.v0 $0 ^const0.xxxx, stop
700
static const uint32_t pp_clear_program[] = {
701
0x00020425, 0x0000000c, 0x01e007cf, 0xb0000000,
702
0x000005f5, 0x00000000, 0x00000000, 0x00000000,
704
memcpy(lima_bo_map(screen->pp_buffer) + pp_clear_program_offset,
705
pp_clear_program, sizeof(pp_clear_program));
707
/* copy texture to framebuffer, used to reload gpu tile buffer
708
* load.v $1 0.xy, texld 0, mov.v0 $0 ^tex_sampler, sync, stop
710
static const uint32_t pp_reload_program[] = {
711
0x000005e6, 0xf1003c20, 0x00000000, 0x39001000,
712
0x00000e4e, 0x000007cf, 0x00000000, 0x00000000,
714
memcpy(lima_bo_map(screen->pp_buffer) + pp_reload_program_offset,
715
pp_reload_program, sizeof(pp_reload_program));
717
/* 0/1/2 vertex index for reload/clear draw */
718
static const uint8_t pp_shared_index[] = { 0, 1, 2 };
719
memcpy(lima_bo_map(screen->pp_buffer) + pp_shared_index_offset,
720
pp_shared_index, sizeof(pp_shared_index));
722
/* 4096x4096 gl pos used for partial clear */
723
static const float pp_clear_gl_pos[] = {
728
memcpy(lima_bo_map(screen->pp_buffer) + pp_clear_gl_pos_offset,
729
pp_clear_gl_pos, sizeof(pp_clear_gl_pos));
731
/* is pp frame render state static? */
732
uint32_t *pp_frame_rsw = lima_bo_map(screen->pp_buffer) + pp_frame_rsw_offset;
733
memset(pp_frame_rsw, 0, 0x40);
734
pp_frame_rsw[8] = 0x0000f008;
735
pp_frame_rsw[9] = screen->pp_buffer->va + pp_clear_program_offset;
736
pp_frame_rsw[13] = 0x00000100;
738
screen->base.destroy = lima_screen_destroy;
739
screen->base.get_name = lima_screen_get_name;
740
screen->base.get_vendor = lima_screen_get_vendor;
741
screen->base.get_device_vendor = lima_screen_get_device_vendor;
742
screen->base.get_param = lima_screen_get_param;
743
screen->base.get_paramf = lima_screen_get_paramf;
744
screen->base.get_shader_param = lima_screen_get_shader_param;
745
screen->base.context_create = lima_context_create;
746
screen->base.is_format_supported = lima_screen_is_format_supported;
747
screen->base.get_compiler_options = lima_screen_get_compiler_options;
748
screen->base.query_dmabuf_modifiers = lima_screen_query_dmabuf_modifiers;
749
screen->base.is_dmabuf_modifier_supported = lima_screen_is_dmabuf_modifier_supported;
750
screen->base.get_disk_shader_cache = lima_get_disk_shader_cache;
752
lima_resource_screen_init(screen);
753
lima_fence_screen_init(screen);
754
lima_disk_cache_init(screen);
756
slab_create_parent(&screen->transfer_pool, sizeof(struct lima_transfer), 16);
760
return &screen->base;
763
lima_bo_table_fini(screen);
765
lima_bo_cache_fini(screen);