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* Copyright © 2020 Valve Corporation
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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#include "aco_builder.h"
29
#include "util/debug.h"
31
#include "c11/threads.h"
35
uint64_t debug_flags = 0;
37
static const struct debug_control aco_debug_options[] = {{"validateir", DEBUG_VALIDATE_IR},
38
{"validatera", DEBUG_VALIDATE_RA},
39
{"perfwarn", DEBUG_PERFWARN},
40
{"force-waitcnt", DEBUG_FORCE_WAITCNT},
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{"novn", DEBUG_NO_VN},
42
{"noopt", DEBUG_NO_OPT},
43
{"nosched", DEBUG_NO_SCHED},
44
{"perfinfo", DEBUG_PERF_INFO},
45
{"liveinfo", DEBUG_LIVE_INFO},
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static once_flag init_once_flag = ONCE_FLAG_INIT;
53
debug_flags = parse_debug_string(getenv("ACO_DEBUG"), aco_debug_options);
56
/* enable some flags by default on debug builds */
57
debug_flags |= aco::DEBUG_VALIDATE_IR;
64
call_once(&init_once_flag, init_once);
68
init_program(Program* program, Stage stage, const struct radv_shader_info* info,
69
enum chip_class chip_class, enum radeon_family family, bool wgp_mode,
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ac_shader_config* config)
72
program->stage = stage;
73
program->config = config;
75
program->chip_class = chip_class;
76
if (family == CHIP_UNKNOWN) {
78
case GFX6: program->family = CHIP_TAHITI; break;
79
case GFX7: program->family = CHIP_BONAIRE; break;
80
case GFX8: program->family = CHIP_POLARIS10; break;
81
case GFX9: program->family = CHIP_VEGA10; break;
82
case GFX10: program->family = CHIP_NAVI10; break;
83
default: program->family = CHIP_UNKNOWN; break;
86
program->family = family;
88
program->wave_size = info->wave_size;
89
program->lane_mask = program->wave_size == 32 ? s1 : s2;
91
program->dev.lds_encoding_granule = chip_class >= GFX7 ? 512 : 256;
92
program->dev.lds_alloc_granule =
93
chip_class >= GFX10_3 ? 1024 : program->dev.lds_encoding_granule;
94
program->dev.lds_limit = chip_class >= GFX7 ? 65536 : 32768;
95
/* apparently gfx702 also has 16-bank LDS but I can't find a family for that */
96
program->dev.has_16bank_lds = family == CHIP_KABINI || family == CHIP_STONEY;
98
program->dev.vgpr_limit = 256;
99
program->dev.physical_vgprs = 256;
100
program->dev.vgpr_alloc_granule = 4;
102
if (chip_class >= GFX10) {
103
program->dev.physical_sgprs = 5120; /* doesn't matter as long as it's at least 128 * 40 */
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program->dev.physical_vgprs = program->wave_size == 32 ? 1024 : 512;
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program->dev.sgpr_alloc_granule = 128;
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program->dev.sgpr_limit =
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108; /* includes VCC, which can be treated as s[106-107] on GFX10+ */
108
if (chip_class >= GFX10_3)
109
program->dev.vgpr_alloc_granule = program->wave_size == 32 ? 16 : 8;
111
program->dev.vgpr_alloc_granule = program->wave_size == 32 ? 8 : 4;
112
} else if (program->chip_class >= GFX8) {
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program->dev.physical_sgprs = 800;
114
program->dev.sgpr_alloc_granule = 16;
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program->dev.sgpr_limit = 102;
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if (family == CHIP_TONGA || family == CHIP_ICELAND)
117
program->dev.sgpr_alloc_granule = 96; /* workaround hardware bug */
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program->dev.physical_sgprs = 512;
120
program->dev.sgpr_alloc_granule = 8;
121
program->dev.sgpr_limit = 104;
124
program->dev.max_wave64_per_simd = 10;
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if (program->chip_class >= GFX10_3)
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program->dev.max_wave64_per_simd = 16;
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else if (program->chip_class == GFX10)
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program->dev.max_wave64_per_simd = 20;
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else if (program->family >= CHIP_POLARIS10 && program->family <= CHIP_VEGAM)
130
program->dev.max_wave64_per_simd = 8;
132
program->dev.simd_per_cu = program->chip_class >= GFX10 ? 2 : 4;
134
switch (program->family) {
141
case CHIP_RENOIR: program->dev.xnack_enabled = true; break;
145
program->dev.sram_ecc_enabled = program->family == CHIP_ARCTURUS;
146
/* apparently gfx702 also has fast v_fma_f32 but I can't find a family for that */
147
program->dev.has_fast_fma32 = program->chip_class >= GFX9;
148
if (program->family == CHIP_TAHITI || program->family == CHIP_CARRIZO ||
149
program->family == CHIP_HAWAII)
150
program->dev.has_fast_fma32 = true;
151
program->dev.has_mac_legacy32 = program->chip_class <= GFX7 || program->chip_class >= GFX10;
153
program->dev.fused_mad_mix = program->chip_class >= GFX10;
154
if (program->family == CHIP_VEGA12 || program->family == CHIP_VEGA20 ||
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program->family == CHIP_ARCTURUS || program->family == CHIP_ALDEBARAN)
156
program->dev.fused_mad_mix = true;
158
program->wgp_mode = wgp_mode;
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program->progress = CompilationProgress::after_isel;
162
program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
163
program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
164
program->next_fp_mode.must_flush_denorms32 = false;
165
program->next_fp_mode.must_flush_denorms16_64 = false;
166
program->next_fp_mode.care_about_round32 = false;
167
program->next_fp_mode.care_about_round16_64 = false;
168
program->next_fp_mode.denorm16_64 = fp_denorm_keep;
169
program->next_fp_mode.denorm32 = 0;
170
program->next_fp_mode.round16_64 = fp_round_ne;
171
program->next_fp_mode.round32 = fp_round_ne;
175
get_sync_info(const Instruction* instr)
177
switch (instr->format) {
178
case Format::SMEM: return instr->smem().sync;
179
case Format::MUBUF: return instr->mubuf().sync;
180
case Format::MIMG: return instr->mimg().sync;
181
case Format::MTBUF: return instr->mtbuf().sync;
184
case Format::SCRATCH: return instr->flatlike().sync;
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case Format::DS: return instr->ds().sync;
186
default: return memory_sync_info();
191
can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_ra)
193
if (!instr->isVALU())
196
if (chip < GFX8 || instr->isDPP() || instr->isVOP3P())
202
if (instr->isVOP3()) {
203
VOP3_instruction& vop3 = instr->vop3();
204
if (instr->format == Format::VOP3)
206
if (vop3.clamp && instr->isVOPC() && chip != GFX8)
208
if (vop3.omod && chip < GFX9)
211
// TODO: return true if we know we will use vcc
212
if (!pre_ra && instr->definitions.size() >= 2)
215
for (unsigned i = 1; i < instr->operands.size(); i++) {
216
if (instr->operands[i].isLiteral())
218
if (chip < GFX9 && !instr->operands[i].isOfType(RegType::vgpr))
223
if (!instr->definitions.empty() && instr->definitions[0].bytes() > 4 && !instr->isVOPC())
226
if (!instr->operands.empty()) {
227
if (instr->operands[0].isLiteral())
229
if (chip < GFX9 && !instr->operands[0].isOfType(RegType::vgpr))
231
if (instr->operands[0].bytes() > 4)
233
if (instr->operands.size() > 1 && instr->operands[1].bytes() > 4)
237
bool is_mac = instr->opcode == aco_opcode::v_mac_f32 || instr->opcode == aco_opcode::v_mac_f16 ||
238
instr->opcode == aco_opcode::v_fmac_f32 || instr->opcode == aco_opcode::v_fmac_f16;
240
if (chip != GFX8 && is_mac)
243
// TODO: return true if we know we will use vcc
244
if (!pre_ra && instr->isVOPC() && chip == GFX8)
246
if (!pre_ra && instr->operands.size() >= 3 && !is_mac)
249
return instr->opcode != aco_opcode::v_madmk_f32 && instr->opcode != aco_opcode::v_madak_f32 &&
250
instr->opcode != aco_opcode::v_madmk_f16 && instr->opcode != aco_opcode::v_madak_f16 &&
251
instr->opcode != aco_opcode::v_readfirstlane_b32 &&
252
instr->opcode != aco_opcode::v_clrexcp && instr->opcode != aco_opcode::v_swap_b32;
255
/* updates "instr" and returns the old instruction (or NULL if no update was needed) */
257
convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& instr)
262
aco_ptr<Instruction> tmp = std::move(instr);
264
(Format)(((uint16_t)tmp->format & ~(uint16_t)Format::VOP3) | (uint16_t)Format::SDWA);
265
instr.reset(create_instruction<SDWA_instruction>(tmp->opcode, format, tmp->operands.size(),
266
tmp->definitions.size()));
267
std::copy(tmp->operands.cbegin(), tmp->operands.cend(), instr->operands.begin());
268
std::copy(tmp->definitions.cbegin(), tmp->definitions.cend(), instr->definitions.begin());
270
SDWA_instruction& sdwa = instr->sdwa();
273
VOP3_instruction& vop3 = tmp->vop3();
274
memcpy(sdwa.neg, vop3.neg, sizeof(sdwa.neg));
275
memcpy(sdwa.abs, vop3.abs, sizeof(sdwa.abs));
276
sdwa.omod = vop3.omod;
277
sdwa.clamp = vop3.clamp;
280
for (unsigned i = 0; i < instr->operands.size(); i++) {
281
/* SDWA only uses operands 0 and 1. */
285
sdwa.sel[i] = SubdwordSel(instr->operands[i].bytes(), 0, false);
288
sdwa.dst_sel = SubdwordSel(instr->definitions[0].bytes(), 0, false);
290
if (instr->definitions[0].getTemp().type() == RegType::sgpr && chip == GFX8)
291
instr->definitions[0].setFixed(vcc);
292
if (instr->definitions.size() >= 2)
293
instr->definitions[1].setFixed(vcc);
294
if (instr->operands.size() >= 3)
295
instr->operands[2].setFixed(vcc);
297
instr->pass_flags = tmp->pass_flags;
303
can_use_DPP(const aco_ptr<Instruction>& instr, bool pre_ra, bool dpp8)
305
assert(instr->isVALU() && !instr->operands.empty());
308
return instr->isDPP8() == dpp8;
310
if (instr->operands.size() && instr->operands[0].isLiteral())
316
if (!pre_ra && (instr->isVOPC() || instr->definitions.size() > 1) &&
317
instr->definitions.back().physReg() != vcc)
320
if (!pre_ra && instr->operands.size() >= 3 && instr->operands[2].physReg() != vcc)
323
if (instr->isVOP3()) {
324
const VOP3_instruction* vop3 = &instr->vop3();
325
if (vop3->clamp || vop3->omod || vop3->opsel)
329
if (instr->format == Format::VOP3)
331
if (instr->operands.size() > 1 && !instr->operands[1].isOfType(RegType::vgpr))
335
/* there are more cases but those all take 64-bit inputs */
336
return instr->opcode != aco_opcode::v_madmk_f32 && instr->opcode != aco_opcode::v_madak_f32 &&
337
instr->opcode != aco_opcode::v_madmk_f16 && instr->opcode != aco_opcode::v_madak_f16 &&
338
instr->opcode != aco_opcode::v_readfirstlane_b32 &&
339
instr->opcode != aco_opcode::v_cvt_f64_i32 &&
340
instr->opcode != aco_opcode::v_cvt_f64_f32 && instr->opcode != aco_opcode::v_cvt_f64_u32;
344
convert_to_DPP(aco_ptr<Instruction>& instr, bool dpp8)
349
aco_ptr<Instruction> tmp = std::move(instr);
350
Format format = (Format)(((uint32_t)tmp->format & ~(uint32_t)Format::VOP3) |
351
(dpp8 ? (uint32_t)Format::DPP8 : (uint32_t)Format::DPP16));
353
instr.reset(create_instruction<DPP8_instruction>(tmp->opcode, format, tmp->operands.size(),
354
tmp->definitions.size()));
356
instr.reset(create_instruction<DPP16_instruction>(tmp->opcode, format, tmp->operands.size(),
357
tmp->definitions.size()));
358
std::copy(tmp->operands.cbegin(), tmp->operands.cend(), instr->operands.begin());
359
for (unsigned i = 0; i < instr->definitions.size(); i++)
360
instr->definitions[i] = tmp->definitions[i];
363
DPP8_instruction* dpp = &instr->dpp8();
364
for (unsigned i = 0; i < 8; i++)
365
dpp->lane_sel[i] = i;
367
DPP16_instruction* dpp = &instr->dpp16();
368
dpp->dpp_ctrl = dpp_quad_perm(0, 1, 2, 3);
370
dpp->bank_mask = 0xf;
373
const VOP3_instruction* vop3 = &tmp->vop3();
374
memcpy(dpp->neg, vop3->neg, sizeof(dpp->neg));
375
memcpy(dpp->abs, vop3->abs, sizeof(dpp->abs));
379
if (instr->isVOPC() || instr->definitions.size() > 1)
380
instr->definitions.back().setFixed(vcc);
382
if (instr->operands.size() >= 3)
383
instr->operands[2].setFixed(vcc);
385
instr->pass_flags = tmp->pass_flags;
391
can_use_opsel(chip_class chip, aco_opcode op, int idx)
393
/* opsel is only GFX9+ */
398
case aco_opcode::v_div_fixup_f16:
399
case aco_opcode::v_fma_f16:
400
case aco_opcode::v_mad_f16:
401
case aco_opcode::v_mad_u16:
402
case aco_opcode::v_mad_i16:
403
case aco_opcode::v_med3_f16:
404
case aco_opcode::v_med3_i16:
405
case aco_opcode::v_med3_u16:
406
case aco_opcode::v_min3_f16:
407
case aco_opcode::v_min3_i16:
408
case aco_opcode::v_min3_u16:
409
case aco_opcode::v_max3_f16:
410
case aco_opcode::v_max3_i16:
411
case aco_opcode::v_max3_u16:
412
case aco_opcode::v_max_u16_e64:
413
case aco_opcode::v_max_i16_e64:
414
case aco_opcode::v_min_u16_e64:
415
case aco_opcode::v_min_i16_e64:
416
case aco_opcode::v_add_i16:
417
case aco_opcode::v_sub_i16:
418
case aco_opcode::v_add_u16_e64:
419
case aco_opcode::v_sub_u16_e64:
420
case aco_opcode::v_lshlrev_b16_e64:
421
case aco_opcode::v_lshrrev_b16_e64:
422
case aco_opcode::v_ashrrev_i16_e64:
423
case aco_opcode::v_mul_lo_u16_e64: return true;
424
case aco_opcode::v_pack_b32_f16:
425
case aco_opcode::v_cvt_pknorm_i16_f16:
426
case aco_opcode::v_cvt_pknorm_u16_f16: return idx != -1;
427
case aco_opcode::v_mad_u32_u16:
428
case aco_opcode::v_mad_i32_i16: return idx >= 0 && idx < 2;
429
default: return false;
434
instr_is_16bit(chip_class chip, aco_opcode op)
436
/* partial register writes are GFX9+, only */
442
case aco_opcode::v_mad_f16:
443
case aco_opcode::v_mad_u16:
444
case aco_opcode::v_mad_i16:
445
case aco_opcode::v_fma_f16:
446
case aco_opcode::v_div_fixup_f16:
447
case aco_opcode::v_interp_p2_f16:
448
case aco_opcode::v_fma_mixlo_f16:
450
case aco_opcode::v_mac_f16:
451
case aco_opcode::v_madak_f16:
452
case aco_opcode::v_madmk_f16: return chip >= GFX9;
453
case aco_opcode::v_add_f16:
454
case aco_opcode::v_sub_f16:
455
case aco_opcode::v_subrev_f16:
456
case aco_opcode::v_mul_f16:
457
case aco_opcode::v_max_f16:
458
case aco_opcode::v_min_f16:
459
case aco_opcode::v_ldexp_f16:
460
case aco_opcode::v_fmac_f16:
461
case aco_opcode::v_fmamk_f16:
462
case aco_opcode::v_fmaak_f16:
464
case aco_opcode::v_cvt_f16_f32:
465
case aco_opcode::v_cvt_f16_u16:
466
case aco_opcode::v_cvt_f16_i16:
467
case aco_opcode::v_rcp_f16:
468
case aco_opcode::v_sqrt_f16:
469
case aco_opcode::v_rsq_f16:
470
case aco_opcode::v_log_f16:
471
case aco_opcode::v_exp_f16:
472
case aco_opcode::v_frexp_mant_f16:
473
case aco_opcode::v_frexp_exp_i16_f16:
474
case aco_opcode::v_floor_f16:
475
case aco_opcode::v_ceil_f16:
476
case aco_opcode::v_trunc_f16:
477
case aco_opcode::v_rndne_f16:
478
case aco_opcode::v_fract_f16:
479
case aco_opcode::v_sin_f16:
480
case aco_opcode::v_cos_f16: return chip >= GFX10;
481
// TODO: confirm whether these write 16 or 32 bit on GFX10+
482
// case aco_opcode::v_cvt_u16_f16:
483
// case aco_opcode::v_cvt_i16_f16:
484
// case aco_opcode::p_cvt_f16_f32_rtne:
485
// case aco_opcode::v_cvt_norm_i16_f16:
486
// case aco_opcode::v_cvt_norm_u16_f16:
487
/* on GFX10, all opsel instructions preserve the high bits */
488
default: return chip >= GFX10 && can_use_opsel(chip, op, -1);
493
get_reduction_identity(ReduceOp op, unsigned idx)
514
case umax64: return 0;
518
case imul64: return idx ? 0 : 1;
519
case fmul16: return 0x3c00u; /* 1.0 */
520
case fmul32: return 0x3f800000u; /* 1.0 */
521
case fmul64: return idx ? 0x3ff00000u : 0u; /* 1.0 */
522
case imin8: return INT8_MAX;
523
case imin16: return INT16_MAX;
524
case imin32: return INT32_MAX;
525
case imin64: return idx ? 0x7fffffffu : 0xffffffffu;
526
case imax8: return INT8_MIN;
527
case imax16: return INT16_MIN;
528
case imax32: return INT32_MIN;
529
case imax64: return idx ? 0x80000000u : 0;
533
case iand16: return 0xffffffffu;
537
case iand64: return 0xffffffffu;
538
case fmin16: return 0x7c00u; /* infinity */
539
case fmin32: return 0x7f800000u; /* infinity */
540
case fmin64: return idx ? 0x7ff00000u : 0u; /* infinity */
541
case fmax16: return 0xfc00u; /* negative infinity */
542
case fmax32: return 0xff800000u; /* negative infinity */
543
case fmax64: return idx ? 0xfff00000u : 0u; /* negative infinity */
544
default: unreachable("Invalid reduction operation"); break;
550
needs_exec_mask(const Instruction* instr)
552
if (instr->isVALU()) {
553
return instr->opcode != aco_opcode::v_readlane_b32 &&
554
instr->opcode != aco_opcode::v_readlane_b32_e64 &&
555
instr->opcode != aco_opcode::v_writelane_b32 &&
556
instr->opcode != aco_opcode::v_writelane_b32_e64;
559
if (instr->isVMEM() || instr->isFlatLike())
562
if (instr->isSALU() || instr->isBranch() || instr->isSMEM() || instr->isBarrier())
563
return instr->reads_exec();
565
if (instr->isPseudo()) {
566
switch (instr->opcode) {
567
case aco_opcode::p_create_vector:
568
case aco_opcode::p_extract_vector:
569
case aco_opcode::p_split_vector:
570
case aco_opcode::p_phi:
571
case aco_opcode::p_parallelcopy:
572
for (Definition def : instr->definitions) {
573
if (def.getTemp().type() == RegType::vgpr)
576
return instr->reads_exec();
577
case aco_opcode::p_spill:
578
case aco_opcode::p_reload:
579
case aco_opcode::p_end_linear_vgpr:
580
case aco_opcode::p_logical_start:
581
case aco_opcode::p_logical_end:
582
case aco_opcode::p_startpgm: return instr->reads_exec();
592
aco_opcode unordered;
593
aco_opcode ordered_swapped;
594
aco_opcode unordered_swapped;
601
get_cmp_info(aco_opcode op, CmpInfo* info)
603
info->ordered = aco_opcode::num_opcodes;
604
info->unordered = aco_opcode::num_opcodes;
605
info->ordered_swapped = aco_opcode::num_opcodes;
606
info->unordered_swapped = aco_opcode::num_opcodes;
609
#define CMP2(ord, unord, ord_swap, unord_swap, sz) \
610
case aco_opcode::v_cmp_##ord##_f##sz: \
611
case aco_opcode::v_cmp_n##unord##_f##sz: \
612
info->ordered = aco_opcode::v_cmp_##ord##_f##sz; \
613
info->unordered = aco_opcode::v_cmp_n##unord##_f##sz; \
614
info->ordered_swapped = aco_opcode::v_cmp_##ord_swap##_f##sz; \
615
info->unordered_swapped = aco_opcode::v_cmp_n##unord_swap##_f##sz; \
616
info->inverse = op == aco_opcode::v_cmp_n##unord##_f##sz ? aco_opcode::v_cmp_##unord##_f##sz \
617
: aco_opcode::v_cmp_n##ord##_f##sz; \
618
info->f32 = op == aco_opcode::v_cmp_##ord##_f##sz ? aco_opcode::v_cmp_##ord##_f32 \
619
: aco_opcode::v_cmp_n##unord##_f32; \
622
#define CMP(ord, unord, ord_swap, unord_swap) \
623
CMP2(ord, unord, ord_swap, unord_swap, 16) \
624
CMP2(ord, unord, ord_swap, unord_swap, 32) \
625
CMP2(ord, unord, ord_swap, unord_swap, 64)
626
CMP(lt, /*n*/ge, gt, /*n*/le)
627
CMP(eq, /*n*/lg, eq, /*n*/lg)
628
CMP(le, /*n*/gt, ge, /*n*/lt)
629
CMP(gt, /*n*/le, lt, /*n*/le)
630
CMP(lg, /*n*/eq, lg, /*n*/eq)
631
CMP(ge, /*n*/lt, le, /*n*/gt)
634
#define ORD_TEST(sz) \
635
case aco_opcode::v_cmp_u_f##sz: \
636
info->f32 = aco_opcode::v_cmp_u_f32; \
637
info->inverse = aco_opcode::v_cmp_o_f##sz; \
640
case aco_opcode::v_cmp_o_f##sz: \
641
info->f32 = aco_opcode::v_cmp_o_f32; \
642
info->inverse = aco_opcode::v_cmp_u_f##sz; \
650
default: return false;
655
get_ordered(aco_opcode op)
658
return get_cmp_info(op, &info) ? info.ordered : aco_opcode::num_opcodes;
662
get_unordered(aco_opcode op)
665
return get_cmp_info(op, &info) ? info.unordered : aco_opcode::num_opcodes;
669
get_inverse(aco_opcode op)
672
return get_cmp_info(op, &info) ? info.inverse : aco_opcode::num_opcodes;
676
get_f32_cmp(aco_opcode op)
679
return get_cmp_info(op, &info) ? info.f32 : aco_opcode::num_opcodes;
683
get_cmp_bitsize(aco_opcode op)
686
return get_cmp_info(op, &info) ? info.size : 0;
690
is_cmp(aco_opcode op)
693
return get_cmp_info(op, &info) && info.ordered != aco_opcode::num_opcodes;
697
can_swap_operands(aco_ptr<Instruction>& instr, aco_opcode* new_op)
702
if (instr->operands[0].isConstant() ||
703
(instr->operands[0].isTemp() && instr->operands[0].getTemp().type() == RegType::sgpr))
706
switch (instr->opcode) {
707
case aco_opcode::v_add_u32:
708
case aco_opcode::v_add_co_u32:
709
case aco_opcode::v_add_co_u32_e64:
710
case aco_opcode::v_add_i32:
711
case aco_opcode::v_add_f16:
712
case aco_opcode::v_add_f32:
713
case aco_opcode::v_mul_f16:
714
case aco_opcode::v_mul_f32:
715
case aco_opcode::v_or_b32:
716
case aco_opcode::v_and_b32:
717
case aco_opcode::v_xor_b32:
718
case aco_opcode::v_max_f16:
719
case aco_opcode::v_max_f32:
720
case aco_opcode::v_min_f16:
721
case aco_opcode::v_min_f32:
722
case aco_opcode::v_max_i32:
723
case aco_opcode::v_min_i32:
724
case aco_opcode::v_max_u32:
725
case aco_opcode::v_min_u32:
726
case aco_opcode::v_max_i16:
727
case aco_opcode::v_min_i16:
728
case aco_opcode::v_max_u16:
729
case aco_opcode::v_min_u16:
730
case aco_opcode::v_max_i16_e64:
731
case aco_opcode::v_min_i16_e64:
732
case aco_opcode::v_max_u16_e64:
733
case aco_opcode::v_min_u16_e64: *new_op = instr->opcode; return true;
734
case aco_opcode::v_sub_f16: *new_op = aco_opcode::v_subrev_f16; return true;
735
case aco_opcode::v_sub_f32: *new_op = aco_opcode::v_subrev_f32; return true;
736
case aco_opcode::v_sub_co_u32: *new_op = aco_opcode::v_subrev_co_u32; return true;
737
case aco_opcode::v_sub_u16: *new_op = aco_opcode::v_subrev_u16; return true;
738
case aco_opcode::v_sub_u32: *new_op = aco_opcode::v_subrev_u32; return true;
741
get_cmp_info(instr->opcode, &info);
742
if (info.ordered == instr->opcode) {
743
*new_op = info.ordered_swapped;
746
if (info.unordered == instr->opcode) {
747
*new_op = info.unordered_swapped;
755
wait_imm::wait_imm() : vm(unset_counter), exp(unset_counter), lgkm(unset_counter), vs(unset_counter)
757
wait_imm::wait_imm(uint16_t vm_, uint16_t exp_, uint16_t lgkm_, uint16_t vs_)
758
: vm(vm_), exp(exp_), lgkm(lgkm_), vs(vs_)
761
wait_imm::wait_imm(enum chip_class chip, uint16_t packed) : vs(unset_counter)
765
vm |= (packed >> 10) & 0x30;
767
exp = (packed >> 4) & 0x7;
769
lgkm = (packed >> 8) & 0xf;
771
lgkm |= (packed >> 8) & 0x30;
775
wait_imm::pack(enum chip_class chip) const
778
assert(exp == unset_counter || exp <= 0x7);
782
assert(lgkm == unset_counter || lgkm <= 0x3f);
783
assert(vm == unset_counter || vm <= 0x3f);
784
imm = ((vm & 0x30) << 10) | ((lgkm & 0x3f) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
787
assert(lgkm == unset_counter || lgkm <= 0xf);
788
assert(vm == unset_counter || vm <= 0x3f);
789
imm = ((vm & 0x30) << 10) | ((lgkm & 0xf) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
792
assert(lgkm == unset_counter || lgkm <= 0xf);
793
assert(vm == unset_counter || vm <= 0xf);
794
imm = ((lgkm & 0xf) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
797
if (chip < GFX9 && vm == wait_imm::unset_counter)
798
imm |= 0xc000; /* should have no effect on pre-GFX9 and now we won't have to worry about the
799
architecture when interpreting the immediate */
800
if (chip < GFX10 && lgkm == wait_imm::unset_counter)
801
imm |= 0x3000; /* should have no effect on pre-GFX10 and now we won't have to worry about the
802
architecture when interpreting the immediate */
807
wait_imm::combine(const wait_imm& other)
809
bool changed = other.vm < vm || other.exp < exp || other.lgkm < lgkm || other.vs < vs;
810
vm = std::min(vm, other.vm);
811
exp = std::min(exp, other.exp);
812
lgkm = std::min(lgkm, other.lgkm);
813
vs = std::min(vs, other.vs);
818
wait_imm::empty() const
820
return vm == unset_counter && exp == unset_counter && lgkm == unset_counter &&
825
should_form_clause(const Instruction* a, const Instruction* b)
827
/* Vertex attribute loads from the same binding likely load from similar addresses */
828
unsigned a_vtx_binding =
829
a->isMUBUF() ? a->mubuf().vtx_binding : (a->isMTBUF() ? a->mtbuf().vtx_binding : 0);
830
unsigned b_vtx_binding =
831
b->isMUBUF() ? b->mubuf().vtx_binding : (b->isMTBUF() ? b->mtbuf().vtx_binding : 0);
832
if (a_vtx_binding && a_vtx_binding == b_vtx_binding)
835
if (a->format != b->format)
838
/* Assume loads which don't use descriptors might load from similar addresses. */
841
if (a->isSMEM() && a->operands[0].bytes() == 8 && b->operands[0].bytes() == 8)
844
/* If they load from the same descriptor, assume they might load from similar
847
if (a->isVMEM() || a->isSMEM())
848
return a->operands[0].tempId() == b->operands[0].tempId();