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* Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* Rob Clark <robclark@freedesktop.org>
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#include "pipe/p_state.h"
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#include "util/format/u_format.h"
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#include "util/u_helpers.h"
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#include "util/u_memory.h"
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#include "util/u_string.h"
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#include "util/u_viewport.h"
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#include "freedreno_query_hw.h"
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#include "freedreno_resource.h"
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#include "fd3_blend.h"
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#include "fd3_context.h"
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#include "fd3_format.h"
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#include "fd3_program.h"
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#include "fd3_rasterizer.h"
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#include "fd3_texture.h"
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#define emit_const_user fd3_emit_const_user
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#define emit_const_bo fd3_emit_const_bo
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#include "ir3_const.h"
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static const enum adreno_state_block sb[] = {
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[MESA_SHADER_VERTEX] = SB_VERT_SHADER,
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[MESA_SHADER_FRAGMENT] = SB_FRAG_SHADER,
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/* regid: base const register
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* prsc or dwords: buffer containing constant values
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* sizedwords: size of const value buffer
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fd3_emit_const_user(struct fd_ringbuffer *ring,
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const struct ir3_shader_variant *v, uint32_t regid,
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uint32_t sizedwords, const uint32_t *dwords)
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emit_const_asserts(ring, v, regid, sizedwords);
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OUT_PKT3(ring, CP_LOAD_STATE, 2 + sizedwords);
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OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid / 2) |
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CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
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CP_LOAD_STATE_0_STATE_BLOCK(sb[v->type]) |
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CP_LOAD_STATE_0_NUM_UNIT(sizedwords / 2));
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OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
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CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
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for (int i = 0; i < sizedwords; i++)
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OUT_RING(ring, dwords[i]);
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fd3_emit_const_bo(struct fd_ringbuffer *ring,
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const struct ir3_shader_variant *v, uint32_t regid,
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uint32_t offset, uint32_t sizedwords, struct fd_bo *bo)
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uint32_t dst_off = regid / 2;
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/* The blob driver aligns all const uploads dst_off to 64. We've been
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* successfully aligning to 8 vec4s as const_upload_unit so far with no
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assert(dst_off % 16 == 0);
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uint32_t num_unit = sizedwords / 2;
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assert(num_unit % 2 == 0);
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emit_const_asserts(ring, v, regid, sizedwords);
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OUT_PKT3(ring, CP_LOAD_STATE, 2);
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OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(dst_off) |
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CP_LOAD_STATE_0_STATE_SRC(SS_INDIRECT) |
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CP_LOAD_STATE_0_STATE_BLOCK(sb[v->type]) |
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CP_LOAD_STATE_0_NUM_UNIT(num_unit));
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OUT_RELOC(ring, bo, offset, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
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fd3_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type,
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uint32_t regid, uint32_t num, struct fd_bo **bos,
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uint32_t anum = align(num, 4);
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debug_assert((regid % 4) == 0);
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OUT_PKT3(ring, CP_LOAD_STATE, 2 + anum);
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OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid / 2) |
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CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
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CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
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CP_LOAD_STATE_0_NUM_UNIT(anum / 2));
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OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
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CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
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for (i = 0; i < num; i++) {
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OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
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OUT_RING(ring, 0xbad00000 | (i << 16));
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for (; i < anum; i++)
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OUT_RING(ring, 0xffffffff);
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is_stateobj(struct fd_ringbuffer *ring)
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emit_const_ptrs(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
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uint32_t dst_offset, uint32_t num, struct fd_bo **bos,
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/* TODO inline this */
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assert(dst_offset + num <= v->constlen * 4);
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fd3_emit_const_ptrs(ring, v->type, dst_offset, num, bos, offsets);
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#define VERT_TEX_OFF 0
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#define FRAG_TEX_OFF 16
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#define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
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emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
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enum adreno_state_block sb, struct fd_texture_stateobj *tex)
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static const unsigned tex_off[] = {
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[SB_VERT_TEX] = VERT_TEX_OFF,
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[SB_FRAG_TEX] = FRAG_TEX_OFF,
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static const enum adreno_state_block mipaddr[] = {
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[SB_VERT_TEX] = SB_VERT_MIPADDR,
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[SB_FRAG_TEX] = SB_FRAG_MIPADDR,
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static const uint32_t bcolor_reg[] = {
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[SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
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[SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
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struct fd3_context *fd3_ctx = fd3_context(ctx);
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bool needs_border = false;
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if (tex->num_samplers > 0) {
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/* output sampler state: */
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OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
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OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
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CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
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CP_LOAD_STATE_0_STATE_BLOCK(sb) |
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CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
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OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
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CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
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for (i = 0; i < tex->num_samplers; i++) {
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static const struct fd3_sampler_stateobj dummy_sampler = {};
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const struct fd3_sampler_stateobj *sampler =
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tex->samplers[i] ? fd3_sampler_stateobj(tex->samplers[i])
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OUT_RING(ring, sampler->texsamp0);
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OUT_RING(ring, sampler->texsamp1);
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needs_border |= sampler->needs_border;
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if (tex->num_textures > 0) {
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/* emit texture state: */
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OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
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OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
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CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
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CP_LOAD_STATE_0_STATE_BLOCK(sb) |
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CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
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OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
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CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
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for (i = 0; i < tex->num_textures; i++) {
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static const struct fd3_pipe_sampler_view dummy_view = {};
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const struct fd3_pipe_sampler_view *view =
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tex->textures[i] ? fd3_pipe_sampler_view(tex->textures[i])
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OUT_RING(ring, view->texconst0);
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OUT_RING(ring, view->texconst1);
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view->texconst2 | A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
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OUT_RING(ring, view->texconst3);
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OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
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CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
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CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
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CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
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CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
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OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
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CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
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for (i = 0; i < tex->num_textures; i++) {
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static const struct fd3_pipe_sampler_view dummy_view = {
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.base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
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.base.u.tex.first_level = 1,
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const struct fd3_pipe_sampler_view *view =
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tex->textures[i] ? fd3_pipe_sampler_view(tex->textures[i])
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struct fd_resource *rsc = fd_resource(view->base.texture);
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if (rsc && rsc->b.b.target == PIPE_BUFFER) {
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OUT_RELOC(ring, rsc->bo, view->base.u.buf.offset, 0, 0);
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unsigned start = fd_sampler_first_level(&view->base);
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unsigned end = fd_sampler_last_level(&view->base);
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for (j = 0; j < (end - start + 1); j++) {
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struct fdl_slice *slice = fd_resource_slice(rsc, j + start);
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OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
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/* pad the remaining entries w/ null: */
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for (; j < BASETABLE_SZ; j++) {
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OUT_RING(ring, 0x00000000);
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u_upload_alloc(fd3_ctx->border_color_uploader, 0,
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BORDER_COLOR_UPLOAD_SIZE, BORDER_COLOR_UPLOAD_SIZE, &off,
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&fd3_ctx->border_color_buf, &ptr);
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fd_setup_border_colors(tex, ptr, tex_off[sb]);
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OUT_PKT0(ring, bcolor_reg[sb], 1);
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OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
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u_upload_unmap(fd3_ctx->border_color_uploader);
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/* emit texture state for mem->gmem restore operation.. eventually it would
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* be good to get rid of this and use normal CSO/etc state for more of these
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* special cases, but for now the compiler is not sufficient..
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* Also, for using normal state, not quite sure how to handle the special
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* case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
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fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
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struct pipe_surface **psurf, int bufs)
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/* output sampler state: */
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OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
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OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
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CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
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CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
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CP_LOAD_STATE_0_NUM_UNIT(bufs));
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OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
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CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
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for (i = 0; i < bufs; i++) {
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OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
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A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
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A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
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A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
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A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
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OUT_RING(ring, 0x00000000);
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/* emit texture state: */
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OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
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OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
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CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
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CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
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CP_LOAD_STATE_0_NUM_UNIT(bufs));
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OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
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CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
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for (i = 0; i < bufs; i++) {
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OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
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A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
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A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
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A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
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A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
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OUT_RING(ring, 0x00000000);
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struct fd_resource *rsc = fd_resource(psurf[i]->texture);
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enum pipe_format format = fd_gmem_restore_format(psurf[i]->format);
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/* The restore blit_zs shader expects stencil in sampler 0, and depth
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if (rsc->stencil && i == 0) {
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format = fd_gmem_restore_format(rsc->b.b.format);
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/* note: PIPE_BUFFER disallowed for surfaces */
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unsigned lvl = psurf[i]->u.tex.level;
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debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
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OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
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A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
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A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
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fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
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PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
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OUT_RING(ring, A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
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A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
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OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc, lvl)) |
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A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
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OUT_RING(ring, 0x00000000);
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OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
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OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
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CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
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CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
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CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
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OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
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CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
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for (i = 0; i < bufs; i++) {
357
struct fd_resource *rsc = fd_resource(psurf[i]->texture);
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/* Matches above logic for blit_zs shader */
359
if (rsc->stencil && i == 0)
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unsigned lvl = psurf[i]->u.tex.level;
363
fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
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OUT_RELOC(ring, rsc->bo, offset, 0, 0);
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OUT_RING(ring, 0x00000000);
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/* pad the remaining entries w/ null: */
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for (j = 1; j < BASETABLE_SZ; j++) {
371
OUT_RING(ring, 0x00000000);
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fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
379
int32_t i, j, last = -1;
380
uint32_t total_in = 0;
381
const struct fd_vertex_state *vtx = emit->vtx;
382
const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
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unsigned vertex_regid = regid(63, 0);
384
unsigned instance_regid = regid(63, 0);
385
unsigned vtxcnt_regid = regid(63, 0);
387
/* Note that sysvals come *after* normal inputs: */
388
for (i = 0; i < vp->inputs_count; i++) {
389
if (!vp->inputs[i].compmask)
391
if (vp->inputs[i].sysval) {
392
switch (vp->inputs[i].slot) {
393
case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
394
vertex_regid = vp->inputs[i].regid;
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case SYSTEM_VALUE_INSTANCE_ID:
397
instance_regid = vp->inputs[i].regid;
399
case SYSTEM_VALUE_VERTEX_CNT:
400
vtxcnt_regid = vp->inputs[i].regid;
403
unreachable("invalid system value");
406
} else if (i < vtx->vtx->num_elements) {
411
for (i = 0, j = 0; i <= last; i++) {
412
assert(!vp->inputs[i].sysval);
413
if (vp->inputs[i].compmask) {
414
struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
415
const struct pipe_vertex_buffer *vb =
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&vtx->vertexbuf.vb[elem->vertex_buffer_index];
417
struct fd_resource *rsc = fd_resource(vb->buffer.resource);
418
enum pipe_format pfmt = elem->src_format;
419
enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
420
bool switchnext = (i != last) || (vertex_regid != regid(63, 0)) ||
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(instance_regid != regid(63, 0)) ||
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(vtxcnt_regid != regid(63, 0));
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bool isint = util_format_is_pure_integer(pfmt);
424
uint32_t off = vb->buffer_offset + elem->src_offset;
425
uint32_t fs = util_format_get_blocksize(pfmt);
427
debug_assert(fmt != VFMT_NONE);
429
OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
430
OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
431
A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
432
COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
433
A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
434
COND(elem->instance_divisor,
435
A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
436
A3XX_VFD_FETCH_INSTR_0_STEPRATE(
437
MAX2(1, elem->instance_divisor)));
438
OUT_RELOC(ring, rsc->bo, off, 0, 0);
440
OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
442
A3XX_VFD_DECODE_INSTR_CONSTFILL |
443
A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
444
A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
445
A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
446
A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
447
A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
448
A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
449
COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
450
COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
452
total_in += util_bitcount(vp->inputs[i].compmask);
457
/* hw doesn't like to be configured for zero vbo's, it seems: */
459
/* just recycle the shader bo, we just need to point to *something*
462
struct fd_bo *dummy_vbo = vp->bo;
463
bool switchnext = (vertex_regid != regid(63, 0)) ||
464
(instance_regid != regid(63, 0)) ||
465
(vtxcnt_regid != regid(63, 0));
467
OUT_PKT0(ring, REG_A3XX_VFD_FETCH(0), 2);
468
OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
469
A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
470
COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
471
A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
472
A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
473
OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
475
OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(0), 1);
476
OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
477
A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
478
A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM) |
479
A3XX_VFD_DECODE_INSTR_SWAP(XYZW) |
480
A3XX_VFD_DECODE_INSTR_REGID(regid(0, 0)) |
481
A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
482
A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
483
COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
489
OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
490
OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
491
A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
492
A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
493
A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
494
OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
495
A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
496
A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
498
OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
500
A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
501
A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
505
fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
506
struct fd3_emit *emit)
508
const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
509
const struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
510
const enum fd_dirty_3d_state dirty = emit->dirty;
512
emit_marker(ring, 5);
514
if (dirty & FD_DIRTY_SAMPLE_MASK) {
515
OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
516
OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
517
A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
518
A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
521
if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG |
522
FD_DIRTY_BLEND_DUAL)) &&
523
!emit->binning_pass) {
524
uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
525
fd3_blend_stateobj(ctx->blend)->rb_render_control;
527
val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
528
val |= COND(fp->fragcoord_compmask != 0,
529
A3XX_RB_RENDER_CONTROL_COORD_MASK(fp->fragcoord_compmask));
530
val |= COND(ctx->rasterizer->rasterizer_discard,
531
A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
533
/* I suppose if we needed to (which I don't *think* we need
534
* to), we could emit this for binning pass too. But we
535
* would need to keep a different patch-list for binning
539
OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
540
OUT_RINGP(ring, val, &ctx->batch->rbrc_patches);
543
if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
544
struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
545
struct pipe_stencil_ref *sr = &ctx->stencil_ref;
547
OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
548
OUT_RING(ring, zsa->rb_alpha_ref);
550
OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
551
OUT_RING(ring, zsa->rb_stencil_control);
553
OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
554
OUT_RING(ring, zsa->rb_stencilrefmask |
555
A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
556
OUT_RING(ring, zsa->rb_stencilrefmask_bf |
557
A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
560
if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
561
uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
562
if (fp->writes_pos) {
563
val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
564
val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
566
if (fp->no_earlyz || fp->has_kill) {
567
val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
569
if (!ctx->rasterizer->depth_clip_near) {
570
val |= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE;
572
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
576
if (dirty & FD_DIRTY_RASTERIZER) {
577
struct fd3_rasterizer_stateobj *rasterizer =
578
fd3_rasterizer_stateobj(ctx->rasterizer);
580
OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
581
OUT_RING(ring, rasterizer->gras_su_mode_control);
583
OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
584
OUT_RING(ring, rasterizer->gras_su_point_minmax);
585
OUT_RING(ring, rasterizer->gras_su_point_size);
587
OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
588
OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
589
OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
592
if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
594
fd3_rasterizer_stateobj(ctx->rasterizer)->gras_cl_clip_cntl;
595
uint8_t planes = ctx->rasterizer->clip_plane_enable;
597
ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL),
598
A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);
600
ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL),
601
A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER);
603
ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID),
604
A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID);
606
ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID),
607
A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID);
608
/* docs say enable at least one of IJ_PERSP_CENTER/CENTROID when fragcoord
610
val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRAG_COORD),
611
A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);
612
val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
614
COND(fp->fragcoord_compmask != 0,
615
A3XX_GRAS_CL_CLIP_CNTL_ZCOORD | A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
616
if (!emit->key.key.ucp_enables)
617
val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
618
MIN2(util_bitcount(planes), 6));
619
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
623
if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_UCP)) {
624
uint32_t planes = ctx->rasterizer->clip_plane_enable;
627
if (emit->key.key.ucp_enables)
630
while (planes && count < 6) {
631
int i = ffs(planes) - 1;
633
planes &= ~(1U << i);
634
fd_wfi(ctx->batch, ring);
635
OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
636
OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
637
OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
638
OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
639
OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
643
/* NOTE: since primitive_restart is not actually part of any
644
* state object, we need to make sure that we always emit
645
* PRIM_VTX_CNTL.. either that or be more clever and detect
649
const struct pipe_draw_info *info = emit->info;
650
uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)->pc_prim_vtx_cntl;
652
if (!emit->binning_pass) {
653
uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
654
if (stride_in_vpc > 0)
655
stride_in_vpc = MAX2(stride_in_vpc, 2);
656
val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
659
if (info->index_size && info->primitive_restart) {
660
val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
663
val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
665
OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
669
if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER | FD_DIRTY_VIEWPORT)) {
670
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
671
int minx = scissor->minx;
672
int miny = scissor->miny;
673
int maxx = scissor->maxx;
674
int maxy = scissor->maxy;
676
/* Unfortunately there is no separate depth clip disable, only an all
677
* or nothing deal. So when we disable clipping, we must handle the
678
* viewport clip via scissors.
680
if (!ctx->rasterizer->depth_clip_near) {
681
struct pipe_viewport_state *vp = &ctx->viewport;
682
minx = MAX2(minx, (int)floorf(vp->translate[0] - fabsf(vp->scale[0])));
683
miny = MAX2(miny, (int)floorf(vp->translate[1] - fabsf(vp->scale[1])));
684
maxx = MIN2(maxx, (int)ceilf(vp->translate[0] + fabsf(vp->scale[0])));
685
maxy = MIN2(maxy, (int)ceilf(vp->translate[1] + fabsf(vp->scale[1])));
688
OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
689
OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx) |
690
A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny));
691
OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx - 1) |
692
A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy - 1));
694
ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, minx);
695
ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, miny);
696
ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, maxx);
697
ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, maxy);
700
if (dirty & FD_DIRTY_VIEWPORT) {
701
fd_wfi(ctx->batch, ring);
702
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
704
A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5f));
705
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
707
A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5f));
708
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
709
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
710
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
714
(FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
717
if (ctx->batch->framebuffer.zsbuf) {
718
depth = util_format_get_component_bits(
719
pipe_surface_format(ctx->batch->framebuffer.zsbuf),
720
UTIL_FORMAT_COLORSPACE_ZS, 0);
722
util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
725
OUT_PKT0(ring, REG_A3XX_RB_Z_CLAMP_MIN, 2);
727
OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
728
OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
729
} else if (depth == 16) {
730
OUT_RING(ring, (uint32_t)(zmin * 0xffff));
731
OUT_RING(ring, (uint32_t)(zmax * 0xffff));
733
OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
734
OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
738
if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
739
struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
740
int nr_cbufs = pfb->nr_cbufs;
741
if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
742
A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
744
fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
747
/* TODO we should not need this or fd_wfi() before emit_constants():
749
OUT_PKT3(ring, CP_EVENT_WRITE, 1);
750
OUT_RING(ring, HLSQ_FLUSH);
752
if (!emit->skip_consts) {
753
ir3_emit_vs_consts(vp, ring, ctx, emit->info, emit->indirect, emit->draw);
754
if (!emit->binning_pass)
755
ir3_emit_fs_consts(fp, ring, ctx);
758
if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
759
struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
762
for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
763
enum pipe_format format =
764
pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
765
const struct util_format_description *desc =
766
util_format_description(format);
767
bool is_float = util_format_is_float(format);
768
bool is_int = util_format_is_pure_integer(format);
769
bool has_alpha = util_format_has_alpha(format);
770
uint32_t control = blend->rb_mrt[i].control;
773
control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
774
A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
775
control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
778
if (format == PIPE_FORMAT_NONE)
779
control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
782
control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
785
if (format && util_format_get_component_bits(
786
format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
787
const struct pipe_rt_blend_state *rt;
788
if (ctx->blend->independent_blend_enable)
789
rt = &ctx->blend->rt[i];
791
rt = &ctx->blend->rt[0];
793
if (!util_format_colormask_full(desc, rt->colormask))
794
control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
797
OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
798
OUT_RING(ring, control);
800
OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
802
blend->rb_mrt[i].blend_control |
803
COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
807
if (dirty & FD_DIRTY_BLEND_COLOR) {
808
struct pipe_blend_color *bcolor = &ctx->blend_color;
809
OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
810
OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(CLAMP(bcolor->color[0], 0.f, 1.f) * 0xff) |
811
A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
812
OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(CLAMP(bcolor->color[1], 0.f, 1.f) * 0xff) |
813
A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
814
OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(CLAMP(bcolor->color[2], 0.f, 1.f) * 0xff) |
815
A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
816
OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(CLAMP(bcolor->color[3], 0.f, 1.f) * 0xff) |
817
A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
820
if (dirty & FD_DIRTY_TEX)
821
fd_wfi(ctx->batch, ring);
823
if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
824
emit_textures(ctx, ring, SB_VERT_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
826
if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
827
emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
830
/* emit setup at begin of new cmdstream buffer (don't rely on previous
831
* state, there could have been a context switch between ioctls):
834
fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
836
struct fd_context *ctx = batch->ctx;
837
struct fd3_context *fd3_ctx = fd3_context(ctx);
840
if (ctx->screen->gpu_id == 320) {
841
OUT_PKT3(ring, CP_REG_RMW, 3);
842
OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
843
OUT_RING(ring, 0xfffcffff);
844
OUT_RING(ring, 0x00000000);
848
OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
849
OUT_RING(ring, 0x00007fff);
851
OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
852
OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
853
OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0, 0, 0); /* SP_VS_PVT_MEM_ADDR_REG */
854
OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
856
OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
857
OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
858
OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0, 0, 0); /* SP_FS_PVT_MEM_ADDR_REG */
859
OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
861
OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
862
OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
864
OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
865
OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
866
A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
867
A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
869
OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
870
OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
871
A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
872
A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
873
OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
875
OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
876
OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
877
A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
879
OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
880
OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
882
OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
883
OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
884
A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
885
A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ *
888
OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
889
OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
890
A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
891
A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ *
894
OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
895
OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
896
OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
898
OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
899
OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
901
OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
902
OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
904
OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
905
OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
907
OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
908
OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
910
OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
911
OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
913
OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
914
OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
915
A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
916
OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
917
A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
919
fd3_emit_cache_flush(batch, ring);
921
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
922
OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
924
OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
925
OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
926
OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
928
OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
929
OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
931
OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
932
OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) | A3XX_RB_WINDOW_OFFSET_Y(0));
934
OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
935
OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) | A3XX_RB_BLEND_RED_FLOAT(0.0f));
936
OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) | A3XX_RB_BLEND_GREEN_FLOAT(0.0f));
937
OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) | A3XX_RB_BLEND_BLUE_FLOAT(0.0f));
939
A3XX_RB_BLEND_ALPHA_UINT(0xff) | A3XX_RB_BLEND_ALPHA_FLOAT(1.0f));
941
for (i = 0; i < 6; i++) {
942
OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
943
OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
944
OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
945
OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
946
OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
949
OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
950
OUT_RING(ring, 0x00000000);
952
fd_event_write(batch, ring, CACHE_FLUSH);
954
if (is_a3xx_p0(ctx->screen)) {
955
OUT_PKT3(ring, CP_DRAW_INDX, 3);
956
OUT_RING(ring, 0x00000000);
957
OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX, INDEX_SIZE_IGN,
958
IGNORE_VISIBILITY, 0));
959
OUT_RING(ring, 0); /* NumIndices */
962
OUT_PKT3(ring, CP_NOP, 4);
963
OUT_RING(ring, 0x00000000);
964
OUT_RING(ring, 0x00000000);
965
OUT_RING(ring, 0x00000000);
966
OUT_RING(ring, 0x00000000);
970
fd_hw_query_enable(batch, ring);
974
fd3_emit_init_screen(struct pipe_screen *pscreen)
976
struct fd_screen *screen = fd_screen(pscreen);
977
screen->emit_ib = fd3_emit_ib;
981
fd3_emit_init(struct pipe_context *pctx)
added
removed
src/gallium/drivers/freedreno/a3xx/fd3_emit.c
