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Viewing changes to src/amd/vulkan/radv_meta_decompress.c

  • Committer: mmach
  • Date: 2022-09-22 19:56:13 UTC
  • Revision ID: netbit73@gmail.com-20220922195613-wtik9mmy20tmor0i
2022-09-22 21:17:09

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src/amd/vulkan/radv_meta_decompress.c
1
 
/*
2
 
 * Copyright © 2016 Intel Corporation
3
 
 *
4
 
 * Permission is hereby granted, free of charge, to any person obtaining a
5
 
 * copy of this software and associated documentation files (the "Software"),
6
 
 * to deal in the Software without restriction, including without limitation
7
 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
 
 * and/or sell copies of the Software, and to permit persons to whom the
9
 
 * Software is furnished to do so, subject to the following conditions:
10
 
 *
11
 
 * The above copyright notice and this permission notice (including the next
12
 
 * paragraph) shall be included in all copies or substantial portions of the
13
 
 * Software.
14
 
 *
15
 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18
 
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
 
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
 
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21
 
 * IN THE SOFTWARE.
22
 
 */
23
 
 
24
 
#include <assert.h>
25
 
#include <stdbool.h>
26
 
 
27
 
#include "radv_meta.h"
28
 
#include "radv_private.h"
29
 
#include "sid.h"
30
 
 
31
 
enum radv_depth_op {
32
 
   DEPTH_DECOMPRESS,
33
 
   DEPTH_RESUMMARIZE,
34
 
};
35
 
 
36
 
static nir_shader *
37
 
build_expand_depth_stencil_compute_shader(struct radv_device *dev)
38
 
{
39
 
   const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
40
 
 
41
 
   nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "expand_depth_stencil_compute");
42
 
 
43
 
   /* We need at least 8/8/1 to cover an entire HTILE block in a single workgroup. */
44
 
   b.shader->info.workgroup_size[0] = 8;
45
 
   b.shader->info.workgroup_size[1] = 8;
46
 
   nir_variable *input_img = nir_variable_create(b.shader, nir_var_image, img_type, "in_img");
47
 
   input_img->data.descriptor_set = 0;
48
 
   input_img->data.binding = 0;
49
 
 
50
 
   nir_variable *output_img = nir_variable_create(b.shader, nir_var_image, img_type, "out_img");
51
 
   output_img->data.descriptor_set = 0;
52
 
   output_img->data.binding = 1;
53
 
 
54
 
   nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
55
 
   nir_ssa_def *wg_id = nir_load_workgroup_id(&b, 32);
56
 
   nir_ssa_def *block_size =
57
 
      nir_imm_ivec4(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1],
58
 
                    b.shader->info.workgroup_size[2], 0);
59
 
 
60
 
   nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
61
 
 
62
 
   nir_ssa_def *data = nir_image_deref_load(
63
 
      &b, 4, 32, &nir_build_deref_var(&b, input_img)->dest.ssa, global_id, nir_ssa_undef(&b, 1, 32),
64
 
      nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_2D);
65
 
 
66
 
   /* We need a NIR_SCOPE_DEVICE memory_scope because ACO will avoid
67
 
    * creating a vmcnt(0) because it expects the L1 cache to keep memory
68
 
    * operations in-order for the same workgroup. The vmcnt(0) seems
69
 
    * necessary however. */
70
 
   nir_scoped_barrier(&b, .execution_scope = NIR_SCOPE_WORKGROUP, .memory_scope = NIR_SCOPE_DEVICE,
71
 
                      .memory_semantics = NIR_MEMORY_ACQ_REL, .memory_modes = nir_var_mem_ssbo);
72
 
 
73
 
   nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, global_id,
74
 
                         nir_ssa_undef(&b, 1, 32), data, nir_imm_int(&b, 0),
75
 
                         .image_dim = GLSL_SAMPLER_DIM_2D);
76
 
   return b.shader;
77
 
}
78
 
 
79
 
static VkResult
80
 
create_expand_depth_stencil_compute(struct radv_device *device)
81
 
{
82
 
   VkResult result = VK_SUCCESS;
83
 
   nir_shader *cs = build_expand_depth_stencil_compute_shader(device);
84
 
 
85
 
   VkDescriptorSetLayoutCreateInfo ds_create_info = {
86
 
      .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
87
 
      .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
88
 
      .bindingCount = 2,
89
 
      .pBindings = (VkDescriptorSetLayoutBinding[]){
90
 
         {.binding = 0,
91
 
          .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
92
 
          .descriptorCount = 1,
93
 
          .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
94
 
          .pImmutableSamplers = NULL},
95
 
         {.binding = 1,
96
 
          .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
97
 
          .descriptorCount = 1,
98
 
          .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
99
 
          .pImmutableSamplers = NULL},
100
 
      }};
101
 
 
102
 
   result = radv_CreateDescriptorSetLayout(
103
 
      radv_device_to_handle(device), &ds_create_info, &device->meta_state.alloc,
104
 
      &device->meta_state.expand_depth_stencil_compute_ds_layout);
105
 
   if (result != VK_SUCCESS)
106
 
      goto cleanup;
107
 
 
108
 
   VkPipelineLayoutCreateInfo pl_create_info = {
109
 
      .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
110
 
      .setLayoutCount = 1,
111
 
      .pSetLayouts = &device->meta_state.expand_depth_stencil_compute_ds_layout,
112
 
      .pushConstantRangeCount = 0,
113
 
      .pPushConstantRanges = NULL,
114
 
   };
115
 
 
116
 
   result = radv_CreatePipelineLayout(
117
 
      radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
118
 
      &device->meta_state.expand_depth_stencil_compute_p_layout);
119
 
   if (result != VK_SUCCESS)
120
 
      goto cleanup;
121
 
 
122
 
   /* compute shader */
123
 
 
124
 
   VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
125
 
      .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
126
 
      .stage = VK_SHADER_STAGE_COMPUTE_BIT,
127
 
      .module = vk_shader_module_handle_from_nir(cs),
128
 
      .pName = "main",
129
 
      .pSpecializationInfo = NULL,
130
 
   };
131
 
 
132
 
   VkComputePipelineCreateInfo vk_pipeline_info = {
133
 
      .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
134
 
      .stage = pipeline_shader_stage,
135
 
      .flags = 0,
136
 
      .layout = device->meta_state.expand_depth_stencil_compute_p_layout,
137
 
   };
138
 
 
139
 
   result = radv_CreateComputePipelines(
140
 
      radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
141
 
      &vk_pipeline_info, NULL,
142
 
      &device->meta_state.expand_depth_stencil_compute_pipeline);
143
 
   if (result != VK_SUCCESS)
144
 
      goto cleanup;
145
 
 
146
 
cleanup:
147
 
   ralloc_free(cs);
148
 
   return result;
149
 
}
150
 
 
151
 
static VkResult
152
 
create_pipeline_layout(struct radv_device *device, VkPipelineLayout *layout)
153
 
{
154
 
   VkPipelineLayoutCreateInfo pl_create_info = {
155
 
      .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
156
 
      .setLayoutCount = 0,
157
 
      .pSetLayouts = NULL,
158
 
      .pushConstantRangeCount = 0,
159
 
      .pPushConstantRanges = NULL,
160
 
   };
161
 
 
162
 
   return radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info,
163
 
                                    &device->meta_state.alloc, layout);
164
 
}
165
 
 
166
 
static VkResult
167
 
create_pipeline(struct radv_device *device, uint32_t samples, VkPipelineLayout layout,
168
 
                enum radv_depth_op op, VkPipeline *pipeline)
169
 
{
170
 
   VkResult result;
171
 
   VkDevice device_h = radv_device_to_handle(device);
172
 
 
173
 
   mtx_lock(&device->meta_state.mtx);
174
 
   if (*pipeline) {
175
 
      mtx_unlock(&device->meta_state.mtx);
176
 
      return VK_SUCCESS;
177
 
   }
178
 
 
179
 
   nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices();
180
 
   nir_shader *fs_module = radv_meta_build_nir_fs_noop();
181
 
 
182
 
   if (!vs_module || !fs_module) {
183
 
      /* XXX: Need more accurate error */
184
 
      result = VK_ERROR_OUT_OF_HOST_MEMORY;
185
 
      goto cleanup;
186
 
   }
187
 
 
188
 
   const VkPipelineSampleLocationsStateCreateInfoEXT sample_locs_create_info = {
189
 
      .sType = VK_STRUCTURE_TYPE_PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT,
190
 
      .sampleLocationsEnable = false,
191
 
   };
192
 
 
193
 
   const VkPipelineRenderingCreateInfo rendering_create_info = {
194
 
      .sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO,
195
 
      .depthAttachmentFormat = VK_FORMAT_D32_SFLOAT_S8_UINT,
196
 
      .stencilAttachmentFormat = VK_FORMAT_D32_SFLOAT_S8_UINT,
197
 
   };
198
 
 
199
 
   const VkGraphicsPipelineCreateInfo pipeline_create_info = {
200
 
      .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
201
 
      .pNext = &rendering_create_info,
202
 
      .stageCount = 2,
203
 
      .pStages =
204
 
         (VkPipelineShaderStageCreateInfo[]){
205
 
            {
206
 
               .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
207
 
               .stage = VK_SHADER_STAGE_VERTEX_BIT,
208
 
               .module = vk_shader_module_handle_from_nir(vs_module),
209
 
               .pName = "main",
210
 
            },
211
 
            {
212
 
               .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
213
 
               .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
214
 
               .module = vk_shader_module_handle_from_nir(fs_module),
215
 
               .pName = "main",
216
 
            },
217
 
         },
218
 
      .pVertexInputState =
219
 
         &(VkPipelineVertexInputStateCreateInfo){
220
 
            .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
221
 
            .vertexBindingDescriptionCount = 0,
222
 
            .vertexAttributeDescriptionCount = 0,
223
 
         },
224
 
      .pInputAssemblyState =
225
 
         &(VkPipelineInputAssemblyStateCreateInfo){
226
 
            .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
227
 
            .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
228
 
            .primitiveRestartEnable = false,
229
 
         },
230
 
      .pViewportState =
231
 
         &(VkPipelineViewportStateCreateInfo){
232
 
            .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
233
 
            .viewportCount = 1,
234
 
            .scissorCount = 1,
235
 
         },
236
 
      .pRasterizationState =
237
 
         &(VkPipelineRasterizationStateCreateInfo){
238
 
            .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
239
 
            .depthClampEnable = false,
240
 
            .rasterizerDiscardEnable = false,
241
 
            .polygonMode = VK_POLYGON_MODE_FILL,
242
 
            .cullMode = VK_CULL_MODE_NONE,
243
 
            .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
244
 
         },
245
 
      .pMultisampleState =
246
 
         &(VkPipelineMultisampleStateCreateInfo){
247
 
            .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
248
 
            .pNext = &sample_locs_create_info,
249
 
            .rasterizationSamples = samples,
250
 
            .sampleShadingEnable = false,
251
 
            .pSampleMask = NULL,
252
 
            .alphaToCoverageEnable = false,
253
 
            .alphaToOneEnable = false,
254
 
         },
255
 
      .pColorBlendState =
256
 
         &(VkPipelineColorBlendStateCreateInfo){
257
 
            .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
258
 
            .logicOpEnable = false,
259
 
            .attachmentCount = 0,
260
 
            .pAttachments = NULL,
261
 
         },
262
 
      .pDepthStencilState =
263
 
         &(VkPipelineDepthStencilStateCreateInfo){
264
 
            .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
265
 
            .depthTestEnable = false,
266
 
            .depthWriteEnable = false,
267
 
            .depthBoundsTestEnable = false,
268
 
            .stencilTestEnable = false,
269
 
         },
270
 
      .pDynamicState =
271
 
         &(VkPipelineDynamicStateCreateInfo){
272
 
            .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
273
 
            .dynamicStateCount = 3,
274
 
            .pDynamicStates =
275
 
               (VkDynamicState[]){
276
 
                  VK_DYNAMIC_STATE_VIEWPORT,
277
 
                  VK_DYNAMIC_STATE_SCISSOR,
278
 
                  VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT,
279
 
               },
280
 
         },
281
 
      .layout = layout,
282
 
      .renderPass = VK_NULL_HANDLE,
283
 
      .subpass = 0,
284
 
   };
285
 
 
286
 
   struct radv_graphics_pipeline_create_info extra = {
287
 
      .use_rectlist = true,
288
 
      .depth_compress_disable = true,
289
 
      .stencil_compress_disable = true,
290
 
      .resummarize_enable = op == DEPTH_RESUMMARIZE,
291
 
   };
292
 
 
293
 
   result = radv_graphics_pipeline_create(
294
 
      device_h, radv_pipeline_cache_to_handle(&device->meta_state.cache), &pipeline_create_info,
295
 
      &extra, &device->meta_state.alloc, pipeline);
296
 
 
297
 
cleanup:
298
 
   ralloc_free(fs_module);
299
 
   ralloc_free(vs_module);
300
 
   mtx_unlock(&device->meta_state.mtx);
301
 
   return result;
302
 
}
303
 
 
304
 
void
305
 
radv_device_finish_meta_depth_decomp_state(struct radv_device *device)
306
 
{
307
 
   struct radv_meta_state *state = &device->meta_state;
308
 
 
309
 
   for (uint32_t i = 0; i < ARRAY_SIZE(state->depth_decomp); ++i) {
310
 
      radv_DestroyPipelineLayout(radv_device_to_handle(device), state->depth_decomp[i].p_layout,
311
 
                                 &state->alloc);
312
 
 
313
 
      radv_DestroyPipeline(radv_device_to_handle(device),
314
 
                           state->depth_decomp[i].decompress_pipeline, &state->alloc);
315
 
      radv_DestroyPipeline(radv_device_to_handle(device),
316
 
                           state->depth_decomp[i].resummarize_pipeline, &state->alloc);
317
 
   }
318
 
 
319
 
   radv_DestroyPipeline(radv_device_to_handle(device),
320
 
                        state->expand_depth_stencil_compute_pipeline, &state->alloc);
321
 
   radv_DestroyPipelineLayout(radv_device_to_handle(device),
322
 
                              state->expand_depth_stencil_compute_p_layout, &state->alloc);
323
 
   radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
324
 
                                   state->expand_depth_stencil_compute_ds_layout, &state->alloc);
325
 
}
326
 
 
327
 
VkResult
328
 
radv_device_init_meta_depth_decomp_state(struct radv_device *device, bool on_demand)
329
 
{
330
 
   struct radv_meta_state *state = &device->meta_state;
331
 
   VkResult res = VK_SUCCESS;
332
 
 
333
 
   for (uint32_t i = 0; i < ARRAY_SIZE(state->depth_decomp); ++i) {
334
 
      uint32_t samples = 1 << i;
335
 
 
336
 
      res = create_pipeline_layout(device, &state->depth_decomp[i].p_layout);
337
 
      if (res != VK_SUCCESS)
338
 
         goto fail;
339
 
 
340
 
      if (on_demand)
341
 
         continue;
342
 
 
343
 
      res = create_pipeline(device, samples, state->depth_decomp[i].p_layout, DEPTH_DECOMPRESS,
344
 
                            &state->depth_decomp[i].decompress_pipeline);
345
 
      if (res != VK_SUCCESS)
346
 
         goto fail;
347
 
 
348
 
      res = create_pipeline(device, samples, state->depth_decomp[i].p_layout, DEPTH_RESUMMARIZE,
349
 
                            &state->depth_decomp[i].resummarize_pipeline);
350
 
      if (res != VK_SUCCESS)
351
 
         goto fail;
352
 
   }
353
 
 
354
 
   res = create_expand_depth_stencil_compute(device);
355
 
   if (res != VK_SUCCESS)
356
 
      goto fail;
357
 
 
358
 
   return VK_SUCCESS;
359
 
 
360
 
fail:
361
 
   radv_device_finish_meta_depth_decomp_state(device);
362
 
   return res;
363
 
}
364
 
 
365
 
static VkPipeline *
366
 
radv_get_depth_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
367
 
                        const VkImageSubresourceRange *subresourceRange, enum radv_depth_op op)
368
 
{
369
 
   struct radv_meta_state *state = &cmd_buffer->device->meta_state;
370
 
   uint32_t samples = image->info.samples;
371
 
   uint32_t samples_log2 = ffs(samples) - 1;
372
 
   VkPipeline *pipeline;
373
 
 
374
 
   if (!state->depth_decomp[samples_log2].decompress_pipeline) {
375
 
      VkResult ret;
376
 
 
377
 
      ret = create_pipeline(cmd_buffer->device, samples, state->depth_decomp[samples_log2].p_layout,
378
 
                            DEPTH_DECOMPRESS, &state->depth_decomp[samples_log2].decompress_pipeline);
379
 
      if (ret != VK_SUCCESS) {
380
 
         cmd_buffer->record_result = ret;
381
 
         return NULL;
382
 
      }
383
 
 
384
 
      ret = create_pipeline(cmd_buffer->device, samples, state->depth_decomp[samples_log2].p_layout,
385
 
                            DEPTH_RESUMMARIZE, &state->depth_decomp[samples_log2].resummarize_pipeline);
386
 
      if (ret != VK_SUCCESS) {
387
 
         cmd_buffer->record_result = ret;
388
 
         return NULL;
389
 
      }
390
 
   }
391
 
 
392
 
   switch (op) {
393
 
   case DEPTH_DECOMPRESS:
394
 
      pipeline = &state->depth_decomp[samples_log2].decompress_pipeline;
395
 
      break;
396
 
   case DEPTH_RESUMMARIZE:
397
 
      pipeline = &state->depth_decomp[samples_log2].resummarize_pipeline;
398
 
      break;
399
 
   default:
400
 
      unreachable("unknown operation");
401
 
   }
402
 
 
403
 
   return pipeline;
404
 
}
405
 
 
406
 
static void
407
 
radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
408
 
                               const VkImageSubresourceRange *range, int level, int layer)
409
 
{
410
 
   struct radv_device *device = cmd_buffer->device;
411
 
   struct radv_image_view iview;
412
 
   uint32_t width, height;
413
 
 
414
 
   width = radv_minify(image->info.width, range->baseMipLevel + level);
415
 
   height = radv_minify(image->info.height, range->baseMipLevel + level);
416
 
 
417
 
   radv_image_view_init(&iview, device,
418
 
                        &(VkImageViewCreateInfo){
419
 
                           .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
420
 
                           .image = radv_image_to_handle(image),
421
 
                           .viewType = radv_meta_get_view_type(image),
422
 
                           .format = image->vk_format,
423
 
                           .subresourceRange =
424
 
                              {
425
 
                                 .aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT,
426
 
                                 .baseMipLevel = range->baseMipLevel + level,
427
 
                                 .levelCount = 1,
428
 
                                 .baseArrayLayer = range->baseArrayLayer + layer,
429
 
                                 .layerCount = 1,
430
 
                              },
431
 
                        },
432
 
                        NULL);
433
 
 
434
 
   const VkRenderingAttachmentInfo depth_att = {
435
 
      .sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
436
 
      .imageView = radv_image_view_to_handle(&iview),
437
 
      .imageLayout = VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL,
438
 
      .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
439
 
      .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
440
 
   };
441
 
 
442
 
   const VkRenderingAttachmentInfo stencil_att = {
443
 
      .sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
444
 
      .imageView = radv_image_view_to_handle(&iview),
445
 
      .imageLayout = VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL,
446
 
      .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
447
 
      .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
448
 
   };
449
 
 
450
 
   const VkRenderingInfo rendering_info = {
451
 
      .sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
452
 
      .renderArea = {
453
 
         .offset = { 0, 0 },
454
 
         .extent = { width, height }
455
 
      },
456
 
      .layerCount = 1,
457
 
      .pDepthAttachment = &depth_att,
458
 
      .pStencilAttachment = &stencil_att,
459
 
   };
460
 
 
461
 
   radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
462
 
 
463
 
   radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
464
 
 
465
 
   radv_CmdEndRendering(radv_cmd_buffer_to_handle(cmd_buffer));
466
 
 
467
 
   radv_image_view_finish(&iview);
468
 
}
469
 
 
470
 
static void
471
 
radv_process_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
472
 
                           const VkImageSubresourceRange *subresourceRange,
473
 
                           struct radv_sample_locations_state *sample_locs, enum radv_depth_op op)
474
 
{
475
 
   struct radv_meta_saved_state saved_state;
476
 
   VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
477
 
   VkPipeline *pipeline;
478
 
 
479
 
   radv_meta_save(
480
 
      &saved_state, cmd_buffer,
481
 
      RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_SAMPLE_LOCATIONS | RADV_META_SAVE_PASS);
482
 
 
483
 
   pipeline = radv_get_depth_pipeline(cmd_buffer, image, subresourceRange, op);
484
 
 
485
 
   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_GRAPHICS,
486
 
                        *pipeline);
487
 
 
488
 
   if (sample_locs) {
489
 
      assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
490
 
 
491
 
      /* Set the sample locations specified during explicit or
492
 
       * automatic layout transitions, otherwise the depth decompress
493
 
       * pass uses the default HW locations.
494
 
       */
495
 
      radv_CmdSetSampleLocationsEXT(cmd_buffer_h,
496
 
                                    &(VkSampleLocationsInfoEXT){
497
 
                                       .sampleLocationsPerPixel = sample_locs->per_pixel,
498
 
                                       .sampleLocationGridSize = sample_locs->grid_size,
499
 
                                       .sampleLocationsCount = sample_locs->count,
500
 
                                       .pSampleLocations = sample_locs->locations,
501
 
                                    });
502
 
   }
503
 
 
504
 
   for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); ++l) {
505
 
 
506
 
      /* Do not decompress levels without HTILE. */
507
 
      if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l))
508
 
         continue;
509
 
 
510
 
      uint32_t width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l);
511
 
      uint32_t height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l);
512
 
 
513
 
      radv_CmdSetViewport(cmd_buffer_h, 0, 1,
514
 
                          &(VkViewport){.x = 0,
515
 
                                        .y = 0,
516
 
                                        .width = width,
517
 
                                        .height = height,
518
 
                                        .minDepth = 0.0f,
519
 
                                        .maxDepth = 1.0f});
520
 
 
521
 
      radv_CmdSetScissor(cmd_buffer_h, 0, 1,
522
 
                         &(VkRect2D){
523
 
                            .offset = {0, 0},
524
 
                            .extent = {width, height},
525
 
                         });
526
 
 
527
 
      for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
528
 
         radv_process_depth_image_layer(cmd_buffer, image, subresourceRange, l, s);
529
 
      }
530
 
   }
531
 
 
532
 
   radv_meta_restore(&saved_state, cmd_buffer);
533
 
}
534
 
 
535
 
static void
536
 
radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
537
 
                                  const VkImageSubresourceRange *subresourceRange)
538
 
{
539
 
   struct radv_meta_saved_state saved_state;
540
 
   struct radv_image_view load_iview = {0};
541
 
   struct radv_image_view store_iview = {0};
542
 
   struct radv_device *device = cmd_buffer->device;
543
 
 
544
 
   assert(radv_image_is_tc_compat_htile(image));
545
 
 
546
 
   cmd_buffer->state.flush_bits |=
547
 
      radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
548
 
 
549
 
   radv_meta_save(&saved_state, cmd_buffer,
550
 
                  RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE);
551
 
 
552
 
   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
553
 
                        device->meta_state.expand_depth_stencil_compute_pipeline);
554
 
 
555
 
   for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); l++) {
556
 
      uint32_t width, height;
557
 
 
558
 
      /* Do not decompress levels without HTILE. */
559
 
      if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l))
560
 
         continue;
561
 
 
562
 
      width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l);
563
 
      height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l);
564
 
 
565
 
      for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
566
 
         radv_image_view_init(
567
 
            &load_iview, cmd_buffer->device,
568
 
            &(VkImageViewCreateInfo){
569
 
               .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
570
 
               .image = radv_image_to_handle(image),
571
 
               .viewType = VK_IMAGE_VIEW_TYPE_2D,
572
 
               .format = image->vk_format,
573
 
               .subresourceRange = {.aspectMask = subresourceRange->aspectMask,
574
 
                                    .baseMipLevel = subresourceRange->baseMipLevel + l,
575
 
                                    .levelCount = 1,
576
 
                                    .baseArrayLayer = subresourceRange->baseArrayLayer + s,
577
 
                                    .layerCount = 1},
578
 
            },
579
 
            &(struct radv_image_view_extra_create_info){.enable_compression = true});
580
 
         radv_image_view_init(
581
 
            &store_iview, cmd_buffer->device,
582
 
            &(VkImageViewCreateInfo){
583
 
               .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
584
 
               .image = radv_image_to_handle(image),
585
 
               .viewType = VK_IMAGE_VIEW_TYPE_2D,
586
 
               .format = image->vk_format,
587
 
               .subresourceRange = {.aspectMask = subresourceRange->aspectMask,
588
 
                                    .baseMipLevel = subresourceRange->baseMipLevel + l,
589
 
                                    .levelCount = 1,
590
 
                                    .baseArrayLayer = subresourceRange->baseArrayLayer + s,
591
 
                                    .layerCount = 1},
592
 
            },
593
 
            &(struct radv_image_view_extra_create_info){.disable_compression = true});
594
 
 
595
 
         radv_meta_push_descriptor_set(
596
 
            cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
597
 
            device->meta_state.expand_depth_stencil_compute_p_layout, 0, /* set */
598
 
            2, /* descriptorWriteCount */
599
 
            (VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
600
 
                                      .dstBinding = 0,
601
 
                                      .dstArrayElement = 0,
602
 
                                      .descriptorCount = 1,
603
 
                                      .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
604
 
                                      .pImageInfo =
605
 
                                         (VkDescriptorImageInfo[]){
606
 
                                            {
607
 
                                               .sampler = VK_NULL_HANDLE,
608
 
                                               .imageView = radv_image_view_to_handle(&load_iview),
609
 
                                               .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
610
 
                                            },
611
 
                                         }},
612
 
                                     {.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
613
 
                                      .dstBinding = 1,
614
 
                                      .dstArrayElement = 0,
615
 
                                      .descriptorCount = 1,
616
 
                                      .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
617
 
                                      .pImageInfo = (VkDescriptorImageInfo[]){
618
 
                                         {
619
 
                                            .sampler = VK_NULL_HANDLE,
620
 
                                            .imageView = radv_image_view_to_handle(&store_iview),
621
 
                                            .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
622
 
                                         },
623
 
                                      }}});
624
 
 
625
 
         radv_unaligned_dispatch(cmd_buffer, width, height, 1);
626
 
 
627
 
         radv_image_view_finish(&load_iview);
628
 
         radv_image_view_finish(&store_iview);
629
 
      }
630
 
   }
631
 
 
632
 
   radv_meta_restore(&saved_state, cmd_buffer);
633
 
 
634
 
   cmd_buffer->state.flush_bits |=
635
 
      RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
636
 
      radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
637
 
 
638
 
   /* Initialize the HTILE metadata as "fully expanded". */
639
 
   uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, image);
640
 
 
641
 
   cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, image, subresourceRange, htile_value);
642
 
}
643
 
 
644
 
void
645
 
radv_expand_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
646
 
                          const VkImageSubresourceRange *subresourceRange,
647
 
                          struct radv_sample_locations_state *sample_locs)
648
 
{
649
 
   struct radv_barrier_data barrier = {0};
650
 
 
651
 
   barrier.layout_transitions.depth_stencil_expand = 1;
652
 
   radv_describe_layout_transition(cmd_buffer, &barrier);
653
 
 
654
 
   if (cmd_buffer->qf == RADV_QUEUE_GENERAL) {
655
 
      radv_process_depth_stencil(cmd_buffer, image, subresourceRange, sample_locs, DEPTH_DECOMPRESS);
656
 
   } else {
657
 
      radv_expand_depth_stencil_compute(cmd_buffer, image, subresourceRange);
658
 
   }
659
 
}
660
 
 
661
 
void
662
 
radv_resummarize_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
663
 
                               const VkImageSubresourceRange *subresourceRange,
664
 
                               struct radv_sample_locations_state *sample_locs)
665
 
{
666
 
   struct radv_barrier_data barrier = {0};
667
 
 
668
 
   barrier.layout_transitions.depth_stencil_resummarize = 1;
669
 
   radv_describe_layout_transition(cmd_buffer, &barrier);
670
 
 
671
 
   assert(cmd_buffer->qf == RADV_QUEUE_GENERAL);
672
 
   radv_process_depth_stencil(cmd_buffer, image, subresourceRange, sample_locs, DEPTH_RESUMMARIZE);
673
 
}