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* Copyright 2010 Christoph Bumiller
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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#include "pipe/p_defines.h"
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#include "util/u_framebuffer.h"
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#include "util/u_helpers.h"
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#include "util/u_inlines.h"
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#include "util/u_transfer.h"
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#include "tgsi/tgsi_parse.h"
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#include "compiler/nir/nir.h"
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#include "compiler/nir/nir_serialize.h"
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#include "nvc0/nvc0_stateobj.h"
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#include "nvc0/nvc0_context.h"
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#include "nvc0/nvc0_query_hw.h"
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#include "nvc0/nvc0_3d.xml.h"
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#include "nouveau_gldefs.h"
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static inline uint32_t
42
nvc0_colormask(unsigned mask)
46
if (mask & PIPE_MASK_R)
48
if (mask & PIPE_MASK_G)
50
if (mask & PIPE_MASK_B)
52
if (mask & PIPE_MASK_A)
58
#define NVC0_BLEND_FACTOR_CASE(a, b) \
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case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
61
static inline uint32_t
62
nvc0_blend_fac(unsigned factor)
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NVC0_BLEND_FACTOR_CASE(ONE, ONE);
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NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
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NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
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NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
69
NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
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NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
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NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
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NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
73
NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
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NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
75
NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
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NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
77
NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
78
NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
79
NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
80
NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
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NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
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NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
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NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
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return NV50_BLEND_FACTOR_ZERO;
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nvc0_blend_state_create(struct pipe_context *pipe,
91
const struct pipe_blend_state *cso)
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struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
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int r; /* reference */
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bool indep_masks = false;
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bool indep_funcs = false;
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/* check which states actually have differing values */
104
if (cso->independent_blend_enable) {
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for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
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for (i = r + 1; i < 8; ++i) {
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if (!cso->rt[i].blend_enable)
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if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
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cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
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cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
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cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
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cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
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cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
122
blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
124
for (i = 1; i < 8; ++i) {
125
if (cso->rt[i].colormask != cso->rt[0].colormask) {
132
if (cso->rt[0].blend_enable)
136
if (cso->logicop_enable) {
137
SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
139
SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
141
SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
143
SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
145
SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
146
SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
148
for (i = 0; i < 8; ++i) {
149
if (cso->rt[i].blend_enable) {
150
SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
151
SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
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SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
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SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
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SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
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SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
156
SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
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SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
162
SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
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SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
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SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
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SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
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SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
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SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
168
SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
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SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
173
SB_BEGIN_3D(so, COLOR_MASK(0), 8);
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for (i = 0; i < 8; ++i)
175
SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
177
SB_BEGIN_3D(so, COLOR_MASK(0), 1);
178
SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
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if (cso->alpha_to_coverage)
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ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
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if (cso->alpha_to_one)
186
ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
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SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
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assert(so->size <= ARRAY_SIZE(so->state));
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nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
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struct nvc0_context *nvc0 = nvc0_context(pipe);
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nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
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nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
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/* NOTE: ignoring line_last_pixel */
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nvc0_rasterizer_state_create(struct pipe_context *pipe,
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const struct pipe_rasterizer_state *cso)
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struct nvc0_rasterizer_stateobj *so;
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uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
219
so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
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/* Scissor enables are handled in scissor state, we will not want to
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* always emit 16 commands, one for each scissor rectangle, here.
228
SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
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SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
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SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
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SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
233
SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
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SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
237
SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
238
if (cso->line_smooth || cso->multisample)
239
SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
241
SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
242
SB_DATA (so, fui(cso->line_width));
244
SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
245
if (cso->line_stipple_enable) {
246
SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
247
SB_DATA (so, (cso->line_stipple_pattern << 8) |
248
cso->line_stipple_factor);
252
SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
253
if (!cso->point_size_per_vertex) {
254
SB_BEGIN_3D(so, POINT_SIZE, 1);
255
SB_DATA (so, fui(cso->point_size));
258
reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
259
NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
260
NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
262
SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
263
SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
264
SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
265
SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
267
if (class_3d >= GM200_3D_CLASS) {
268
SB_IMMED_3D(so, FILL_RECTANGLE,
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cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
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NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
273
SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
274
SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
275
SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
276
SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
277
SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
279
SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
280
SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
281
SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
282
NVC0_3D_FRONT_FACE_CW);
283
switch (cso->cull_face) {
284
case PIPE_FACE_FRONT_AND_BACK:
285
SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
287
case PIPE_FACE_FRONT:
288
SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
292
SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
296
SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
297
SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
298
SB_DATA (so, cso->offset_point);
299
SB_DATA (so, cso->offset_line);
300
SB_DATA (so, cso->offset_tri);
302
if (cso->offset_point || cso->offset_line || cso->offset_tri) {
303
SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
304
SB_DATA (so, fui(cso->offset_scale));
305
if (!cso->offset_units_unscaled) {
306
SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
307
SB_DATA (so, fui(cso->offset_units * 2.0f));
309
SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
310
SB_DATA (so, fui(cso->offset_clamp));
313
if (cso->depth_clip_near)
314
reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
317
NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
318
NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
319
NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
320
NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
322
SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
325
SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
327
SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
329
if (class_3d >= GM200_3D_CLASS) {
330
if (cso->conservative_raster_mode != PIPE_CONSERVATIVE_RASTER_OFF) {
331
bool post_snap = cso->conservative_raster_mode ==
332
PIPE_CONSERVATIVE_RASTER_POST_SNAP;
333
uint32_t state = cso->subpixel_precision_x;
334
state |= cso->subpixel_precision_y << 4;
335
state |= (uint32_t)(cso->conservative_raster_dilate * 4) << 8;
336
state |= (post_snap || class_3d < GP100_3D_CLASS) ? 1 << 10 : 0;
337
SB_IMMED_3D(so, MACRO_CONSERVATIVE_RASTER_STATE, state);
339
SB_IMMED_3D(so, CONSERVATIVE_RASTER, 0);
343
assert(so->size <= ARRAY_SIZE(so->state));
348
nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
350
struct nvc0_context *nvc0 = nvc0_context(pipe);
353
nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
357
nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
363
nvc0_zsa_state_create(struct pipe_context *pipe,
364
const struct pipe_depth_stencil_alpha_state *cso)
366
struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
370
SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth_enabled);
371
if (cso->depth_enabled) {
372
SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth_writemask);
373
SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
374
SB_DATA (so, nvgl_comparison_op(cso->depth_func));
377
SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth_bounds_test);
378
if (cso->depth_bounds_test) {
379
SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
380
SB_DATA (so, fui(cso->depth_bounds_min));
381
SB_DATA (so, fui(cso->depth_bounds_max));
384
if (cso->stencil[0].enabled) {
385
SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
387
SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
388
SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
389
SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
390
SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
391
SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
392
SB_DATA (so, cso->stencil[0].valuemask);
393
SB_DATA (so, cso->stencil[0].writemask);
395
SB_IMMED_3D(so, STENCIL_ENABLE, 0);
398
if (cso->stencil[1].enabled) {
399
assert(cso->stencil[0].enabled);
400
SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
402
SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
403
SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
404
SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
405
SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
406
SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
407
SB_DATA (so, cso->stencil[1].writemask);
408
SB_DATA (so, cso->stencil[1].valuemask);
410
if (cso->stencil[0].enabled) {
411
SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
414
SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha_enabled);
415
if (cso->alpha_enabled) {
416
SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
417
SB_DATA (so, fui(cso->alpha_ref_value));
418
SB_DATA (so, nvgl_comparison_op(cso->alpha_func));
421
assert(so->size <= ARRAY_SIZE(so->state));
426
nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
428
struct nvc0_context *nvc0 = nvc0_context(pipe);
431
nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
435
nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
440
/* ====================== SAMPLERS AND TEXTURES ================================
443
#define NV50_TSC_WRAP_CASE(n) \
444
case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
447
nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
451
for (s = 0; s < 6; ++s)
452
for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
453
if (nvc0_context(pipe)->samplers[s][i] == hwcso)
454
nvc0_context(pipe)->samplers[s][i] = NULL;
456
nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
462
nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
464
unsigned nr, void **hwcsos)
466
unsigned highest_found = 0;
469
for (i = 0; i < nr; ++i) {
470
struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
471
struct nv50_tsc_entry *old = nvc0->samplers[s][i];
478
nvc0->samplers_dirty[s] |= 1 << i;
480
nvc0->samplers[s][i] = hwcso;
482
nvc0_screen_tsc_unlock(nvc0->screen, old);
484
if (nr >= nvc0->num_samplers[s])
485
nvc0->num_samplers[s] = highest_found + 1;
489
nvc0_bind_sampler_states(struct pipe_context *pipe,
490
enum pipe_shader_type shader,
491
unsigned start, unsigned nr, void **samplers)
493
const unsigned s = nvc0_shader_stage(shader);
496
nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers);
499
nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
501
nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
505
/* NOTE: only called when not referenced anywhere, won't be bound */
507
nvc0_sampler_view_destroy(struct pipe_context *pipe,
508
struct pipe_sampler_view *view)
510
pipe_resource_reference(&view->texture, NULL);
512
nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
514
FREE(nv50_tic_entry(view));
518
nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
519
unsigned nr, bool take_ownership,
520
struct pipe_sampler_view **views)
524
for (i = 0; i < nr; ++i) {
525
struct pipe_sampler_view *view = views ? views[i] : NULL;
526
struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
528
if (view == nvc0->textures[s][i]) {
530
pipe_sampler_view_reference(&view, NULL);
533
nvc0->textures_dirty[s] |= 1 << i;
535
if (view && view->texture) {
536
struct pipe_resource *res = view->texture;
537
if (res->target == PIPE_BUFFER &&
538
(res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
539
nvc0->textures_coherent[s] |= 1 << i;
541
nvc0->textures_coherent[s] &= ~(1 << i);
543
nvc0->textures_coherent[s] &= ~(1 << i);
548
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
550
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
551
nvc0_screen_tic_unlock(nvc0->screen, old);
554
if (take_ownership) {
555
pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
556
nvc0->textures[s][i] = view;
558
pipe_sampler_view_reference(&nvc0->textures[s][i], view);
562
for (i = nr; i < nvc0->num_textures[s]; ++i) {
563
struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
566
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
568
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
569
nvc0_screen_tic_unlock(nvc0->screen, old);
570
pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
574
nvc0->num_textures[s] = nr;
578
nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
579
unsigned start, unsigned nr,
580
unsigned unbind_num_trailing_slots,
582
struct pipe_sampler_view **views)
584
const unsigned s = nvc0_shader_stage(shader);
587
nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, take_ownership, views);
590
nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
592
nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES;
595
/* ============================= SHADERS =======================================
599
nvc0_sp_state_create(struct pipe_context *pipe,
600
const struct pipe_shader_state *cso, unsigned type)
602
struct nvc0_program *prog;
604
prog = CALLOC_STRUCT(nvc0_program);
609
prog->pipe.type = cso->type;
612
case PIPE_SHADER_IR_TGSI:
613
prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
615
case PIPE_SHADER_IR_NIR:
616
prog->pipe.ir.nir = cso->ir.nir;
619
assert(!"unsupported IR!");
624
if (cso->stream_output.num_outputs)
625
prog->pipe.stream_output = cso->stream_output;
627
prog->translated = nvc0_program_translate(
628
prog, nvc0_context(pipe)->screen->base.device->chipset,
629
nvc0_context(pipe)->screen->base.disk_shader_cache,
630
&nouveau_context(pipe)->debug);
636
nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
638
struct nvc0_program *prog = (struct nvc0_program *)hwcso;
640
nvc0_program_destroy(nvc0_context(pipe), prog);
642
if (prog->pipe.type == PIPE_SHADER_IR_TGSI)
643
FREE((void *)prog->pipe.tokens);
644
else if (prog->pipe.type == PIPE_SHADER_IR_NIR)
645
ralloc_free(prog->pipe.ir.nir);
650
nvc0_vp_state_create(struct pipe_context *pipe,
651
const struct pipe_shader_state *cso)
653
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
657
nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
659
struct nvc0_context *nvc0 = nvc0_context(pipe);
661
nvc0->vertprog = hwcso;
662
nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
666
nvc0_fp_state_create(struct pipe_context *pipe,
667
const struct pipe_shader_state *cso)
669
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
673
nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
675
struct nvc0_context *nvc0 = nvc0_context(pipe);
677
nvc0->fragprog = hwcso;
678
nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
682
nvc0_gp_state_create(struct pipe_context *pipe,
683
const struct pipe_shader_state *cso)
685
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
689
nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
691
struct nvc0_context *nvc0 = nvc0_context(pipe);
693
nvc0->gmtyprog = hwcso;
694
nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
698
nvc0_tcp_state_create(struct pipe_context *pipe,
699
const struct pipe_shader_state *cso)
701
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
705
nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
707
struct nvc0_context *nvc0 = nvc0_context(pipe);
709
nvc0->tctlprog = hwcso;
710
nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
714
nvc0_tep_state_create(struct pipe_context *pipe,
715
const struct pipe_shader_state *cso)
717
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
721
nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
723
struct nvc0_context *nvc0 = nvc0_context(pipe);
725
nvc0->tevlprog = hwcso;
726
nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
730
nvc0_cp_state_create(struct pipe_context *pipe,
731
const struct pipe_compute_state *cso)
733
struct nvc0_program *prog;
735
prog = CALLOC_STRUCT(nvc0_program);
738
prog->type = PIPE_SHADER_COMPUTE;
739
prog->pipe.type = cso->ir_type;
741
prog->cp.smem_size = cso->req_local_mem;
742
prog->cp.lmem_size = cso->req_private_mem;
743
prog->parm_size = cso->req_input_mem;
745
switch(cso->ir_type) {
746
case PIPE_SHADER_IR_TGSI:
747
prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
749
case PIPE_SHADER_IR_NIR:
750
prog->pipe.ir.nir = (nir_shader *)cso->prog;
752
case PIPE_SHADER_IR_NIR_SERIALIZED: {
753
struct blob_reader reader;
754
const struct pipe_binary_program_header *hdr = cso->prog;
756
blob_reader_init(&reader, hdr->blob, hdr->num_bytes);
757
prog->pipe.ir.nir = nir_deserialize(NULL, pipe->screen->get_compiler_options(pipe->screen, PIPE_SHADER_IR_NIR, PIPE_SHADER_COMPUTE), &reader);
758
prog->pipe.type = PIPE_SHADER_IR_NIR;
762
assert(!"unsupported IR!");
767
prog->translated = nvc0_program_translate(
768
prog, nvc0_context(pipe)->screen->base.device->chipset,
769
nvc0_context(pipe)->screen->base.disk_shader_cache,
770
&nouveau_context(pipe)->debug);
776
nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
778
struct nvc0_context *nvc0 = nvc0_context(pipe);
780
nvc0->compprog = hwcso;
781
nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
785
nvc0_set_constant_buffer(struct pipe_context *pipe,
786
enum pipe_shader_type shader, uint index,
788
const struct pipe_constant_buffer *cb)
790
struct nvc0_context *nvc0 = nvc0_context(pipe);
791
struct pipe_resource *res = cb ? cb->buffer : NULL;
792
const unsigned s = nvc0_shader_stage(shader);
793
const unsigned i = index;
795
if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
796
if (nvc0->constbuf[s][i].user)
797
nvc0->constbuf[s][i].u.buf = NULL;
799
if (nvc0->constbuf[s][i].u.buf)
800
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
802
nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
804
if (nvc0->constbuf[s][i].user)
805
nvc0->constbuf[s][i].u.buf = NULL;
807
if (nvc0->constbuf[s][i].u.buf)
808
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
810
nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
812
nvc0->constbuf_dirty[s] |= 1 << i;
814
if (nvc0->constbuf[s][i].u.buf)
815
nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
817
if (take_ownership) {
818
pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, NULL);
819
nvc0->constbuf[s][i].u.buf = res;
821
pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
824
nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
825
if (nvc0->constbuf[s][i].user) {
826
nvc0->constbuf[s][i].u.data = cb->user_buffer;
827
nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
828
nvc0->constbuf_valid[s] |= 1 << i;
829
nvc0->constbuf_coherent[s] &= ~(1 << i);
832
nvc0->constbuf[s][i].offset = cb->buffer_offset;
833
nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
834
nvc0->constbuf_valid[s] |= 1 << i;
835
if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
836
nvc0->constbuf_coherent[s] |= 1 << i;
838
nvc0->constbuf_coherent[s] &= ~(1 << i);
841
nvc0->constbuf_valid[s] &= ~(1 << i);
842
nvc0->constbuf_coherent[s] &= ~(1 << i);
846
/* =============================================================================
850
nvc0_set_blend_color(struct pipe_context *pipe,
851
const struct pipe_blend_color *bcol)
853
struct nvc0_context *nvc0 = nvc0_context(pipe);
855
nvc0->blend_colour = *bcol;
856
nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
860
nvc0_set_stencil_ref(struct pipe_context *pipe,
861
const struct pipe_stencil_ref sr)
863
struct nvc0_context *nvc0 = nvc0_context(pipe);
865
nvc0->stencil_ref = sr;
866
nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
870
nvc0_set_clip_state(struct pipe_context *pipe,
871
const struct pipe_clip_state *clip)
873
struct nvc0_context *nvc0 = nvc0_context(pipe);
875
memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
877
nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
881
nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
883
struct nvc0_context *nvc0 = nvc0_context(pipe);
885
nvc0->sample_mask = sample_mask;
886
nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
890
nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
892
struct nvc0_context *nvc0 = nvc0_context(pipe);
894
if (nvc0->min_samples != min_samples) {
895
nvc0->min_samples = min_samples;
896
nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
901
nvc0_set_framebuffer_state(struct pipe_context *pipe,
902
const struct pipe_framebuffer_state *fb)
904
struct nvc0_context *nvc0 = nvc0_context(pipe);
906
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
908
util_copy_framebuffer_state(&nvc0->framebuffer, fb);
910
nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SAMPLE_LOCATIONS |
911
NVC0_NEW_3D_TEXTURES;
912
nvc0->dirty_cp |= NVC0_NEW_CP_TEXTURES;
916
nvc0_set_sample_locations(struct pipe_context *pipe,
917
size_t size, const uint8_t *locations)
919
struct nvc0_context *nvc0 = nvc0_context(pipe);
921
nvc0->sample_locations_enabled = size && locations;
922
if (size > sizeof(nvc0->sample_locations))
923
size = sizeof(nvc0->sample_locations);
924
memcpy(nvc0->sample_locations, locations, size);
926
nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_LOCATIONS;
930
nvc0_set_polygon_stipple(struct pipe_context *pipe,
931
const struct pipe_poly_stipple *stipple)
933
struct nvc0_context *nvc0 = nvc0_context(pipe);
935
nvc0->stipple = *stipple;
936
nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
940
nvc0_set_scissor_states(struct pipe_context *pipe,
942
unsigned num_scissors,
943
const struct pipe_scissor_state *scissor)
945
struct nvc0_context *nvc0 = nvc0_context(pipe);
948
assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
949
for (i = 0; i < num_scissors; i++) {
950
if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
952
nvc0->scissors[start_slot + i] = scissor[i];
953
nvc0->scissors_dirty |= 1 << (start_slot + i);
954
nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
959
nvc0_set_viewport_states(struct pipe_context *pipe,
961
unsigned num_viewports,
962
const struct pipe_viewport_state *vpt)
964
struct nvc0_context *nvc0 = nvc0_context(pipe);
967
assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
968
for (i = 0; i < num_viewports; i++) {
969
if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
971
nvc0->viewports[start_slot + i] = vpt[i];
972
nvc0->viewports_dirty |= 1 << (start_slot + i);
973
nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
979
nvc0_set_window_rectangles(struct pipe_context *pipe,
981
unsigned num_rectangles,
982
const struct pipe_scissor_state *rectangles)
984
struct nvc0_context *nvc0 = nvc0_context(pipe);
986
nvc0->window_rect.inclusive = include;
987
nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
988
memcpy(nvc0->window_rect.rect, rectangles,
989
sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
991
nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
995
nvc0_set_tess_state(struct pipe_context *pipe,
996
const float default_tess_outer[4],
997
const float default_tess_inner[2])
999
struct nvc0_context *nvc0 = nvc0_context(pipe);
1001
memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
1002
memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
1003
nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
1007
nvc0_set_patch_vertices(struct pipe_context *pipe, uint8_t patch_vertices)
1009
struct nvc0_context *nvc0 = nvc0_context(pipe);
1011
nvc0->patch_vertices = patch_vertices;
1015
nvc0_set_vertex_buffers(struct pipe_context *pipe,
1016
unsigned start_slot, unsigned count,
1017
unsigned unbind_num_trailing_slots,
1018
bool take_ownership,
1019
const struct pipe_vertex_buffer *vb)
1021
struct nvc0_context *nvc0 = nvc0_context(pipe);
1024
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
1025
nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
1027
util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1029
unbind_num_trailing_slots,
1032
unsigned clear_mask = ~u_bit_consecutive(start_slot + count, unbind_num_trailing_slots);
1033
nvc0->vbo_user &= clear_mask;
1034
nvc0->constant_vbos &= clear_mask;
1035
nvc0->vtxbufs_coherent &= clear_mask;
1038
clear_mask = ~u_bit_consecutive(start_slot, count);
1039
nvc0->vbo_user &= clear_mask;
1040
nvc0->constant_vbos &= clear_mask;
1041
nvc0->vtxbufs_coherent &= clear_mask;
1045
for (i = 0; i < count; ++i) {
1046
unsigned dst_index = start_slot + i;
1048
if (vb[i].is_user_buffer) {
1049
nvc0->vbo_user |= 1 << dst_index;
1050
if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1051
nvc0->constant_vbos |= 1 << dst_index;
1053
nvc0->constant_vbos &= ~(1 << dst_index);
1054
nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1056
nvc0->vbo_user &= ~(1 << dst_index);
1057
nvc0->constant_vbos &= ~(1 << dst_index);
1059
if (vb[i].buffer.resource &&
1060
vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1061
nvc0->vtxbufs_coherent |= (1 << dst_index);
1063
nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1069
nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1071
struct nvc0_context *nvc0 = nvc0_context(pipe);
1073
nvc0->vertex = hwcso;
1074
nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
1077
static struct pipe_stream_output_target *
1078
nvc0_so_target_create(struct pipe_context *pipe,
1079
struct pipe_resource *res,
1080
unsigned offset, unsigned size)
1082
struct nv04_resource *buf = (struct nv04_resource *)res;
1083
struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1087
targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1094
targ->pipe.buffer_size = size;
1095
targ->pipe.buffer_offset = offset;
1096
targ->pipe.context = pipe;
1097
targ->pipe.buffer = NULL;
1098
pipe_resource_reference(&targ->pipe.buffer, res);
1099
pipe_reference_init(&targ->pipe.reference, 1);
1101
assert(buf->base.target == PIPE_BUFFER);
1102
util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
1108
nvc0_so_target_save_offset(struct pipe_context *pipe,
1109
struct pipe_stream_output_target *ptarg,
1110
unsigned index, bool *serialize)
1112
struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1116
PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1117
IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1119
NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1122
nvc0_query(targ->pq)->index = index;
1123
pipe->end_query(pipe, targ->pq);
1127
nvc0_so_target_destroy(struct pipe_context *pipe,
1128
struct pipe_stream_output_target *ptarg)
1130
struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1131
pipe->destroy_query(pipe, targ->pq);
1132
pipe_resource_reference(&targ->pipe.buffer, NULL);
1137
nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1138
unsigned num_targets,
1139
struct pipe_stream_output_target **targets,
1140
const unsigned *offsets)
1142
struct nvc0_context *nvc0 = nvc0_context(pipe);
1144
bool serialize = true;
1146
assert(num_targets <= 4);
1148
for (i = 0; i < num_targets; ++i) {
1149
const bool changed = nvc0->tfbbuf[i] != targets[i];
1150
const bool append = (offsets[i] == ((unsigned)-1));
1151
if (!changed && append)
1153
nvc0->tfbbuf_dirty |= 1 << i;
1155
if (nvc0->tfbbuf[i] && changed)
1156
nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1158
if (targets[i] && !append)
1159
nvc0_so_target(targets[i])->clean = true;
1161
pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1163
for (; i < nvc0->num_tfbbufs; ++i) {
1164
if (nvc0->tfbbuf[i]) {
1165
nvc0->tfbbuf_dirty |= 1 << i;
1166
nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1167
pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1170
nvc0->num_tfbbufs = num_targets;
1172
if (nvc0->tfbbuf_dirty) {
1173
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1174
nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1179
nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1180
unsigned start, unsigned nr,
1181
struct pipe_surface **psurfaces)
1183
const unsigned end = start + nr;
1184
const unsigned mask = ((1 << nr) - 1) << start;
1188
for (i = start; i < end; ++i) {
1189
const unsigned p = i - start;
1191
nvc0->surfaces_valid[t] |= (1 << i);
1193
nvc0->surfaces_valid[t] &= ~(1 << i);
1194
pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1197
for (i = start; i < end; ++i)
1198
pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1199
nvc0->surfaces_valid[t] &= ~mask;
1201
nvc0->surfaces_dirty[t] |= mask;
1204
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1206
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1210
nvc0_set_compute_resources(struct pipe_context *pipe,
1211
unsigned start, unsigned nr,
1212
struct pipe_surface **resources)
1214
nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1216
nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1220
nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1221
unsigned start, unsigned nr,
1222
const struct pipe_image_view *pimages)
1224
const unsigned end = start + nr;
1231
for (i = start; i < end; ++i) {
1232
struct pipe_image_view *img = &nvc0->images[s][i];
1233
const unsigned p = i - start;
1235
if (img->resource == pimages[p].resource &&
1236
img->format == pimages[p].format &&
1237
img->access == pimages[p].access) {
1238
if (img->resource == NULL)
1240
if (img->resource->target == PIPE_BUFFER &&
1241
img->u.buf.offset == pimages[p].u.buf.offset &&
1242
img->u.buf.size == pimages[p].u.buf.size)
1244
if (img->resource->target != PIPE_BUFFER &&
1245
img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1246
img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1247
img->u.tex.level == pimages[p].u.tex.level)
1252
if (pimages[p].resource)
1253
nvc0->images_valid[s] |= (1 << i);
1255
nvc0->images_valid[s] &= ~(1 << i);
1257
img->format = pimages[p].format;
1258
img->access = pimages[p].access;
1259
if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1260
img->u.buf = pimages[p].u.buf;
1262
img->u.tex = pimages[p].u.tex;
1264
pipe_resource_reference(
1265
&img->resource, pimages[p].resource);
1267
if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1268
if (nvc0->images_tic[s][i]) {
1269
struct nv50_tic_entry *old =
1270
nv50_tic_entry(nvc0->images_tic[s][i]);
1271
nvc0_screen_tic_unlock(nvc0->screen, old);
1272
pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1275
nvc0->images_tic[s][i] =
1276
gm107_create_texture_view_from_image(&nvc0->base.pipe,
1283
mask = ((1 << nr) - 1) << start;
1284
if (!(nvc0->images_valid[s] & mask))
1286
for (i = start; i < end; ++i) {
1287
pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1288
if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1289
struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1291
nvc0_screen_tic_unlock(nvc0->screen, old);
1292
pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1296
nvc0->images_valid[s] &= ~mask;
1298
nvc0->images_dirty[s] |= mask;
1301
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1303
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1309
nvc0_set_shader_images(struct pipe_context *pipe,
1310
enum pipe_shader_type shader,
1311
unsigned start, unsigned nr,
1312
unsigned unbind_num_trailing_slots,
1313
const struct pipe_image_view *images)
1315
const unsigned s = nvc0_shader_stage(shader);
1317
nvc0_bind_images_range(nvc0_context(pipe), s, start + nr,
1318
unbind_num_trailing_slots, NULL);
1320
if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1324
nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1326
nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1330
nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1331
unsigned start, unsigned nr,
1332
const struct pipe_shader_buffer *pbuffers)
1334
const unsigned end = start + nr;
1341
for (i = start; i < end; ++i) {
1342
struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1343
const unsigned p = i - start;
1344
if (buf->buffer == pbuffers[p].buffer &&
1345
buf->buffer_offset == pbuffers[p].buffer_offset &&
1346
buf->buffer_size == pbuffers[p].buffer_size)
1350
if (pbuffers[p].buffer)
1351
nvc0->buffers_valid[t] |= (1 << i);
1353
nvc0->buffers_valid[t] &= ~(1 << i);
1354
buf->buffer_offset = pbuffers[p].buffer_offset;
1355
buf->buffer_size = pbuffers[p].buffer_size;
1356
pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1361
mask = ((1 << nr) - 1) << start;
1362
if (!(nvc0->buffers_valid[t] & mask))
1364
for (i = start; i < end; ++i)
1365
pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1366
nvc0->buffers_valid[t] &= ~mask;
1368
nvc0->buffers_dirty[t] |= mask;
1371
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1373
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1379
nvc0_set_shader_buffers(struct pipe_context *pipe,
1380
enum pipe_shader_type shader,
1381
unsigned start, unsigned nr,
1382
const struct pipe_shader_buffer *buffers,
1383
unsigned writable_bitmask)
1385
const unsigned s = nvc0_shader_stage(shader);
1386
if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1390
nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1392
nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1396
nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1398
struct nv04_resource *buf = nv04_resource(res);
1400
uint64_t address = buf->address + *phandle;
1401
/* even though it's a pointer to uint32_t that's fine */
1402
memcpy(phandle, &address, 8);
1409
nvc0_set_global_bindings(struct pipe_context *pipe,
1410
unsigned start, unsigned nr,
1411
struct pipe_resource **resources,
1414
struct nvc0_context *nvc0 = nvc0_context(pipe);
1415
struct pipe_resource **ptr;
1417
const unsigned end = start + nr;
1422
if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1423
const unsigned old_size = nvc0->global_residents.size;
1424
if (util_dynarray_resize(&nvc0->global_residents, struct pipe_resource *, end)) {
1425
memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1426
nvc0->global_residents.size - old_size);
1428
NOUVEAU_ERR("Could not resize global residents array\n");
1434
ptr = util_dynarray_element(
1435
&nvc0->global_residents, struct pipe_resource *, start);
1436
for (i = 0; i < nr; ++i) {
1437
pipe_resource_reference(&ptr[i], resources[i]);
1438
nvc0_set_global_handle(handles[i], resources[i]);
1441
ptr = util_dynarray_element(
1442
&nvc0->global_residents, struct pipe_resource *, start);
1443
for (i = 0; i < nr; ++i)
1444
pipe_resource_reference(&ptr[i], NULL);
1447
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1449
nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1453
nvc0_init_state_functions(struct nvc0_context *nvc0)
1455
struct pipe_context *pipe = &nvc0->base.pipe;
1457
pipe->create_blend_state = nvc0_blend_state_create;
1458
pipe->bind_blend_state = nvc0_blend_state_bind;
1459
pipe->delete_blend_state = nvc0_blend_state_delete;
1461
pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1462
pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1463
pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1465
pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1466
pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1467
pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1469
pipe->create_sampler_state = nv50_sampler_state_create;
1470
pipe->delete_sampler_state = nvc0_sampler_state_delete;
1471
pipe->bind_sampler_states = nvc0_bind_sampler_states;
1473
pipe->create_sampler_view = nvc0_create_sampler_view;
1474
pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1475
pipe->set_sampler_views = nvc0_set_sampler_views;
1477
pipe->create_vs_state = nvc0_vp_state_create;
1478
pipe->create_fs_state = nvc0_fp_state_create;
1479
pipe->create_gs_state = nvc0_gp_state_create;
1480
pipe->create_tcs_state = nvc0_tcp_state_create;
1481
pipe->create_tes_state = nvc0_tep_state_create;
1482
pipe->bind_vs_state = nvc0_vp_state_bind;
1483
pipe->bind_fs_state = nvc0_fp_state_bind;
1484
pipe->bind_gs_state = nvc0_gp_state_bind;
1485
pipe->bind_tcs_state = nvc0_tcp_state_bind;
1486
pipe->bind_tes_state = nvc0_tep_state_bind;
1487
pipe->delete_vs_state = nvc0_sp_state_delete;
1488
pipe->delete_fs_state = nvc0_sp_state_delete;
1489
pipe->delete_gs_state = nvc0_sp_state_delete;
1490
pipe->delete_tcs_state = nvc0_sp_state_delete;
1491
pipe->delete_tes_state = nvc0_sp_state_delete;
1493
pipe->create_compute_state = nvc0_cp_state_create;
1494
pipe->bind_compute_state = nvc0_cp_state_bind;
1495
pipe->delete_compute_state = nvc0_sp_state_delete;
1497
pipe->set_blend_color = nvc0_set_blend_color;
1498
pipe->set_stencil_ref = nvc0_set_stencil_ref;
1499
pipe->set_clip_state = nvc0_set_clip_state;
1500
pipe->set_sample_mask = nvc0_set_sample_mask;
1501
pipe->set_min_samples = nvc0_set_min_samples;
1502
pipe->set_constant_buffer = nvc0_set_constant_buffer;
1503
pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1504
pipe->set_sample_locations = nvc0_set_sample_locations;
1505
pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1506
pipe->set_scissor_states = nvc0_set_scissor_states;
1507
pipe->set_viewport_states = nvc0_set_viewport_states;
1508
pipe->set_window_rectangles = nvc0_set_window_rectangles;
1509
pipe->set_tess_state = nvc0_set_tess_state;
1510
pipe->set_patch_vertices = nvc0_set_patch_vertices;
1512
pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1513
pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1514
pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1516
pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1518
pipe->create_stream_output_target = nvc0_so_target_create;
1519
pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1520
pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1522
pipe->set_global_binding = nvc0_set_global_bindings;
1523
pipe->set_compute_resources = nvc0_set_compute_resources;
1524
pipe->set_shader_images = nvc0_set_shader_images;
1525
pipe->set_shader_buffers = nvc0_set_shader_buffers;
1527
nvc0->sample_mask = ~0;
1528
nvc0->min_samples = 1;
1529
nvc0->default_tess_outer[0] =
1530
nvc0->default_tess_outer[1] =
1531
nvc0->default_tess_outer[2] =
1532
nvc0->default_tess_outer[3] = 1.0;
1533
nvc0->default_tess_inner[0] =
1534
nvc0->default_tess_inner[1] = 1.0;