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* Copyright (c) 2017 Lima Project
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* Copyright (c) 2013 Connor Abbott
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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#ifndef LIMA_IR_PP_PPIR_H
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#define LIMA_IR_PP_PPIR_H
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#include "util/u_math.h"
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#include "util/list.h"
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#include "ir/lima_ir.h"
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ppir_op_unsupported = 0,
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ppir_op_load_uniform,
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ppir_op_load_varying,
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ppir_op_load_coords_reg,
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ppir_op_load_fragcoord,
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ppir_op_load_pointcoord,
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ppir_op_load_frontface,
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ppir_op_load_texture,
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ppir_node_type_const,
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ppir_node_type_store,
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ppir_node_type_load_texture,
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ppir_node_type_discard,
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ppir_node_type_branch,
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extern const ppir_op_info ppir_op_infos[];
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ppir_dep_write_after_read,
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struct list_head pred_link;
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struct list_head succ_link;
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typedef struct ppir_node {
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struct list_head list;
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struct list_head sched_list;
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struct ppir_instr *instr;
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struct ppir_block *block;
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bool succ_different_block;
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struct list_head succ_list;
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struct list_head pred_list;
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ppir_pipeline_reg_const0,
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ppir_pipeline_reg_const1,
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ppir_pipeline_reg_sampler,
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ppir_pipeline_reg_uniform,
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ppir_pipeline_reg_vmul,
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ppir_pipeline_reg_fmul,
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ppir_pipeline_reg_discard, /* varying load */
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ppir_output_invalid = -1,
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static inline const char *ppir_output_type_to_str(ppir_output_type type)
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case ppir_output_color0:
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return "OUTPUT_COLOR0";
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case ppir_output_color1:
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return "OUTPUT_COLOR1";
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case ppir_output_depth:
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return "OUTPUT_DEPTH";
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static inline ppir_output_type ppir_nir_output_to_ppir(gl_frag_result res, int dual_src_index)
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case FRAG_RESULT_COLOR:
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case FRAG_RESULT_DATA0:
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return ppir_output_color0 + dual_src_index;
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case FRAG_RESULT_DEPTH:
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return ppir_output_depth;
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return ppir_output_invalid;
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typedef struct ppir_reg {
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struct list_head list;
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ppir_output_type out_type;
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/* whether this reg has to start from the x component
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* of a full physical reg, this is true for reg used
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* in load/store instr which has no swizzle field */
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ppir_target_pipeline,
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ppir_target_register,
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typedef struct ppir_src {
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ppir_pipeline pipeline;
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bool absolute, negate;
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ppir_outmod_clamp_fraction,
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ppir_outmod_clamp_positive,
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typedef struct ppir_dest {
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ppir_pipeline pipeline;
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ppir_outmod modifier;
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unsigned write_mask : 4;
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int shift : 3; /* Only used for ppir_op_mul */
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typedef struct ppir_const {
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ppir_perspective_none = 0,
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ppir_perspective perspective;
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} ppir_load_texture_node;
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enum ppir_instr_slot {
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PPIR_INSTR_SLOT_VARYING,
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PPIR_INSTR_SLOT_TEXLD,
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PPIR_INSTR_SLOT_UNIFORM,
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PPIR_INSTR_SLOT_ALU_VEC_MUL,
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PPIR_INSTR_SLOT_ALU_SCL_MUL,
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PPIR_INSTR_SLOT_ALU_VEC_ADD,
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PPIR_INSTR_SLOT_ALU_SCL_ADD,
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PPIR_INSTR_SLOT_ALU_COMBINE,
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PPIR_INSTR_SLOT_STORE_TEMP,
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PPIR_INSTR_SLOT_BRANCH,
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PPIR_INSTR_SLOT_ALU_START = PPIR_INSTR_SLOT_ALU_VEC_MUL,
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PPIR_INSTR_SLOT_ALU_END = PPIR_INSTR_SLOT_ALU_COMBINE,
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typedef struct ppir_instr {
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struct list_head list;
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int seq; /* command sequence after schedule */
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ppir_node *slots[PPIR_INSTR_SLOT_NUM];
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ppir_const constant[2];
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struct list_head succ_list;
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struct list_head pred_list;
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int est; /* earliest start time */
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/* for liveness analysis */
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BITSET_WORD *live_set;
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uint8_t *live_mask; /* mask for non-ssa registers */
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/* live_internal is to mark registers only live within an
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* instruction, without propagation */
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BITSET_WORD *live_internal;
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typedef struct ppir_block {
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struct list_head list;
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struct list_head node_list;
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struct list_head instr_list;
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struct ppir_block *successors[2];
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struct ppir_compiler *comp;
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int sched_instr_index;
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int sched_instr_base;
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struct lima_fs_compiled_shader;
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typedef struct ppir_compiler {
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struct list_head block_list;
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struct hash_table_u64 *blocks;
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int *out_type_to_reg;
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struct list_head reg_list;
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/* array for searching ssa/reg node */
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ppir_node **var_nodes;
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struct lima_fs_compiled_shader *prog;
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bool dual_source_blend;
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int sched_instr_base;
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/* for regalloc spilling debug */
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ppir_block *discard_block;
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ppir_block *current_block;
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ppir_block *loop_break_block;
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ppir_block *loop_cont_block;
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void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask);
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void ppir_node_add_dep(ppir_node *succ, ppir_node *pred, ppir_dep_type type);
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void ppir_node_remove_dep(ppir_dep *dep);
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void ppir_node_delete(ppir_node *node);
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void ppir_node_print_prog(ppir_compiler *comp);
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void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child);
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void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src);
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void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred);
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ppir_dep *ppir_dep_for_pred(ppir_node *node, ppir_node *pred);
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/* Assumes that node successors are in the same block */
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ppir_node *ppir_node_insert_mov(ppir_node *node);
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static inline bool ppir_node_is_root(ppir_node *node)
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return list_is_empty(&node->succ_list);
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static inline bool ppir_node_is_leaf(ppir_node *node)
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return list_is_empty(&node->pred_list);
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static inline bool ppir_node_has_single_succ(ppir_node *node)
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return list_is_singular(&node->succ_list)
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&& !node->succ_different_block;
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bool ppir_node_has_single_src_succ(ppir_node *node);
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static inline ppir_node *ppir_node_first_succ(ppir_node *node)
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return list_first_entry(&node->succ_list, ppir_dep, succ_link)->succ;
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static inline bool ppir_node_has_single_pred(ppir_node *node)
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return list_is_singular(&node->pred_list);
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static inline ppir_node *ppir_node_first_pred(ppir_node *node)
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return list_first_entry(&node->pred_list, ppir_dep, pred_link)->pred;
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#define ppir_node_foreach_succ(node, dep) \
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list_for_each_entry(ppir_dep, dep, &node->succ_list, succ_link)
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#define ppir_node_foreach_succ_safe(node, dep) \
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list_for_each_entry_safe(ppir_dep, dep, &node->succ_list, succ_link)
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#define ppir_node_foreach_pred(node, dep) \
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list_for_each_entry(ppir_dep, dep, &node->pred_list, pred_link)
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#define ppir_node_foreach_pred_safe(node, dep) \
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list_for_each_entry_safe(ppir_dep, dep, &node->pred_list, pred_link)
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#define ppir_node_to_alu(node) ((ppir_alu_node *)(node))
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#define ppir_node_to_const(node) ((ppir_const_node *)(node))
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#define ppir_node_to_load(node) ((ppir_load_node *)(node))
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#define ppir_node_to_store(node) ((ppir_store_node *)(node))
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#define ppir_node_to_load_texture(node) ((ppir_load_texture_node *)(node))
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#define ppir_node_to_discard(node) ((ppir_discard_node *)(node))
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#define ppir_node_to_branch(node) ((ppir_branch_node *)(node))
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static inline ppir_dest *ppir_node_get_dest(ppir_node *node)
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switch (node->type) {
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case ppir_node_type_alu:
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return &ppir_node_to_alu(node)->dest;
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case ppir_node_type_load:
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return &ppir_node_to_load(node)->dest;
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case ppir_node_type_const:
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return &ppir_node_to_const(node)->dest;
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case ppir_node_type_load_texture:
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return &ppir_node_to_load_texture(node)->dest;
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static inline int ppir_node_get_src_num(ppir_node *node)
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switch (node->type) {
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case ppir_node_type_alu:
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return ppir_node_to_alu(node)->num_src;
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case ppir_node_type_branch:
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return ppir_node_to_branch(node)->num_src;
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case ppir_node_type_load:
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return ppir_node_to_load(node)->num_src;
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case ppir_node_type_load_texture:
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return ppir_node_to_load_texture(node)->num_src;
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case ppir_node_type_store:
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static inline ppir_src *ppir_node_get_src(ppir_node *node, int idx)
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if (idx < 0 || idx >= ppir_node_get_src_num(node))
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switch (node->type) {
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case ppir_node_type_alu:
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return &ppir_node_to_alu(node)->src[idx];
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case ppir_node_type_branch:
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return &ppir_node_to_branch(node)->src[idx];
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case ppir_node_type_load_texture:
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return &ppir_node_to_load_texture(node)->src[idx];
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case ppir_node_type_load:
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return &ppir_node_to_load(node)->src;
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case ppir_node_type_store:
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return &ppir_node_to_store(node)->src;
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static inline ppir_reg *ppir_src_get_reg(ppir_src *src)
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case ppir_target_ssa:
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case ppir_target_register:
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static inline ppir_reg *ppir_dest_get_reg(ppir_dest *dest)
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switch (dest->type) {
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case ppir_target_ssa:
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case ppir_target_register:
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static inline void ppir_node_target_assign(ppir_src *src, ppir_node *node)
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ppir_dest *dest = ppir_node_get_dest(node);
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src->type = dest->type;
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case ppir_target_ssa:
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src->ssa = &dest->ssa;
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case ppir_target_register:
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src->reg = dest->reg;
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/* Registers can be assigned from multiple nodes, so don't keep
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* pointer to the node here
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case ppir_target_pipeline:
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src->pipeline = dest->pipeline;
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static inline bool ppir_node_target_equal(ppir_src *src, ppir_dest *dest)
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if (src->type != dest->type ||
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(src->type == ppir_target_ssa && src->ssa != &dest->ssa) ||
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(src->type == ppir_target_register && src->reg != dest->reg) ||
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(src->type == ppir_target_pipeline && src->pipeline != dest->pipeline))
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static inline int ppir_target_get_src_reg_index(ppir_src *src)
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case ppir_target_ssa:
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return src->ssa->index;
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case ppir_target_register:
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return src->reg->index;
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case ppir_target_pipeline:
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if (src->pipeline == ppir_pipeline_reg_discard)
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return (src->pipeline + 12) * 4;
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static inline int ppir_target_get_dest_reg_index(ppir_dest *dest)
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switch (dest->type) {
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case ppir_target_ssa:
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return dest->ssa.index;
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case ppir_target_register:
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return dest->reg->index;
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case ppir_target_pipeline:
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if (dest->pipeline == ppir_pipeline_reg_discard)
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return (dest->pipeline + 12) * 4;
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static inline int ppir_src_get_mask(ppir_src *src)
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ppir_reg *reg = ppir_src_get_reg(src);
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for (int i = 0; i < reg->num_components; i++)
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mask |= (1 << src->swizzle[i]);
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static inline bool ppir_target_is_scalar(ppir_dest *dest)
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switch (dest->type) {
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case ppir_target_ssa:
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return dest->ssa.num_components == 1;
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case ppir_target_register:
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/* only one bit in mask is set */
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if ((dest->write_mask & 0x3) == 0x3 ||
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(dest->write_mask & 0x5) == 0x5 ||
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(dest->write_mask & 0x9) == 0x9 ||
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(dest->write_mask & 0x6) == 0x6 ||
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(dest->write_mask & 0xa) == 0xa ||
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(dest->write_mask & 0xc) == 0xc)
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case ppir_target_pipeline:
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if (dest->pipeline == ppir_pipeline_reg_fmul)
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static inline bool ppir_node_schedulable_slot(ppir_node *node,
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enum ppir_instr_slot slot)
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int *slots = ppir_op_infos[node->op].slots;
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for (int i = 0; slots[i] != PPIR_INSTR_SLOT_END; i++)
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if (slots[i] == slot)
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ppir_instr *ppir_instr_create(ppir_block *block);
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bool ppir_instr_insert_node(ppir_instr *instr, ppir_node *node);
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void ppir_instr_add_dep(ppir_instr *succ, ppir_instr *pred);
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void ppir_instr_print_list(ppir_compiler *comp);
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void ppir_instr_print_dep(ppir_compiler *comp);
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void ppir_instr_insert_mul_node(ppir_node *add, ppir_node *mul);
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#define ppir_instr_foreach_succ(instr, dep) \
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list_for_each_entry(ppir_dep, dep, &instr->succ_list, succ_link)
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#define ppir_instr_foreach_succ_safe(instr, dep) \
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list_for_each_entry_safe(ppir_dep, dep, &instr->succ_list, succ_link)
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#define ppir_instr_foreach_pred(instr, dep) \
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list_for_each_entry(ppir_dep, dep, &instr->pred_list, pred_link)
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#define ppir_instr_foreach_pred_safe(instr, dep) \
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list_for_each_entry_safe(ppir_dep, dep, &instr->pred_list, pred_link)
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static inline bool ppir_instr_is_root(ppir_instr *instr)
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return list_is_empty(&instr->succ_list);
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static inline bool ppir_instr_is_leaf(ppir_instr *instr)
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return list_is_empty(&instr->pred_list);
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bool ppir_lower_prog(ppir_compiler *comp);
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bool ppir_node_to_instr(ppir_compiler *comp);
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bool ppir_schedule_prog(ppir_compiler *comp);
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bool ppir_regalloc_prog(ppir_compiler *comp);
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bool ppir_codegen_prog(ppir_compiler *comp);
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void ppir_liveness_analysis(ppir_compiler *comp);
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static inline unsigned int reg_mask_size(unsigned int num_reg)
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return (num_reg + 1) / 2;
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static inline uint8_t get_reg_mask(uint8_t *set, unsigned index)
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unsigned int i = index / 2;
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unsigned int shift = index % 2 ? 4 : 0;
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uint8_t mask = 0x0f << shift;
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return (set[i] & mask) >> shift;
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static inline void set_reg_mask(uint8_t *set, unsigned int index, uint8_t bits)
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unsigned int i = index / 2;
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unsigned int shift = index % 2 ? 4 : 0;
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uint8_t mask = 0x0f << shift;
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set[i] |= (bits << shift);