2
* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
* copy of this software and associated documentation files (the "Software"),
6
* to deal in the Software without restriction, including without limitation
7
* on the rights to use, copy, modify, merge, publish, distribute, sub
8
* license, and/or sell copies of the Software, and to permit persons to whom
9
* the Software is furnished to do so, subject to the following conditions:
11
* The above copyright notice and this permission notice (including the next
12
* paragraph) shall be included in all copies or substantial portions of the
15
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21
* USE OR OTHER DEALINGS IN THE SOFTWARE.
29
#include "r600_pipe_common.h"
31
#include "r600_public.h"
32
#include "pipe/p_defines.h"
34
#include "util/u_suballoc.h"
35
#include "util/list.h"
36
#include "util/u_transfer.h"
37
#include "util/u_memory.h"
39
#include "tgsi/tgsi_scan.h"
41
#define R600_NUM_ATOMS 56
43
#define R600_MAX_IMAGES 8
45
* ranges reserved for images on evergreen
46
* first set for the immediate buffers,
47
* second for the actual resources for RESQ.
49
#define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
50
#define R600_IMAGE_REAL_RESOURCE_OFFSET 168
53
#define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
54
#define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
55
#define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
56
/* read-write caches */
57
#define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
58
#define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
59
#define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
60
#define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
61
#define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
62
/* engine synchronization */
63
#define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
64
#define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
65
#define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
66
#define R600_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
68
/* the number of CS dwords for flushing and drawing */
69
#define R600_MAX_FLUSH_CS_DWORDS 18
70
#define R600_MAX_DRAW_CS_DWORDS 58
71
#define R600_MAX_PFP_SYNC_ME_DWORDS 16
73
#define EG_MAX_ATOMIC_BUFFERS 8
75
#define R600_MAX_USER_CONST_BUFFERS 15
76
#define R600_MAX_DRIVER_CONST_BUFFERS 3
77
#define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
78
#define R600_MAX_HW_CONST_BUFFERS 16
80
/* start driver buffers after user buffers */
81
#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
82
#define R600_UCP_SIZE (4*4*8)
83
#define R600_CS_BLOCK_GRID_SIZE (8 * 4)
84
#define R600_TCS_DEFAULT_LEVELS_SIZE (6 * 4)
85
#define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
88
* We only access this buffer through vtx clauses hence it's fine to exist
91
#define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
93
* Note GS doesn't use a constant buffer binding, just a resource index,
94
* so it's fine to have it exist at index beyond 15. I.e. it's not actually
95
* a const buffer, just a buffer resource.
97
#define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
98
/* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
99
* of 16 const buffers.
100
* UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
102
* In order to support d3d 11 mandated minimum of 15 user const buffers
103
* we'd have to squash all use cases into one driver buffer.
105
#define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
108
#define R600_HW_STAGE_PS 0
109
#define R600_HW_STAGE_VS 1
110
#define R600_HW_STAGE_GS 2
111
#define R600_HW_STAGE_ES 3
112
#define EG_HW_STAGE_LS 4
113
#define EG_HW_STAGE_HS 5
115
#define R600_NUM_HW_STAGES 4
116
#define EG_NUM_HW_STAGES 6
119
struct r600_bytecode;
120
union r600_shader_key;
122
/* This is an atom containing GPU commands that never change.
123
* This is supposed to be copied directly into the CS. */
124
struct r600_command_buffer {
131
struct r600_db_state {
132
struct r600_atom atom;
133
struct r600_surface *rsurf;
136
struct r600_db_misc_state {
137
struct r600_atom atom;
138
bool occlusion_queries_disabled;
139
bool flush_depthstencil_through_cb;
140
bool flush_depth_inplace;
141
bool flush_stencil_inplace;
142
bool copy_depth, copy_stencil;
143
unsigned copy_sample;
144
unsigned log_samples;
145
unsigned db_shader_control;
147
uint8_t ps_conservative_z;
150
struct r600_cb_misc_state {
151
struct r600_atom atom;
152
unsigned cb_color_control; /* this comes from blend state */
153
unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
155
unsigned bound_cbufs_target_mask;
156
unsigned nr_ps_color_outputs;
157
unsigned ps_color_export_mask;
158
unsigned image_rat_enabled_mask;
159
unsigned buffer_rat_enabled_mask;
164
struct r600_clip_misc_state {
165
struct r600_atom atom;
166
unsigned pa_cl_clip_cntl; /* from rasterizer */
167
unsigned pa_cl_vs_out_cntl; /* from vertex shader */
168
unsigned clip_plane_enable; /* from rasterizer */
169
unsigned cc_dist_mask; /* from vertex shader */
170
unsigned clip_dist_write; /* from vertex shader */
171
unsigned cull_dist_write; /* from vertex shader */
172
boolean clip_disable; /* from vertex shader */
173
boolean vs_out_viewport; /* from vertex shader */
176
struct r600_alphatest_state {
177
struct r600_atom atom;
178
unsigned sx_alpha_test_control; /* this comes from dsa state */
179
unsigned sx_alpha_ref; /* this comes from dsa state */
181
bool cb0_export_16bpc; /* from set_framebuffer_state */
184
struct r600_vgt_state {
185
struct r600_atom atom;
186
uint32_t vgt_multi_prim_ib_reset_en;
187
uint32_t vgt_multi_prim_ib_reset_indx;
188
uint32_t vgt_indx_offset;
189
bool last_draw_was_indirect;
192
struct r600_blend_color {
193
struct r600_atom atom;
194
struct pipe_blend_color state;
197
struct r600_clip_state {
198
struct r600_atom atom;
199
struct pipe_clip_state state;
202
struct r600_cs_shader_state {
203
struct r600_atom atom;
204
unsigned kernel_index;
206
struct r600_pipe_compute *shader;
209
struct r600_framebuffer {
210
struct r600_atom atom;
211
struct pipe_framebuffer_state state;
212
unsigned compressed_cb_mask;
216
bool is_msaa_resolve;
218
bool do_update_surf_dirtiness;
221
struct r600_sample_mask {
222
struct r600_atom atom;
223
uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
226
struct r600_config_state {
227
struct r600_atom atom;
228
unsigned sq_gpr_resource_mgmt_1;
229
unsigned sq_gpr_resource_mgmt_2;
230
unsigned sq_gpr_resource_mgmt_3;
231
bool dyn_gpr_enabled;
234
struct r600_stencil_ref
241
struct r600_stencil_ref_state {
242
struct r600_atom atom;
243
struct r600_stencil_ref state;
244
struct pipe_stencil_ref pipe_state;
247
struct r600_shader_stages_state {
248
struct r600_atom atom;
249
unsigned geom_enable;
252
struct r600_gs_rings_state {
253
struct r600_atom atom;
255
struct pipe_constant_buffer esgs_ring;
256
struct pipe_constant_buffer gsvs_ring;
259
/* This must start from 16. */
261
#define DBG_NO_CP_DMA (1 << 30)
263
#define DBG_NO_SB (1 << 21)
264
#define DBG_SB_DRY_RUN (1 << 23)
265
#define DBG_SB_STAT (1 << 24)
266
#define DBG_SB_DUMP (1 << 25)
267
#define DBG_SB_NO_FALLBACK (1 << 26)
268
#define DBG_SB_DISASM (1 << 27)
269
#define DBG_SB_SAFEMATH (1 << 28)
270
#define DBG_NIR_SB (1 << 28)
272
#define DBG_NIR_PREFERRED (DBG_NIR_SB | DBG_NIR)
275
struct r600_common_screen b;
277
bool has_compressed_msaa_texturing;
280
/*for compute global memory binding, we allocate stuff here, instead of
282
* XXX: Not sure if this is the best place for global_pool. Also,
283
* it's not thread safe, so it won't work with multiple contexts. */
284
struct compute_memory_pool *global_pool;
287
struct r600_pipe_sampler_view {
288
struct pipe_sampler_view base;
289
struct list_head list;
290
struct r600_resource *tex_resource;
291
uint32_t tex_resource_words[8];
292
bool skip_mip_address_reloc;
293
bool is_stencil_sampler;
296
struct r600_rasterizer_state {
297
struct r600_command_buffer buffer;
300
unsigned sprite_coord_enable;
301
unsigned clip_plane_enable;
302
unsigned pa_sc_line_stipple;
303
unsigned pa_cl_clip_cntl;
304
unsigned pa_su_sc_mode_cntl;
308
bool offset_units_unscaled;
310
bool multisample_enable;
312
bool rasterizer_discard;
315
struct r600_poly_offset_state {
316
struct r600_atom atom;
317
enum pipe_format zs_format;
320
bool offset_units_unscaled;
323
struct r600_blend_state {
324
struct r600_command_buffer buffer;
325
struct r600_command_buffer buffer_no_blend;
326
unsigned cb_target_mask;
327
unsigned cb_color_control;
328
unsigned cb_color_control_no_blend;
333
struct r600_dsa_state {
334
struct r600_command_buffer buffer;
339
unsigned sx_alpha_test_control;
342
struct r600_pipe_shader;
344
struct r600_pipe_shader_selector {
345
struct r600_pipe_shader *current;
347
struct tgsi_token *tokens;
348
struct nir_shader *nir;
349
struct pipe_stream_output_info so;
350
struct tgsi_shader_info info;
352
unsigned num_shaders;
354
enum pipe_shader_type type;
355
enum pipe_shader_ir ir_type;
357
/* geometry shader properties */
358
enum pipe_prim_type gs_output_prim;
359
unsigned gs_max_out_vertices;
360
unsigned gs_num_invocations;
363
uint64_t lds_patch_outputs_written_mask;
364
uint64_t lds_outputs_written_mask;
367
struct r600_pipe_sampler_state {
368
uint32_t tex_sampler_words[3];
369
union pipe_color_union border_color;
370
bool border_color_use;
371
bool seamless_cube_map;
374
/* needed for blitter save */
375
#define NUM_TEX_UNITS 16
377
struct r600_seamless_cube_map {
378
struct r600_atom atom;
382
struct r600_samplerview_state {
383
struct r600_atom atom;
384
struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
385
uint32_t enabled_mask;
387
uint32_t compressed_depthtex_mask; /* which textures are depth */
388
uint32_t compressed_colortex_mask;
389
boolean dirty_buffer_constants;
392
struct r600_sampler_states {
393
struct r600_atom atom;
394
struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
395
uint32_t enabled_mask;
397
uint32_t has_bordercolor_mask; /* which states contain the border color */
400
struct r600_textures_info {
401
struct r600_samplerview_state views;
402
struct r600_sampler_states states;
403
bool is_array_sampler[NUM_TEX_UNITS];
406
struct r600_shader_driver_constants_info {
407
/* currently 128 bytes for UCP/samplepos + sampler buffer constants */
410
bool texture_const_dirty;
412
bool ps_sample_pos_dirty;
413
bool cs_block_grid_size_dirty;
414
bool tcs_default_levels_dirty;
417
struct r600_constbuf_state
419
struct r600_atom atom;
420
struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
421
uint32_t enabled_mask;
425
struct r600_vertexbuf_state
427
struct r600_atom atom;
428
struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
429
uint32_t enabled_mask; /* non-NULL buffers */
433
/* CSO (constant state object, in other words, immutable state). */
434
struct r600_cso_state
436
struct r600_atom atom;
437
void *cso; /* e.g. r600_blend_state */
438
struct r600_command_buffer *cb;
441
struct r600_fetch_shader {
442
struct r600_resource *buffer;
446
struct r600_shader_state {
447
struct r600_atom atom;
448
struct r600_pipe_shader *shader;
451
struct r600_atomic_buffer_state {
452
struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
455
struct r600_image_view {
456
struct pipe_image_view base;
457
uint32_t cb_color_base;
458
uint32_t cb_color_pitch;
459
uint32_t cb_color_slice;
460
uint32_t cb_color_view;
461
uint32_t cb_color_info;
462
uint32_t cb_color_attrib;
463
uint32_t cb_color_dim;
464
uint32_t cb_color_fmask;
465
uint32_t cb_color_fmask_slice;
466
uint32_t immed_resource_words[8];
467
uint32_t resource_words[8];
468
bool skip_mip_address_reloc;
472
struct r600_image_state {
473
struct r600_atom atom;
474
uint32_t enabled_mask;
476
uint32_t compressed_depthtex_mask;
477
uint32_t compressed_colortex_mask;
478
boolean dirty_buffer_constants;
479
struct r600_image_view views[R600_MAX_IMAGES];
482
/* Used to spill shader temps */
483
struct r600_scratch_buffer {
484
struct r600_resource *buffer;
490
struct r600_context {
491
struct r600_common_context b;
492
struct r600_screen *screen;
493
struct blitter_context *blitter;
494
struct u_suballocator allocator_fetch_shader;
497
boolean has_vertex_cache;
498
unsigned default_gprs[EG_NUM_HW_STAGES];
499
unsigned current_gprs[EG_NUM_HW_STAGES];
500
unsigned r6xx_num_clause_temp_gprs;
502
/* Miscellaneous state objects. */
503
void *custom_dsa_flush;
504
void *custom_blend_resolve;
505
void *custom_blend_decompress;
506
void *custom_blend_fastclear;
507
/* With rasterizer discard, there doesn't have to be a pixel shader.
508
* In that case, we bind this one: */
509
void *dummy_pixel_shader;
510
/* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
511
* bug where valid CMASK and FMASK are required to be present to avoid
512
* a hardlock in certain operations but aren't actually used
513
* for anything useful. */
514
struct r600_resource *dummy_fmask;
515
struct r600_resource *dummy_cmask;
517
/* State binding slots are here. */
518
struct r600_atom *atoms[R600_NUM_ATOMS];
519
/* Dirty atom bitmask for fast tests */
520
uint64_t dirty_atoms;
521
/* States for CS initialization. */
522
struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
523
/** Compute specific registers initializations. The start_cs_cmd atom
524
* must be emitted before start_compute_cs_cmd. */
525
struct r600_command_buffer start_compute_cs_cmd;
526
/* Register states. */
527
struct r600_alphatest_state alphatest_state;
528
struct r600_cso_state blend_state;
529
struct r600_blend_color blend_color;
530
struct r600_cb_misc_state cb_misc_state;
531
struct r600_clip_misc_state clip_misc_state;
532
struct r600_clip_state clip_state;
533
struct r600_db_misc_state db_misc_state;
534
struct r600_db_state db_state;
535
struct r600_cso_state dsa_state;
536
struct r600_framebuffer framebuffer;
537
struct r600_poly_offset_state poly_offset_state;
538
struct r600_cso_state rasterizer_state;
539
struct r600_sample_mask sample_mask;
540
struct r600_seamless_cube_map seamless_cube_map;
541
struct r600_config_state config_state;
542
struct r600_stencil_ref_state stencil_ref;
543
struct r600_vgt_state vgt_state;
544
struct r600_atomic_buffer_state atomic_buffer_state;
545
/* only have images on fragment shader */
546
struct r600_image_state fragment_images;
547
struct r600_image_state compute_images;
548
struct r600_image_state fragment_buffers;
549
struct r600_image_state compute_buffers;
550
/* Shaders and shader resources. */
551
struct r600_cso_state vertex_fetch_shader;
552
struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
553
struct r600_cs_shader_state cs_shader_state;
554
struct r600_shader_stages_state shader_stages;
555
struct r600_gs_rings_state gs_rings;
556
struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
557
struct r600_textures_info samplers[PIPE_SHADER_TYPES];
559
struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
561
/** Vertex buffers for fetch shaders */
562
struct r600_vertexbuf_state vertex_buffer_state;
563
/** Vertex buffers for compute shaders */
564
struct r600_vertexbuf_state cs_vertex_buffer_state;
566
/* Additional context states. */
567
unsigned compute_cb_target_mask;
568
struct r600_pipe_shader_selector *ps_shader;
569
struct r600_pipe_shader_selector *vs_shader;
570
struct r600_pipe_shader_selector *gs_shader;
572
struct r600_pipe_shader_selector *tcs_shader;
573
struct r600_pipe_shader_selector *tes_shader;
575
struct r600_pipe_shader_selector *fixed_func_tcs_shader;
577
struct r600_rasterizer_state *rasterizer;
579
bool force_blend_disable;
580
bool gs_tri_strip_adj_fix;
581
boolean dual_src_blend;
583
unsigned ps_iter_samples;
585
/* The list of all texture buffer objects in this context.
586
* This list is walked when a buffer is invalidated/reallocated and
587
* the GPU addresses are updated. */
588
struct list_head texture_buffers;
590
/* Last draw state (-1 = unset). */
591
enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
592
enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
593
enum pipe_prim_type last_rast_prim;
594
unsigned last_start_instance;
597
struct r600_isa *isa;
598
float sample_positions[4 * 16];
600
uint32_t cs_block_grid_sizes[8]; /* 3 for grid + 1 pad, 3 for block + 1 pad*/
601
struct r600_pipe_shader_selector *last_ls;
602
struct r600_pipe_shader_selector *last_tcs;
603
unsigned last_num_tcs_input_cp;
606
struct r600_scratch_buffer scratch_buffers[MAX2(R600_NUM_HW_STAGES, EG_NUM_HW_STAGES)];
610
struct radeon_saved_cs last_gfx;
611
struct r600_resource *last_trace_buf;
612
struct r600_resource *trace_buf;
615
uint8_t patch_vertices;
616
bool cmd_buf_is_compute;
617
struct pipe_resource *append_fence;
618
uint32_t append_fence_id;
621
static inline void r600_emit_command_buffer(struct radeon_cmdbuf *cs,
622
struct r600_command_buffer *cb)
624
assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
625
memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
626
cs->current.cdw += cb->num_dw;
629
static inline void r600_set_atom_dirty(struct r600_context *rctx,
630
struct r600_atom *atom,
635
assert(atom->id != 0);
636
assert(atom->id < sizeof(mask) * 8);
637
mask = 1ull << atom->id;
639
rctx->dirty_atoms |= mask;
641
rctx->dirty_atoms &= ~mask;
644
static inline void r600_mark_atom_dirty(struct r600_context *rctx,
645
struct r600_atom *atom)
647
r600_set_atom_dirty(rctx, atom, true);
650
static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
652
atom->emit(&rctx->b, atom);
653
r600_set_atom_dirty(rctx, atom, false);
656
static inline void r600_set_cso_state(struct r600_context *rctx,
657
struct r600_cso_state *state, void *cso)
660
r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
663
static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
664
struct r600_cso_state *state, void *cso,
665
struct r600_command_buffer *cb)
668
state->atom.num_dw = cb ? cb->num_dw : 0;
669
r600_set_cso_state(rctx, state, cso);
672
/* compute_memory_pool.c */
673
struct compute_memory_pool;
674
void compute_memory_pool_delete(struct compute_memory_pool* pool);
675
struct compute_memory_pool* compute_memory_pool_new(
676
struct r600_screen *rscreen);
678
/* evergreen_state.c */
679
struct pipe_sampler_view *
680
evergreen_create_sampler_view_custom(struct pipe_context *ctx,
681
struct pipe_resource *texture,
682
const struct pipe_sampler_view *state,
683
unsigned width0, unsigned height0,
684
unsigned force_level);
685
void evergreen_init_common_regs(struct r600_context *ctx,
686
struct r600_command_buffer *cb,
687
enum chip_class ctx_chip_class,
688
enum radeon_family ctx_family,
690
void cayman_init_common_regs(struct r600_command_buffer *cb,
691
enum chip_class ctx_chip_class,
692
enum radeon_family ctx_family,
695
void evergreen_init_state_functions(struct r600_context *rctx);
696
void evergreen_init_atom_start_cs(struct r600_context *rctx);
697
void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
698
void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
699
void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
700
void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
701
void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
702
void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
703
void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
704
void *evergreen_create_resolve_blend(struct r600_context *rctx);
705
void *evergreen_create_decompress_blend(struct r600_context *rctx);
706
void *evergreen_create_fastclear_blend(struct r600_context *rctx);
707
bool evergreen_is_format_supported(struct pipe_screen *screen,
708
enum pipe_format format,
709
enum pipe_texture_target target,
710
unsigned sample_count,
711
unsigned storage_sample_count,
713
void evergreen_init_color_surface(struct r600_context *rctx,
714
struct r600_surface *surf);
715
void evergreen_init_color_surface_rat(struct r600_context *rctx,
716
struct r600_surface *surf);
717
void evergreen_update_db_shader_control(struct r600_context * rctx);
718
bool evergreen_adjust_gprs(struct r600_context *rctx);
719
void evergreen_setup_scratch_buffers(struct r600_context *rctx);
720
uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
723
void r600_init_blit_functions(struct r600_context *rctx);
724
void r600_decompress_depth_textures(struct r600_context *rctx,
725
struct r600_samplerview_state *textures);
726
void r600_decompress_depth_images(struct r600_context *rctx,
727
struct r600_image_state *images);
728
void r600_decompress_color_textures(struct r600_context *rctx,
729
struct r600_samplerview_state *textures);
730
void r600_decompress_color_images(struct r600_context *rctx,
731
struct r600_image_state *images);
732
void r600_resource_copy_region(struct pipe_context *ctx,
733
struct pipe_resource *dst,
735
unsigned dstx, unsigned dsty, unsigned dstz,
736
struct pipe_resource *src,
738
const struct pipe_box *src_box);
741
int r600_pipe_shader_create(struct pipe_context *ctx,
742
struct r600_pipe_shader *shader,
743
union r600_shader_key key);
745
void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
748
struct pipe_sampler_view *
749
r600_create_sampler_view_custom(struct pipe_context *ctx,
750
struct pipe_resource *texture,
751
const struct pipe_sampler_view *state,
752
unsigned width_first_level, unsigned height_first_level);
753
void r600_init_state_functions(struct r600_context *rctx);
754
void r600_init_atom_start_cs(struct r600_context *rctx);
755
void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
756
void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
757
void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
758
void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
759
void *r600_create_db_flush_dsa(struct r600_context *rctx);
760
void *r600_create_resolve_blend(struct r600_context *rctx);
761
void *r700_create_resolve_blend(struct r600_context *rctx);
762
void *r600_create_decompress_blend(struct r600_context *rctx);
763
bool r600_adjust_gprs(struct r600_context *rctx);
764
bool r600_is_format_supported(struct pipe_screen *screen,
765
enum pipe_format format,
766
enum pipe_texture_target target,
767
unsigned sample_count,
768
unsigned storage_sample_count,
770
void r600_update_db_shader_control(struct r600_context * rctx);
771
void r600_setup_scratch_buffers(struct r600_context *rctx);
773
/* r600_hw_context.c */
774
void r600_context_gfx_flush(void *context, unsigned flags,
775
struct pipe_fence_handle **fence);
776
void r600_begin_new_cs(struct r600_context *ctx);
777
void r600_flush_emit(struct r600_context *ctx);
778
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in, unsigned num_atomics);
779
void r600_emit_pfp_sync_me(struct r600_context *rctx);
780
void r600_cp_dma_copy_buffer(struct r600_context *rctx,
781
struct pipe_resource *dst, uint64_t dst_offset,
782
struct pipe_resource *src, uint64_t src_offset,
784
void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
785
struct pipe_resource *dst, uint64_t offset,
786
unsigned size, uint32_t clear_value,
787
enum r600_coherency coher);
788
void r600_dma_copy_buffer(struct r600_context *rctx,
789
struct pipe_resource *dst,
790
struct pipe_resource *src,
796
* evergreen_hw_context.c
798
void evergreen_dma_copy_buffer(struct r600_context *rctx,
799
struct pipe_resource *dst,
800
struct pipe_resource *src,
804
void evergreen_setup_tess_constants(struct r600_context *rctx,
805
const struct pipe_draw_info *info,
806
unsigned *num_patches);
807
uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
808
const struct pipe_draw_info *info,
809
unsigned num_patches);
810
void evergreen_set_ls_hs_config(struct r600_context *rctx,
811
struct radeon_cmdbuf *cs,
812
uint32_t ls_hs_config);
813
void evergreen_set_lds_alloc(struct r600_context *rctx,
814
struct radeon_cmdbuf *cs,
817
/* r600_state_common.c */
818
void r600_init_common_state_functions(struct r600_context *rctx);
819
void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
820
void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
821
void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
822
void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
823
void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
824
void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
825
void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
826
void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
827
void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
828
void (*emit)(struct r600_context *ctx, struct r600_atom *state),
830
void r600_vertex_buffers_dirty(struct r600_context *rctx);
831
void r600_sampler_views_dirty(struct r600_context *rctx,
832
struct r600_samplerview_state *state);
833
void r600_sampler_states_dirty(struct r600_context *rctx,
834
struct r600_sampler_states *state);
835
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
836
void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
837
void r600_setup_scratch_area_for_shader(struct r600_context *rctx,
838
struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch,
839
unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg);
840
uint32_t r600_translate_stencil_op(int s_op);
841
uint32_t r600_translate_fill(uint32_t func);
842
unsigned r600_tex_wrap(unsigned wrap);
843
unsigned r600_tex_mipfilter(unsigned filter);
844
unsigned r600_tex_compare(unsigned compare);
845
bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
846
unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
847
const unsigned char *swizzle_view,
849
uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
850
const unsigned char *swizzle_view,
851
uint32_t *word4_p, uint32_t *yuv_format_p,
852
bool do_endian_swap);
853
uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
854
bool do_endian_swap);
855
uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
858
struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
859
const struct pipe_video_codec *decoder);
861
struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
862
const struct pipe_video_buffer *tmpl);
865
* Helpers for building command buffers
868
#define PKT3_SET_CONFIG_REG 0x68
869
#define PKT3_SET_CONTEXT_REG 0x69
870
#define PKT3_SET_CTL_CONST 0x6F
871
#define PKT3_SET_LOOP_CONST 0x6C
873
#define R600_CONFIG_REG_OFFSET 0x08000
874
#define R600_CONTEXT_REG_OFFSET 0x28000
875
#define R600_CTL_CONST_OFFSET 0x3CFF0
876
#define R600_LOOP_CONST_OFFSET 0X0003E200
877
#define EG_LOOP_CONST_OFFSET 0x0003A200
879
#define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
880
#define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
881
#define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
882
#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
883
#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
885
#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
887
/*Evergreen Compute packet3*/
888
#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
890
static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
892
cb->buf[cb->num_dw++] = value;
895
static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
897
assert(cb->num_dw+num <= cb->max_num_dw);
898
memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
902
static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
904
assert(reg < R600_CONTEXT_REG_OFFSET);
905
assert(cb->num_dw+2+num <= cb->max_num_dw);
906
cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
907
cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
911
* Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
914
static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
916
assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
917
assert(cb->num_dw+2+num <= cb->max_num_dw);
918
cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
919
cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
923
* Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
926
static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
928
assert(reg >= R600_CTL_CONST_OFFSET);
929
assert(cb->num_dw+2+num <= cb->max_num_dw);
930
cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
931
cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
934
static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
936
assert(reg >= R600_LOOP_CONST_OFFSET);
937
assert(cb->num_dw+2+num <= cb->max_num_dw);
938
cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
939
cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
943
* Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
946
static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
948
assert(reg >= EG_LOOP_CONST_OFFSET);
949
assert(cb->num_dw+2+num <= cb->max_num_dw);
950
cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
951
cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
954
static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
956
r600_store_config_reg_seq(cb, reg, 1);
957
r600_store_value(cb, value);
960
static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
962
r600_store_context_reg_seq(cb, reg, 1);
963
r600_store_value(cb, value);
966
static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
968
r600_store_ctl_const_seq(cb, reg, 1);
969
r600_store_value(cb, value);
972
static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
974
r600_store_loop_const_seq(cb, reg, 1);
975
r600_store_value(cb, value);
978
static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
980
eg_store_loop_const_seq(cb, reg, 1);
981
r600_store_value(cb, value);
984
void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
985
void r600_release_command_buffer(struct r600_command_buffer *cb);
987
static inline void radeon_compute_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
989
radeon_set_context_reg_seq(cs, reg, num);
990
/* Set the compute bit on the packet header */
991
cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
994
static inline void radeon_set_ctl_const_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
996
assert(reg >= R600_CTL_CONST_OFFSET);
997
assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
998
radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
999
radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
1002
static inline void radeon_compute_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
1004
radeon_compute_set_context_reg_seq(cs, reg, 1);
1005
radeon_emit(cs, value);
1008
static inline void radeon_set_context_reg_flag(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned flag)
1010
if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
1011
radeon_compute_set_context_reg(cs, reg, value);
1013
radeon_set_context_reg(cs, reg, value);
1017
static inline void radeon_set_ctl_const(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
1019
radeon_set_ctl_const_seq(cs, reg, 1);
1020
radeon_emit(cs, value);
1027
/* 12.4 fixed-point */
1028
static inline unsigned r600_pack_float_12p4(float x)
1031
x >= 4096 ? 0xffff : x * 16;
1034
static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
1038
case R600_COHERENCY_NONE:
1040
case R600_COHERENCY_SHADER:
1041
return R600_CONTEXT_INV_CONST_CACHE |
1042
R600_CONTEXT_INV_VERTEX_CACHE |
1043
R600_CONTEXT_INV_TEX_CACHE |
1044
R600_CONTEXT_STREAMOUT_FLUSH;
1045
case R600_COHERENCY_CB_META:
1046
return R600_CONTEXT_FLUSH_AND_INV_CB |
1047
R600_CONTEXT_FLUSH_AND_INV_CB_META;
1051
#define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
1052
#define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
1053
#define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
1055
unsigned r600_conv_prim_to_gs_out(unsigned mode);
1057
void eg_trace_emit(struct r600_context *rctx);
1058
void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
1061
struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
1063
enum pipe_shader_ir,
1064
unsigned pipe_shader_type);
1065
int r600_shader_select(struct pipe_context *ctx,
1066
struct r600_pipe_shader_selector* sel,
1067
bool *dirty, bool precompile);
1069
void r600_delete_shader_selector(struct pipe_context *ctx,
1070
struct r600_pipe_shader_selector *sel);
1072
struct r600_shader_atomic;
1073
void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx,
1074
struct r600_pipe_shader *cs_shader,
1075
struct r600_shader_atomic *combined_atomics,
1076
uint8_t *atomic_used_mask_p);
1077
void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
1079
struct r600_shader_atomic *combined_atomics,
1080
uint8_t atomic_used_mask);
1081
void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
1083
struct r600_shader_atomic *combined_atomics,
1084
uint8_t *atomic_used_mask_p);
1085
void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only);
1087
void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type);
1088
void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only);
added
removed
src/gallium/drivers/r600/r600_pipe.h
