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# Copyright © 2021 Google, Inc.
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# Permission is hereby granted, free of charge, to any person obtaining a
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# copy of this software and associated documentation files (the "Software"),
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# to deal in the Software without restriction, including without limitation
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# the rights to use, copy, modify, merge, publish, distribute, sublicense,
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# and/or sell copies of the Software, and to permit persons to whom the
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# Software is furnished to do so, subject to the following conditions:
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# The above copyright notice and this permission notice (including the next
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# paragraph) shall be included in all copies or substantial portions of the
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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from mako.template import Template
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def max_bitfield_val(high, low, shift):
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return ((1 << (high - low)) - 1) << shift
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# List of unique device-info structs, multiple different GPU ids
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# can map to a single info struct in cases where the differences
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# are not sw visible, or the only differences are parameters
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# queried from the kernel (like GMEM size)
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# Table mapping GPU id to device-info struct
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def info_index(self, gpu_info):
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for info in self.gpu_infos:
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raise Error("invalid info")
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def add_gpus(ids, info):
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def __init__(self, gpu_id = None, chip_id = None, name=None):
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assert(gpu_id != None)
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major = int(val / 10);
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chip_id = (core << 24) | (major << 16) | (minor << 8) | 0xff
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self.chip_id = chip_id
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name = "FD%d" % gpu_id
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"""A helper class that stringifies itself to a 'C' struct initializer
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for name, value in vars(self).items():
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s += "." + name + "=" + str(value) + ","
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class GPUInfo(Struct):
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"""Base class for any generation of adreno, consists of GMEM layout
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Note that tile_max_h is normally only constrained by corresponding
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bitfield size/shift (ie. VSC_BIN_SIZE, or similar), but tile_max_h
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tends to have lower limits, in which case a comment will describe
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the bitfield size/shift
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def __init__(self, gmem_align_w, gmem_align_h,
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tile_align_w, tile_align_h,
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tile_max_w, tile_max_h, num_vsc_pipes):
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self.gmem_align_w = gmem_align_w
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self.gmem_align_h = gmem_align_h
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self.tile_align_w = tile_align_w
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self.tile_align_h = tile_align_h
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self.tile_max_w = tile_max_w
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self.tile_max_h = tile_max_h
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self.num_vsc_pipes = num_vsc_pipes
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s.gpu_infos.append(self)
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class A6xxGPUInfo(GPUInfo):
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"""The a6xx generation has a lot more parameters, and is broken down
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into distinct sub-generations. The template parameter avoids
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duplication of parameters that are unique to the sub-generation.
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def __init__(self, template, num_sp_cores, num_ccu,
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RB_UNKNOWN_8E04_blit, PC_POWER_CNTL):
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super().__init__(gmem_align_w = 16, gmem_align_h = 4,
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tile_align_w = 32, tile_align_h = 32,
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tile_max_w = 1024, # max_bitfield_val(5, 0, 5)
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tile_max_h = max_bitfield_val(14, 8, 4),
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assert(num_sp_cores == num_ccu)
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self.num_sp_cores = num_sp_cores
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# 96 tile alignment seems correlated to 3 CCU
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self.tile_align_w = 96
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self.a6xx.magic = Struct()
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for name, val in template["magic"].items():
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setattr(self.a6xx.magic, name, val)
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# Various "magic" register values:
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self.a6xx.magic.RB_UNKNOWN_8E04_blit = RB_UNKNOWN_8E04_blit
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self.a6xx.magic.PC_POWER_CNTL = PC_POWER_CNTL
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# Things that earlier gens have and later gens remove, provide
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# defaults here and let them be overridden by sub-gen template:
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self.a6xx.has_cp_reg_write = True
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self.a6xx.has_8bpp_ubwc = True
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for name, val in template.items():
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if name == "magic": # handled above
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setattr(self.a6xx, name, val)
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# a2xx is really two sub-generations, a20x and a22x, but we don't currently
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# capture that in the device-info tables
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gmem_align_w = 32, gmem_align_h = 32,
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tile_align_w = 32, tile_align_h = 32,
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tile_max_h = ~0, # TODO
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gmem_align_w = 32, gmem_align_h = 32,
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tile_align_w = 32, tile_align_h = 32,
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tile_max_w = 992, # max_bitfield_val(4, 0, 5)
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tile_max_h = max_bitfield_val(9, 5, 5),
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gmem_align_w = 32, gmem_align_h = 32,
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tile_align_w = 32, tile_align_h = 32,
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tile_max_w = 1024, # max_bitfield_val(4, 0, 5)
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tile_max_h = max_bitfield_val(9, 5, 5),
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gmem_align_w = 64, gmem_align_h = 32,
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tile_align_w = 64, tile_align_h = 32,
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tile_max_w = 1024, # max_bitfield_val(7, 0, 5)
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tile_max_h = max_bitfield_val(16, 9, 5),
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# a6xx can be divided into distinct sub-generations, where certain device-
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# info parameters are keyed to the sub-generation. These templates reduce
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fibers_per_sp = 128 * 16,
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instr_cache_size = 64,
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ccu_cntl_gmem_unk2 = True,
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indirect_draw_wfm_quirk = True,
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depth_bounds_require_depth_test_quirk = True,
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TPL1_DBG_ECO_CNTL = 0x100000,
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fibers_per_sp = 128 * 4 * 16,
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instr_cache_size = 64, # TODO
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supports_multiview_mask = True,
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has_z24uint_s8uint = True,
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indirect_draw_wfm_quirk = True,
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depth_bounds_require_depth_test_quirk = True, # TODO: check if true
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has_dp2acc = False, # TODO: check if true
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TPL1_DBG_ECO_CNTL = 0,
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fibers_per_sp = 128 * 2 * 16,
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# Blob limits it to 128 but we hang with 128
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instr_cache_size = 127,
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supports_multiview_mask = True,
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has_z24uint_s8uint = True,
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tess_use_shared = True,
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storage_16bit = True,
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has_tex_filter_cubic = True,
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has_sample_locations = True,
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has_ccu_flush_bug = True,
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has_8bpp_ubwc = False,
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# this seems to be a chicken bit that fixes cubic filtering:
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TPL1_DBG_ECO_CNTL = 0x1000000,
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fibers_per_sp = 128 * 2 * 16,
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# Blob limits it to 128 but we hang with 128
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instr_cache_size = 127,
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supports_multiview_mask = True,
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has_z24uint_s8uint = True,
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tess_use_shared = True,
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storage_16bit = True,
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has_tex_filter_cubic = True,
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has_sample_locations = True,
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has_ccu_flush_bug = True,
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has_cp_reg_write = False,
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has_8bpp_ubwc = False,
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has_shading_rate = True,
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has_getfiberid = True,
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TPL1_DBG_ECO_CNTL = 0x5008000,
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RB_UNKNOWN_8E04_blit = 0x00100000,
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RB_UNKNOWN_8E04_blit = 0x01000000,
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RB_UNKNOWN_8E04_blit = 0x00100000,
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RB_UNKNOWN_8E04_blit = 0x04100000,
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RB_UNKNOWN_8E04_blit = 0x04100000,
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GPUId(chip_id=0x00be06030500, name="Adreno 8c Gen 3"),
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GPUId(chip_id=0x007506030500, name="Adreno 7c+ Gen 3"),
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# fallback wildcard entry should be last:
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GPUId(chip_id=0xffff06030500, name="Adreno 7c+ Gen 3"),
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RB_UNKNOWN_8E04_blit = 0x00100000,
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RB_UNKNOWN_8E04_blit = 0x04100000,
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/* Copyright (C) 2021 Google, Inc.
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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#include "freedreno_dev_info.h"
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/* Map python to C: */
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%for info in s.gpu_infos:
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static const struct fd_dev_info __info${s.info_index(info)} = ${str(info)};
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static const struct fd_dev_rec fd_dev_recs[] = {
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%for id, info in s.gpus.items():
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{ {${id.gpu_id}, ${hex(id.chip_id)}}, "${id.name}", &__info${s.info_index(info)} },
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print(Template(template).render(s=s))