2
* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
24
#include "r600_opcodes.h"
25
#include "r600_formats.h"
26
#include "r600_shader.h"
30
#include "util/u_bitcast.h"
31
#include "util/u_dump.h"
32
#include "util/u_memory.h"
33
#include "util/u_math.h"
34
#include "pipe/p_shader_tokens.h"
36
#include "sb/sb_public.h"
38
#define NUM_OF_CYCLES 3
39
#define NUM_OF_COMPONENTS 4
41
static inline bool alu_writes(struct r600_bytecode_alu *alu)
43
return alu->dst.write || alu->is_op3;
46
static inline unsigned int r600_bytecode_get_num_operands(const struct r600_bytecode_alu *alu)
48
return r600_isa_alu(alu->op)->src_count;
51
static struct r600_bytecode_cf *r600_bytecode_cf(void)
53
struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
57
list_inithead(&cf->list);
58
list_inithead(&cf->alu);
59
list_inithead(&cf->vtx);
60
list_inithead(&cf->tex);
61
list_inithead(&cf->gds);
65
static struct r600_bytecode_alu *r600_bytecode_alu(void)
67
struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
71
list_inithead(&alu->list);
75
static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
77
struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
81
list_inithead(&vtx->list);
85
static struct r600_bytecode_tex *r600_bytecode_tex(void)
87
struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
91
list_inithead(&tex->list);
95
static struct r600_bytecode_gds *r600_bytecode_gds(void)
97
struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds);
101
list_inithead(&gds->list);
105
static unsigned stack_entry_size(enum radeon_family chip) {
107
* 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
108
* Aruba/Sumo/Sumo2/redwood/juniper
109
* 32: R630/R730/R710/Palm/Cedar
113
* Wavefront Size 16 32 48 64
114
* Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
115
* Columns per Row (R9xx+) 8 4 4 4 */
118
/* FIXME: are some chips missing here? */
119
/* wavefront size 16 */
124
/* wavefront size 32 */
133
/* wavefront size 64 */
139
void r600_bytecode_init(struct r600_bytecode *bc,
140
enum chip_class chip_class,
141
enum radeon_family family,
142
bool has_compressed_msaa_texturing)
144
static unsigned next_shader_id = 0;
146
bc->debug_id = ++next_shader_id;
148
if ((chip_class == R600) &&
149
(family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
150
bc->ar_handling = AR_HANDLE_RV6XX;
151
bc->r6xx_nop_after_rel_dst = 1;
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bc->ar_handling = AR_HANDLE_NORMAL;
154
bc->r6xx_nop_after_rel_dst = 0;
157
list_inithead(&bc->cf);
158
bc->chip_class = chip_class;
160
bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
161
bc->stack.entry_size = stack_entry_size(family);
164
int r600_bytecode_add_cf(struct r600_bytecode *bc)
166
struct r600_bytecode_cf *cf = r600_bytecode_cf();
170
list_addtail(&cf->list, &bc->cf);
172
cf->id = bc->cf_last->id + 2;
173
if (bc->cf_last->eg_alu_extended) {
174
/* take into account extended alu size */
182
bc->force_add_cf = 0;
187
int r600_bytecode_add_output(struct r600_bytecode *bc,
188
const struct r600_bytecode_output *output)
192
if (output->gpr >= bc->ngpr)
193
bc->ngpr = output->gpr + 1;
195
if (bc->cf_last && (bc->cf_last->op == output->op ||
196
(bc->cf_last->op == CF_OP_EXPORT &&
197
output->op == CF_OP_EXPORT_DONE)) &&
198
output->type == bc->cf_last->output.type &&
199
output->elem_size == bc->cf_last->output.elem_size &&
200
output->swizzle_x == bc->cf_last->output.swizzle_x &&
201
output->swizzle_y == bc->cf_last->output.swizzle_y &&
202
output->swizzle_z == bc->cf_last->output.swizzle_z &&
203
output->swizzle_w == bc->cf_last->output.swizzle_w &&
204
output->comp_mask == bc->cf_last->output.comp_mask &&
205
(output->burst_count + bc->cf_last->output.burst_count) <= 16) {
207
if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
208
(output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
210
bc->cf_last->op = bc->cf_last->output.op = output->op;
211
bc->cf_last->output.gpr = output->gpr;
212
bc->cf_last->output.array_base = output->array_base;
213
bc->cf_last->output.burst_count += output->burst_count;
216
} else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
217
output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
219
bc->cf_last->op = bc->cf_last->output.op = output->op;
220
bc->cf_last->output.burst_count += output->burst_count;
225
r = r600_bytecode_add_cf(bc);
228
bc->cf_last->op = output->op;
229
memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
230
bc->cf_last->barrier = 1;
234
int r600_bytecode_add_pending_output(struct r600_bytecode *bc,
235
const struct r600_bytecode_output *output)
237
assert(bc->n_pending_outputs + 1 < ARRAY_SIZE(bc->pending_outputs));
238
bc->pending_outputs[bc->n_pending_outputs++] = *output;
244
r600_bytecode_add_ack(struct r600_bytecode *bc)
246
bc->need_wait_ack = true;
250
r600_bytecode_wait_acks(struct r600_bytecode *bc)
252
/* Store acks are an R700+ feature. */
253
if (bc->chip_class < R700)
256
if (!bc->need_wait_ack)
259
int ret = r600_bytecode_add_cfinst(bc, CF_OP_WAIT_ACK);
263
struct r600_bytecode_cf *cf = bc->cf_last;
265
/* Request a wait if the number of outstanding acks is > 0 */
272
r600_bytecode_write_export_ack_type(struct r600_bytecode *bc, bool indirect)
274
if (bc->chip_class >= R700) {
276
return V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK_EG;
278
return V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_ACK_EG;
281
return V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
283
return V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
287
/* alu instructions that can ony exits once per group */
288
static int is_alu_once_inst(struct r600_bytecode_alu *alu)
290
return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED) || alu->is_lds_idx_op || alu->op == ALU_OP0_GROUP_BARRIER;
293
static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
295
return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
296
(r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
299
static int is_alu_mova_inst(struct r600_bytecode_alu *alu)
301
return r600_isa_alu(alu->op)->flags & AF_MOVA;
304
static int alu_uses_rel(struct r600_bytecode_alu *alu)
306
unsigned num_src = r600_bytecode_get_num_operands(alu);
313
for (src = 0; src < num_src; ++src) {
314
if (alu->src[src].rel) {
321
static int is_lds_read(int sel)
323
return sel == EG_V_SQ_ALU_SRC_LDS_OQ_A_POP || sel == EG_V_SQ_ALU_SRC_LDS_OQ_B_POP;
326
static int alu_uses_lds(struct r600_bytecode_alu *alu)
328
unsigned num_src = r600_bytecode_get_num_operands(alu);
331
for (src = 0; src < num_src; ++src) {
332
if (is_lds_read(alu->src[src].sel)) {
339
static int is_alu_64bit_inst(struct r600_bytecode_alu *alu)
341
const struct alu_op_info *op = r600_isa_alu(alu->op);
342
return (op->flags & AF_64);
345
static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
347
unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
348
return !(slots & AF_S);
351
static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
353
unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
354
return !(slots & AF_V);
357
/* alu instructions that can execute on any unit */
358
static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
360
unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
361
return slots == AF_VS;
364
static int is_nop_inst(struct r600_bytecode_alu *alu)
366
return alu->op == ALU_OP0_NOP;
369
static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
370
struct r600_bytecode_alu *assignment[5])
372
struct r600_bytecode_alu *alu;
373
unsigned i, chan, trans;
374
int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
376
for (i = 0; i < max_slots; i++)
377
assignment[i] = NULL;
379
for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
380
chan = alu->dst.chan;
383
else if (is_alu_trans_unit_inst(bc, alu))
385
else if (is_alu_vec_unit_inst(bc, alu))
387
else if (assignment[chan])
388
trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
394
assert(0); /* ALU.Trans has already been allocated. */
399
if (assignment[chan]) {
400
assert(0); /* ALU.chan has already been allocated. */
403
assignment[chan] = alu;
412
struct alu_bank_swizzle {
413
int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
414
int hw_cfile_addr[4];
415
int hw_cfile_elem[4];
418
static const unsigned cycle_for_bank_swizzle_vec[][3] = {
419
[SQ_ALU_VEC_012] = { 0, 1, 2 },
420
[SQ_ALU_VEC_021] = { 0, 2, 1 },
421
[SQ_ALU_VEC_120] = { 1, 2, 0 },
422
[SQ_ALU_VEC_102] = { 1, 0, 2 },
423
[SQ_ALU_VEC_201] = { 2, 0, 1 },
424
[SQ_ALU_VEC_210] = { 2, 1, 0 }
427
static const unsigned cycle_for_bank_swizzle_scl[][3] = {
428
[SQ_ALU_SCL_210] = { 2, 1, 0 },
429
[SQ_ALU_SCL_122] = { 1, 2, 2 },
430
[SQ_ALU_SCL_212] = { 2, 1, 2 },
431
[SQ_ALU_SCL_221] = { 2, 2, 1 }
434
static void init_bank_swizzle(struct alu_bank_swizzle *bs)
436
int i, cycle, component;
438
for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
439
for (component = 0; component < NUM_OF_COMPONENTS; component++)
440
bs->hw_gpr[cycle][component] = -1;
441
for (i = 0; i < 4; i++)
442
bs->hw_cfile_addr[i] = -1;
443
for (i = 0; i < 4; i++)
444
bs->hw_cfile_elem[i] = -1;
447
static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
449
if (bs->hw_gpr[cycle][chan] == -1)
450
bs->hw_gpr[cycle][chan] = sel;
451
else if (bs->hw_gpr[cycle][chan] != (int)sel) {
452
/* Another scalar operation has already used the GPR read port for the channel. */
458
static int reserve_cfile(const struct r600_bytecode *bc,
459
struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
461
int res, num_res = 4;
462
if (bc->chip_class >= R700) {
466
for (res = 0; res < num_res; ++res) {
467
if (bs->hw_cfile_addr[res] == -1) {
468
bs->hw_cfile_addr[res] = sel;
469
bs->hw_cfile_elem[res] = chan;
471
} else if (bs->hw_cfile_addr[res] == sel &&
472
bs->hw_cfile_elem[res] == chan)
473
return 0; /* Read for this scalar element already reserved, nothing to do here. */
475
/* All cfile read ports are used, cannot reference vector element. */
479
static int is_gpr(unsigned sel)
484
/* CB constants start at 512, and get translated to a kcache index when ALU
485
* clauses are constructed. Note that we handle kcache constants the same way
486
* as (the now gone) cfile constants, is that really required? */
487
static int is_kcache(unsigned sel)
489
return (sel > 511 && sel < 4607) || /* Kcache before translation. */
490
(sel > 127 && sel < 192) || /* Kcache 0 & 1 after translation. */
491
(sel > 256 && sel < 320); /* Kcache 2 & 3 after translation (EG). */
494
static int is_const(int sel)
496
return is_kcache(sel) ||
497
(sel >= V_SQ_ALU_SRC_0 &&
498
sel <= V_SQ_ALU_SRC_LITERAL);
501
static int check_vector(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
502
struct alu_bank_swizzle *bs, int bank_swizzle)
504
int r, src, num_src, sel, elem, cycle;
506
num_src = r600_bytecode_get_num_operands(alu);
507
for (src = 0; src < num_src; src++) {
508
sel = alu->src[src].sel;
509
elem = alu->src[src].chan;
511
cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
512
if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
513
/* Nothing to do; special-case optimization,
514
* second source uses first source’s reservation. */
517
r = reserve_gpr(bs, sel, elem, cycle);
521
} else if (is_kcache(sel)) {
522
r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
526
/* No restrictions on PV, PS, literal or special constants. */
531
static int check_scalar(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
532
struct alu_bank_swizzle *bs, int bank_swizzle)
534
int r, src, num_src, const_count, sel, elem, cycle;
536
num_src = r600_bytecode_get_num_operands(alu);
537
for (const_count = 0, src = 0; src < num_src; ++src) {
538
sel = alu->src[src].sel;
539
elem = alu->src[src].chan;
540
if (is_const(sel)) { /* Any constant, including literal and inline constants. */
541
if (const_count >= 2)
542
/* More than two references to a constant in
543
* transcendental operation. */
548
if (is_kcache(sel)) {
549
r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
554
for (src = 0; src < num_src; ++src) {
555
sel = alu->src[src].sel;
556
elem = alu->src[src].chan;
558
cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
559
if (cycle < const_count)
560
/* Cycle for GPR load conflicts with
561
* constant load in transcendental operation. */
563
r = reserve_gpr(bs, sel, elem, cycle);
567
/* PV PS restrictions */
568
if (const_count && (sel == 254 || sel == 255)) {
569
cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
570
if (cycle < const_count)
577
static int check_and_set_bank_swizzle(const struct r600_bytecode *bc,
578
struct r600_bytecode_alu *slots[5])
580
struct alu_bank_swizzle bs;
582
int i, r = 0, forced = 1;
583
boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
584
int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
586
for (i = 0; i < max_slots; i++) {
588
if (slots[i]->bank_swizzle_force) {
589
slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
595
if (i < 4 && slots[i])
601
/* Just check every possible combination of bank swizzle.
602
* Not very efficent, but works on the first try in most of the cases. */
603
for (i = 0; i < 4; i++)
604
if (!slots[i] || !slots[i]->bank_swizzle_force)
605
bank_swizzle[i] = SQ_ALU_VEC_012;
607
bank_swizzle[i] = slots[i]->bank_swizzle;
609
bank_swizzle[4] = SQ_ALU_SCL_210;
610
while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
612
init_bank_swizzle(&bs);
613
if (scalar_only == false) {
614
for (i = 0; i < 4; i++) {
616
r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
624
if (!r && max_slots == 5 && slots[4]) {
625
r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
628
for (i = 0; i < max_slots; i++) {
630
slots[i]->bank_swizzle = bank_swizzle[i];
638
for (i = 0; i < max_slots; i++) {
639
if (!slots[i] || !slots[i]->bank_swizzle_force) {
641
if (bank_swizzle[i] <= SQ_ALU_VEC_210)
643
else if (i < max_slots - 1)
644
bank_swizzle[i] = SQ_ALU_VEC_012;
652
/* Couldn't find a working swizzle. */
656
static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
657
struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
659
struct r600_bytecode_alu *prev[5];
661
int i, j, r, src, num_src;
662
int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
664
r = assign_alu_units(bc, alu_prev, prev);
668
for (i = 0; i < max_slots; ++i) {
669
if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
671
if (is_alu_64bit_inst(prev[i])) {
676
gpr[i] = prev[i]->dst.sel;
677
/* cube writes more than PV.X */
678
if (is_alu_reduction_inst(bc, prev[i]))
681
chan[i] = prev[i]->dst.chan;
686
for (i = 0; i < max_slots; ++i) {
687
struct r600_bytecode_alu *alu = slots[i];
691
if (is_alu_64bit_inst(alu))
693
num_src = r600_bytecode_get_num_operands(alu);
694
for (src = 0; src < num_src; ++src) {
695
if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
698
if (bc->chip_class < CAYMAN) {
699
if (alu->src[src].sel == gpr[4] &&
700
alu->src[src].chan == chan[4] &&
701
alu_prev->pred_sel == alu->pred_sel) {
702
alu->src[src].sel = V_SQ_ALU_SRC_PS;
703
alu->src[src].chan = 0;
708
for (j = 0; j < 4; ++j) {
709
if (alu->src[src].sel == gpr[j] &&
710
alu->src[src].chan == j &&
711
alu_prev->pred_sel == alu->pred_sel) {
712
alu->src[src].sel = V_SQ_ALU_SRC_PV;
713
alu->src[src].chan = chan[j];
723
void r600_bytecode_special_constants(uint32_t value, unsigned *sel)
727
*sel = V_SQ_ALU_SRC_0;
730
*sel = V_SQ_ALU_SRC_1_INT;
733
*sel = V_SQ_ALU_SRC_M_1_INT;
735
case 0x3F800000: /* 1.0f */
736
*sel = V_SQ_ALU_SRC_1;
738
case 0x3F000000: /* 0.5f */
739
*sel = V_SQ_ALU_SRC_0_5;
742
*sel = V_SQ_ALU_SRC_LITERAL;
747
/* compute how many literal are needed */
748
static int r600_bytecode_alu_nliterals(struct r600_bytecode_alu *alu,
749
uint32_t literal[4], unsigned *nliteral)
751
unsigned num_src = r600_bytecode_get_num_operands(alu);
754
for (i = 0; i < num_src; ++i) {
755
if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
756
uint32_t value = alu->src[i].value;
758
for (j = 0; j < *nliteral; ++j) {
759
if (literal[j] == value) {
767
literal[(*nliteral)++] = value;
774
static void r600_bytecode_alu_adjust_literals(struct r600_bytecode_alu *alu,
775
uint32_t literal[4], unsigned nliteral)
777
unsigned num_src = r600_bytecode_get_num_operands(alu);
780
for (i = 0; i < num_src; ++i) {
781
if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
782
uint32_t value = alu->src[i].value;
783
for (j = 0; j < nliteral; ++j) {
784
if (literal[j] == value) {
785
alu->src[i].chan = j;
793
static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
794
struct r600_bytecode_alu *alu_prev)
796
struct r600_bytecode_alu *prev[5];
797
struct r600_bytecode_alu *result[5] = { NULL };
799
uint8_t interp_xz = 0;
801
uint32_t literal[4], prev_literal[4];
802
unsigned nliteral = 0, prev_nliteral = 0;
804
int i, j, r, src, num_src;
805
int num_once_inst = 0;
806
int have_mova = 0, have_rel = 0;
807
int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
809
r = assign_alu_units(bc, alu_prev, prev);
813
for (i = 0; i < max_slots; ++i) {
815
if (prev[i]->pred_sel)
817
if (is_alu_once_inst(prev[i]))
820
if (prev[i]->op == ALU_OP1_INTERP_LOAD_P0)
822
if (prev[i]->op == ALU_OP2_INTERP_X)
824
if (prev[i]->op == ALU_OP2_INTERP_Z)
828
if (slots[i]->pred_sel)
830
if (is_alu_once_inst(slots[i]))
832
if (slots[i]->op == ALU_OP1_INTERP_LOAD_P0)
834
if (slots[i]->op == ALU_OP2_INTERP_X)
836
if (slots[i]->op == ALU_OP2_INTERP_Z)
843
for (i = 0; i < max_slots; ++i) {
844
struct r600_bytecode_alu *alu;
846
if (num_once_inst > 0)
849
/* check number of literals */
851
if (r600_bytecode_alu_nliterals(prev[i], literal, &nliteral))
853
if (r600_bytecode_alu_nliterals(prev[i], prev_literal, &prev_nliteral))
855
if (is_alu_mova_inst(prev[i])) {
861
if (alu_uses_rel(prev[i])) {
867
if (alu_uses_lds(prev[i]))
870
num_once_inst += is_alu_once_inst(prev[i]);
872
if (slots[i] && r600_bytecode_alu_nliterals(slots[i], literal, &nliteral))
875
/* Let's check used slots. */
876
if (prev[i] && !slots[i]) {
879
} else if (prev[i] && slots[i]) {
880
if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
881
/* Trans unit is still free try to use it. */
882
if (is_alu_any_unit_inst(bc, slots[i]) && !alu_uses_lds(slots[i])) {
884
result[4] = slots[i];
885
} else if (is_alu_any_unit_inst(bc, prev[i])) {
886
if (slots[i]->dst.sel == prev[i]->dst.sel &&
887
alu_writes(slots[i]) &&
891
result[i] = slots[i];
897
} else if(!slots[i]) {
900
if (max_slots == 5 && slots[i] && prev[4] &&
901
slots[i]->dst.sel == prev[4]->dst.sel &&
902
slots[i]->dst.chan == prev[4]->dst.chan &&
903
alu_writes(slots[i]) &&
907
result[i] = slots[i];
911
num_once_inst += is_alu_once_inst(alu);
913
/* don't reschedule NOPs */
914
if (is_nop_inst(alu))
917
if (is_alu_mova_inst(alu)) {
924
if (alu_uses_rel(alu)) {
931
if (alu->op == ALU_OP0_SET_CF_IDX0 ||
932
alu->op == ALU_OP0_SET_CF_IDX1)
933
return 0; /* data hazard with MOVA */
935
/* Let's check source gprs */
936
num_src = r600_bytecode_get_num_operands(alu);
937
for (src = 0; src < num_src; ++src) {
939
/* Constants don't matter. */
940
if (!is_gpr(alu->src[src].sel))
943
for (j = 0; j < max_slots; ++j) {
944
if (!prev[j] || !alu_writes(prev[j]))
947
/* If it's relative then we can't determin which gpr is really used. */
948
if (prev[j]->dst.chan == alu->src[src].chan &&
949
(prev[j]->dst.sel == alu->src[src].sel ||
950
prev[j]->dst.rel || alu->src[src].rel))
956
/* more than one PRED_ or KILL_ ? */
957
if (num_once_inst > 1)
960
/* check if the result can still be swizzlet */
961
r = check_and_set_bank_swizzle(bc, result);
965
/* looks like everything worked out right, apply the changes */
967
/* undo adding previus literals */
968
bc->cf_last->ndw -= align(prev_nliteral, 2);
970
/* sort instructions */
971
for (i = 0; i < max_slots; ++i) {
972
slots[i] = result[i];
974
list_del(&result[i]->list);
976
list_addtail(&result[i]->list, &bc->cf_last->alu);
980
/* determine new last instruction */
981
LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
983
/* determine new first instruction */
984
for (i = 0; i < max_slots; ++i) {
986
bc->cf_last->curr_bs_head = result[i];
991
bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
992
bc->cf_last->prev2_bs_head = NULL;
997
/* we'll keep kcache sets sorted by bank & addr */
998
static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
999
struct r600_bytecode_kcache *kcache,
1000
unsigned bank, unsigned line, unsigned index_mode)
1002
int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
1004
for (i = 0; i < kcache_banks; i++) {
1005
if (kcache[i].mode) {
1008
if (kcache[i].bank < bank)
1011
if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1012
kcache[i].bank > bank) {
1013
/* try to insert new line */
1014
if (kcache[kcache_banks-1].mode) {
1015
/* all sets are in use */
1019
memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1020
kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1021
kcache[i].bank = bank;
1022
kcache[i].addr = line;
1023
kcache[i].index_mode = index_mode;
1027
d = line - kcache[i].addr;
1031
if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1032
/* we are prepending the line to the current set,
1033
* discarding the existing second line,
1034
* so we'll have to insert line+2 after it */
1037
} else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1038
kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1041
/* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1044
} else if (d == 1) {
1045
kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1049
} else { /* free kcache set - use it */
1050
kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1051
kcache[i].bank = bank;
1052
kcache[i].addr = line;
1053
kcache[i].index_mode = index_mode;
1060
static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1061
struct r600_bytecode_kcache *kcache,
1062
struct r600_bytecode_alu *alu)
1066
for (i = 0; i < 3; i++) {
1067
unsigned bank, line, sel = alu->src[i].sel, index_mode;
1072
bank = alu->src[i].kc_bank;
1073
assert(bank < R600_MAX_HW_CONST_BUFFERS);
1074
line = (sel-512)>>4;
1075
index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
1077
if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
1083
static int r600_bytecode_assign_kcache_banks(
1084
struct r600_bytecode_alu *alu,
1085
struct r600_bytecode_kcache * kcache)
1089
/* Alter the src operands to refer to the kcache. */
1090
for (i = 0; i < 3; ++i) {
1091
static const unsigned int base[] = {128, 160, 256, 288};
1092
unsigned int line, sel = alu->src[i].sel, found = 0;
1100
for (j = 0; j < 4 && !found; ++j) {
1101
switch (kcache[j].mode) {
1102
case V_SQ_CF_KCACHE_NOP:
1103
case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1104
R600_ERR("unexpected kcache line mode\n");
1107
if (kcache[j].bank == alu->src[i].kc_bank &&
1108
kcache[j].addr <= line &&
1109
line < kcache[j].addr + kcache[j].mode) {
1110
alu->src[i].sel = sel - (kcache[j].addr<<4);
1111
alu->src[i].sel += base[j];
1120
static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1121
struct r600_bytecode_alu *alu,
1124
struct r600_bytecode_kcache kcache_sets[4];
1125
struct r600_bytecode_kcache *kcache = kcache_sets;
1128
memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1130
if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1131
/* can't alloc, need to start new clause */
1133
/* Make sure the CF ends with an "last" instruction when
1134
* we split an ALU group because of a new CF */
1135
if (!list_is_empty(&bc->cf_last->alu)) {
1136
struct r600_bytecode_alu *last_submitted =
1137
list_last_entry(&bc->cf_last->alu, struct r600_bytecode_alu, list);
1138
last_submitted->last = 1;
1141
if ((r = r600_bytecode_add_cf(bc))) {
1144
bc->cf_last->op = type;
1146
/* retry with the new clause */
1147
kcache = bc->cf_last->kcache;
1148
if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1149
/* can't alloc again- should never happen */
1153
/* update kcache sets */
1154
memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1157
/* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1158
if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1159
kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1160
if (bc->chip_class < EVERGREEN)
1162
bc->cf_last->eg_alu_extended = 1;
1168
static int insert_nop_r6xx(struct r600_bytecode *bc, int max_slots)
1170
struct r600_bytecode_alu alu;
1173
for (i = 0; i < max_slots; i++) {
1174
memset(&alu, 0, sizeof(alu));
1175
alu.op = ALU_OP0_NOP;
1176
alu.src[0].chan = i & 3;
1177
alu.dst.chan = i & 3;
1178
alu.last = (i == max_slots - 1);
1179
r = r600_bytecode_add_alu(bc, &alu);
1186
/* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1187
static int load_ar_r6xx(struct r600_bytecode *bc)
1189
struct r600_bytecode_alu alu;
1195
/* hack to avoid making MOVA the last instruction in the clause */
1196
if ((bc->cf_last->ndw>>1) >= 110)
1197
bc->force_add_cf = 1;
1199
memset(&alu, 0, sizeof(alu));
1200
alu.op = ALU_OP1_MOVA_GPR_INT;
1201
alu.src[0].sel = bc->ar_reg;
1202
alu.src[0].chan = bc->ar_chan;
1204
alu.index_mode = INDEX_MODE_LOOP;
1205
r = r600_bytecode_add_alu(bc, &alu);
1209
/* no requirement to set uses waterfall on MOVA_GPR_INT */
1214
/* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1215
int r600_load_ar(struct r600_bytecode *bc)
1217
struct r600_bytecode_alu alu;
1220
if (bc->ar_handling)
1221
return load_ar_r6xx(bc);
1226
/* hack to avoid making MOVA the last instruction in the clause */
1227
if ((bc->cf_last->ndw>>1) >= 110)
1228
bc->force_add_cf = 1;
1230
memset(&alu, 0, sizeof(alu));
1231
alu.op = ALU_OP1_MOVA_INT;
1232
alu.src[0].sel = bc->ar_reg;
1233
alu.src[0].chan = bc->ar_chan;
1235
r = r600_bytecode_add_alu(bc, &alu);
1239
bc->cf_last->r6xx_uses_waterfall = 1;
1244
int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1245
const struct r600_bytecode_alu *alu, unsigned type)
1247
struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1248
struct r600_bytecode_alu *lalu;
1253
memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1256
/* will fail later since alu does not support it. */
1257
assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1260
if (bc->cf_last != NULL && bc->cf_last->op != type) {
1261
/* check if we could add it anyway */
1262
if (bc->cf_last->op == CF_OP_ALU &&
1263
type == CF_OP_ALU_PUSH_BEFORE) {
1264
LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1265
if (lalu->execute_mask) {
1266
bc->force_add_cf = 1;
1271
bc->force_add_cf = 1;
1274
/* cf can contains only alu or only vtx or only tex */
1275
if (bc->cf_last == NULL || bc->force_add_cf) {
1276
if (bc->cf_last && bc->cf_last->curr_bs_head)
1277
bc->cf_last->curr_bs_head->last = 1;
1278
r = r600_bytecode_add_cf(bc);
1284
bc->cf_last->op = type;
1286
/* Load index register if required */
1287
if (bc->chip_class >= EVERGREEN) {
1288
for (i = 0; i < 3; i++)
1289
if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1290
egcm_load_index_reg(bc, 0, true);
1293
/* Check AR usage and load it if required */
1294
for (i = 0; i < 3; i++)
1295
if (nalu->src[i].rel && !bc->ar_loaded)
1298
if (nalu->dst.rel && !bc->ar_loaded)
1301
/* Setup the kcache for this ALU instruction. This will start a new
1302
* ALU clause if needed. */
1303
if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1308
if (!bc->cf_last->curr_bs_head) {
1309
bc->cf_last->curr_bs_head = nalu;
1311
/* number of gpr == the last gpr used in any alu */
1312
for (i = 0; i < 3; i++) {
1313
if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1314
bc->ngpr = nalu->src[i].sel + 1;
1316
if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1317
r600_bytecode_special_constants(nalu->src[i].value,
1320
if (nalu->dst.write && nalu->dst.sel >= bc->ngpr) {
1321
bc->ngpr = nalu->dst.sel + 1;
1323
list_addtail(&nalu->list, &bc->cf_last->alu);
1324
/* each alu use 2 dwords */
1325
bc->cf_last->ndw += 2;
1328
/* process cur ALU instructions for bank swizzle */
1330
uint32_t literal[4];
1332
struct r600_bytecode_alu *slots[5];
1333
int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1334
r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1338
if (bc->cf_last->prev_bs_head) {
1339
r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1344
if (bc->cf_last->prev_bs_head) {
1345
r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1350
r = check_and_set_bank_swizzle(bc, slots);
1354
for (i = 0, nliteral = 0; i < max_slots; i++) {
1356
r = r600_bytecode_alu_nliterals(slots[i], literal, &nliteral);
1361
bc->cf_last->ndw += align(nliteral, 2);
1363
/* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1365
if ((bc->cf_last->ndw >> 1) >= 120) {
1366
bc->force_add_cf = 1;
1369
bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1370
bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1371
bc->cf_last->curr_bs_head = NULL;
1373
if (bc->r6xx_nop_after_rel_dst) {
1374
for (int i = 0; i < max_slots; ++i) {
1375
if (slots[i] && slots[i]->dst.rel) {
1376
insert_nop_r6xx(bc, max_slots);
1383
/* Might need to insert spill write ops after current clause */
1384
if (nalu->last && bc->n_pending_outputs) {
1385
while (bc->n_pending_outputs) {
1386
r = r600_bytecode_add_output(bc, &bc->pending_outputs[--bc->n_pending_outputs]);
1395
int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1397
return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1400
static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1402
switch (bc->chip_class) {
1412
R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1417
static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1419
return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1420
bc->cf_last->op != CF_OP_GDS &&
1421
(bc->chip_class == CAYMAN ||
1422
bc->cf_last->op != CF_OP_TEX));
1425
static int r600_bytecode_add_vtx_internal(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx,
1428
struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1433
memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1435
/* Load index register if required */
1436
if (bc->chip_class >= EVERGREEN) {
1437
if (vtx->buffer_index_mode)
1438
egcm_load_index_reg(bc, vtx->buffer_index_mode - 1, false);
1441
/* cf can contains only alu or only vtx or only tex */
1442
if (bc->cf_last == NULL ||
1443
last_inst_was_not_vtx_fetch(bc) ||
1445
r = r600_bytecode_add_cf(bc);
1450
switch (bc->chip_class) {
1453
bc->cf_last->op = CF_OP_VTX;
1457
bc->cf_last->op = CF_OP_TEX;
1459
bc->cf_last->op = CF_OP_VTX;
1462
bc->cf_last->op = CF_OP_TEX;
1465
R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1470
list_addtail(&nvtx->list, &bc->cf_last->vtx);
1471
/* each fetch use 4 dwords */
1472
bc->cf_last->ndw += 4;
1474
if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1475
bc->force_add_cf = 1;
1477
bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1478
bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1483
int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1485
return r600_bytecode_add_vtx_internal(bc, vtx, false);
1488
int r600_bytecode_add_vtx_tc(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1490
return r600_bytecode_add_vtx_internal(bc, vtx, true);
1493
int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1495
struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1500
memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1502
/* Load index register if required */
1503
if (bc->chip_class >= EVERGREEN) {
1504
if (tex->sampler_index_mode || tex->resource_index_mode)
1505
egcm_load_index_reg(bc, 1, false);
1508
/* we can't fetch data und use it as texture lookup address in the same TEX clause */
1509
if (bc->cf_last != NULL &&
1510
bc->cf_last->op == CF_OP_TEX) {
1511
struct r600_bytecode_tex *ttex;
1512
LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1513
if (ttex->dst_gpr == ntex->src_gpr &&
1514
(ttex->dst_sel_x < 4 || ttex->dst_sel_y < 4 ||
1515
ttex->dst_sel_z < 4 || ttex->dst_sel_w < 4)) {
1516
bc->force_add_cf = 1;
1520
/* vtx instrs get inserted after tex, so make sure we aren't moving the tex
1521
* before (say) the instr fetching the texcoord.
1523
if (!list_is_empty(&bc->cf_last->vtx))
1524
bc->force_add_cf = 1;
1526
/* slight hack to make gradients always go into same cf */
1527
if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1528
bc->force_add_cf = 1;
1531
/* cf can contains only alu or only vtx or only tex */
1532
if (bc->cf_last == NULL ||
1533
bc->cf_last->op != CF_OP_TEX ||
1535
r = r600_bytecode_add_cf(bc);
1540
bc->cf_last->op = CF_OP_TEX;
1542
if (ntex->src_gpr >= bc->ngpr) {
1543
bc->ngpr = ntex->src_gpr + 1;
1545
if (ntex->dst_gpr >= bc->ngpr) {
1546
bc->ngpr = ntex->dst_gpr + 1;
1548
list_addtail(&ntex->list, &bc->cf_last->tex);
1549
/* each texture fetch use 4 dwords */
1550
bc->cf_last->ndw += 4;
1552
if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1553
bc->force_add_cf = 1;
1557
int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_gds *gds)
1559
struct r600_bytecode_gds *ngds = r600_bytecode_gds();
1564
memcpy(ngds, gds, sizeof(struct r600_bytecode_gds));
1566
if (bc->chip_class >= EVERGREEN) {
1567
if (gds->uav_index_mode)
1568
egcm_load_index_reg(bc, gds->uav_index_mode - 1, false);
1571
if (bc->cf_last == NULL ||
1572
bc->cf_last->op != CF_OP_GDS ||
1574
r = r600_bytecode_add_cf(bc);
1579
bc->cf_last->op = CF_OP_GDS;
1582
list_addtail(&ngds->list, &bc->cf_last->gds);
1583
bc->cf_last->ndw += 4; /* each GDS uses 4 dwords */
1584
if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1585
bc->force_add_cf = 1;
1589
int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1593
/* Emit WAIT_ACK before control flow to ensure pending writes are always acked. */
1594
if (op != CF_OP_WAIT_ACK && op != CF_OP_MEM_SCRATCH)
1595
r600_bytecode_wait_acks(bc);
1597
r = r600_bytecode_add_cf(bc);
1601
bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1602
bc->cf_last->op = op;
1606
int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1608
return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1611
/* common to all 3 families */
1612
static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1614
if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
1615
return r700_bytecode_fetch_mem_build(bc, vtx, id);
1616
bc->bytecode[id] = S_SQ_VTX_WORD0_VTX_INST(r600_isa_fetch_opcode(bc->isa->hw_class, vtx->op)) |
1617
S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1618
S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1619
S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1620
S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1621
if (bc->chip_class < CAYMAN)
1622
bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1624
bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1625
S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1626
S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1627
S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1628
S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1629
S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1630
S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1631
S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1632
S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1633
S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1634
bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1635
S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1636
if (bc->chip_class >= EVERGREEN)
1637
bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1638
if (bc->chip_class < CAYMAN)
1639
bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1641
bc->bytecode[id++] = 0;
1645
/* common to all 3 families */
1646
static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1648
bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1649
r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1650
EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1651
S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1652
S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1653
S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1654
if (bc->chip_class >= EVERGREEN)
1655
bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1656
((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1658
bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1659
S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1660
S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1661
S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1662
S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1663
S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1664
S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1665
S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1666
S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1667
S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1668
S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1669
bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1670
S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1671
S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1672
S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1673
S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1674
S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1675
S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1676
S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1677
bc->bytecode[id++] = 0;
1681
/* r600 only, r700/eg bits in r700_asm.c */
1682
static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1684
unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1686
/* don't replace gpr by pv or ps for destination register */
1687
bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1688
S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1689
S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1690
S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1691
S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1692
S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1693
S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1694
S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1695
S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1696
S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1697
S_SQ_ALU_WORD0_LAST(alu->last);
1700
assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1701
bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1702
S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1703
S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1704
S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1705
S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1706
S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1707
S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1708
S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1709
S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1710
S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1712
bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1713
S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1714
S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1715
S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1716
S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1717
S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1718
S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1719
S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1720
S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1721
S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1722
S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1723
S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1728
static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1730
*bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1731
*bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1732
S_SQ_CF_WORD1_BARRIER(1) |
1733
S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1)|
1734
S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1737
/* common for r600/r700 - eg in eg_asm.c */
1738
static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1740
unsigned id = cf->id;
1741
const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1742
unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1745
if (cf->op == CF_NATIVE) {
1746
bc->bytecode[id++] = cf->isa[0];
1747
bc->bytecode[id++] = cf->isa[1];
1748
} else if (cfop->flags & CF_ALU) {
1749
bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1750
S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1751
S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1752
S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1754
bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1755
S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1756
S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1757
S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1758
S_SQ_CF_ALU_WORD1_BARRIER(1) |
1759
S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1760
S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1761
} else if (cfop->flags & CF_FETCH) {
1762
if (bc->chip_class == R700)
1763
r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1765
r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1766
} else if (cfop->flags & CF_EXP) {
1767
bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1768
S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1769
S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1770
S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1771
S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1772
bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1773
S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1774
S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1775
S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1776
S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1777
S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1778
S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1779
S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1780
} else if (cfop->flags & CF_MEM) {
1781
bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1782
S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1783
S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1784
S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1785
S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1786
bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1787
S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1788
S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1789
S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1790
S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1791
S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1793
bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1794
bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1795
S_SQ_CF_WORD1_BARRIER(1) |
1796
S_SQ_CF_WORD1_COND(cf->cond) |
1797
S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1798
S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1803
int r600_bytecode_build(struct r600_bytecode *bc)
1805
struct r600_bytecode_cf *cf;
1806
struct r600_bytecode_alu *alu;
1807
struct r600_bytecode_vtx *vtx;
1808
struct r600_bytecode_tex *tex;
1809
struct r600_bytecode_gds *gds;
1810
uint32_t literal[4];
1815
if (!bc->nstack) { // If not 0, Stack_size already provided by llvm
1816
if (bc->stack.max_entries)
1817
bc->nstack = bc->stack.max_entries;
1818
else if (bc->type == PIPE_SHADER_VERTEX ||
1819
bc->type == PIPE_SHADER_TESS_EVAL ||
1820
bc->type == PIPE_SHADER_TESS_CTRL)
1824
/* first path compute addr of each CF block */
1825
/* addr start after all the CF instructions */
1826
addr = bc->cf_last->id + 2;
1827
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1828
if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1830
addr &= 0xFFFFFFFCUL;
1834
bc->ndw = cf->addr + cf->ndw;
1837
bc->bytecode = calloc(4, bc->ndw);
1838
if (bc->bytecode == NULL)
1840
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1841
const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1843
if (bc->chip_class >= EVERGREEN)
1844
r = eg_bytecode_cf_build(bc, cf);
1846
r = r600_bytecode_cf_build(bc, cf);
1849
if (cfop->flags & CF_ALU) {
1851
memset(literal, 0, sizeof(literal));
1852
LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1853
r = r600_bytecode_alu_nliterals(alu, literal, &nliteral);
1856
r600_bytecode_alu_adjust_literals(alu, literal, nliteral);
1857
r600_bytecode_assign_kcache_banks(alu, cf->kcache);
1859
switch(bc->chip_class) {
1861
r = r600_bytecode_alu_build(bc, alu, addr);
1864
r = r700_bytecode_alu_build(bc, alu, addr);
1868
r = eg_bytecode_alu_build(bc, alu, addr);
1871
R600_ERR("unknown chip class %d.\n", bc->chip_class);
1878
for (i = 0; i < align(nliteral, 2); ++i) {
1879
bc->bytecode[addr++] = literal[i];
1882
memset(literal, 0, sizeof(literal));
1885
} else if (cf->op == CF_OP_VTX) {
1886
LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1887
r = r600_bytecode_vtx_build(bc, vtx, addr);
1892
} else if (cf->op == CF_OP_GDS) {
1893
assert(bc->chip_class >= EVERGREEN);
1894
LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
1895
r = eg_bytecode_gds_build(bc, gds, addr);
1900
} else if (cf->op == CF_OP_TEX) {
1901
LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1902
assert(bc->chip_class >= EVERGREEN);
1903
r = r600_bytecode_vtx_build(bc, vtx, addr);
1908
LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1909
r = r600_bytecode_tex_build(bc, tex, addr);
1919
void r600_bytecode_clear(struct r600_bytecode *bc)
1921
struct r600_bytecode_cf *cf = NULL, *next_cf;
1924
bc->bytecode = NULL;
1926
LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1927
struct r600_bytecode_alu *alu = NULL, *next_alu;
1928
struct r600_bytecode_tex *tex = NULL, *next_tex;
1929
struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1930
struct r600_bytecode_gds *gds = NULL, *next_gds;
1932
LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1936
list_inithead(&cf->alu);
1938
LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1942
list_inithead(&cf->tex);
1944
LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1948
list_inithead(&cf->vtx);
1950
LIST_FOR_EACH_ENTRY_SAFE(gds, next_gds, &cf->gds, list) {
1954
list_inithead(&cf->gds);
1959
list_inithead(&cf->list);
1962
static int print_swizzle(unsigned swz)
1964
const char * swzchars = "xyzw01?_";
1965
assert(swz<8 && swz != 6);
1966
return fprintf(stderr, "%c", swzchars[swz]);
1969
static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1970
unsigned need_brackets)
1973
if (rel && index_mode >= 5 && sel < 128)
1974
o += fprintf(stderr, "G");
1975
if (rel || need_brackets) {
1976
o += fprintf(stderr, "[");
1978
o += fprintf(stderr, "%d", sel);
1980
if (index_mode == 0 || index_mode == 6)
1981
o += fprintf(stderr, "+AR");
1982
else if (index_mode == 4)
1983
o += fprintf(stderr, "+AL");
1985
if (rel || need_brackets) {
1986
o += fprintf(stderr, "]");
1991
static int print_dst(struct r600_bytecode_alu *alu)
1994
unsigned sel = alu->dst.sel;
1995
char reg_char = 'R';
1996
if (sel > 128 - 4) { /* clause temporary gpr */
2001
if (alu_writes(alu)) {
2002
o += fprintf(stderr, "%c", reg_char);
2003
o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
2005
o += fprintf(stderr, "__");
2007
o += fprintf(stderr, ".");
2008
o += print_swizzle(alu->dst.chan);
2012
static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
2015
struct r600_bytecode_alu_src *src = &alu->src[idx];
2016
unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
2019
o += fprintf(stderr,"-");
2021
o += fprintf(stderr,"|");
2023
if (sel < 128 - 4) {
2024
o += fprintf(stderr, "R");
2025
} else if (sel < 128) {
2026
o += fprintf(stderr, "T");
2028
} else if (sel < 160) {
2029
o += fprintf(stderr, "KC0");
2032
} else if (sel < 192) {
2033
o += fprintf(stderr, "KC1");
2036
} else if (sel >= 512) {
2037
o += fprintf(stderr, "C%d", src->kc_bank);
2040
} else if (sel >= 448) {
2041
o += fprintf(stderr, "Param");
2044
} else if (sel >= 288) {
2045
o += fprintf(stderr, "KC3");
2048
} else if (sel >= 256) {
2049
o += fprintf(stderr, "KC2");
2056
case EG_V_SQ_ALU_SRC_LDS_DIRECT_A:
2057
o += fprintf(stderr, "LDS_A[0x%08X]", src->value);
2059
case EG_V_SQ_ALU_SRC_LDS_DIRECT_B:
2060
o += fprintf(stderr, "LDS_B[0x%08X]", src->value);
2062
case EG_V_SQ_ALU_SRC_LDS_OQ_A:
2063
o += fprintf(stderr, "LDS_OQ_A");
2066
case EG_V_SQ_ALU_SRC_LDS_OQ_B:
2067
o += fprintf(stderr, "LDS_OQ_B");
2070
case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP:
2071
o += fprintf(stderr, "LDS_OQ_A_POP");
2074
case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP:
2075
o += fprintf(stderr, "LDS_OQ_B_POP");
2078
case EG_V_SQ_ALU_SRC_TIME_LO:
2079
o += fprintf(stderr, "TIME_LO");
2081
case EG_V_SQ_ALU_SRC_TIME_HI:
2082
o += fprintf(stderr, "TIME_HI");
2084
case EG_V_SQ_ALU_SRC_SE_ID:
2085
o += fprintf(stderr, "SE_ID");
2087
case EG_V_SQ_ALU_SRC_SIMD_ID:
2088
o += fprintf(stderr, "SIMD_ID");
2090
case EG_V_SQ_ALU_SRC_HW_WAVE_ID:
2091
o += fprintf(stderr, "HW_WAVE_ID");
2093
case V_SQ_ALU_SRC_PS:
2094
o += fprintf(stderr, "PS");
2096
case V_SQ_ALU_SRC_PV:
2097
o += fprintf(stderr, "PV");
2100
case V_SQ_ALU_SRC_LITERAL:
2101
o += fprintf(stderr, "[0x%08X %f]", src->value, u_bitcast_u2f(src->value));
2103
case V_SQ_ALU_SRC_0_5:
2104
o += fprintf(stderr, "0.5");
2106
case V_SQ_ALU_SRC_M_1_INT:
2107
o += fprintf(stderr, "-1");
2109
case V_SQ_ALU_SRC_1_INT:
2110
o += fprintf(stderr, "1");
2112
case V_SQ_ALU_SRC_1:
2113
o += fprintf(stderr, "1.0");
2115
case V_SQ_ALU_SRC_0:
2116
o += fprintf(stderr, "0");
2119
o += fprintf(stderr, "??IMM_%d", sel);
2125
o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
2128
o += fprintf(stderr, ".");
2129
o += print_swizzle(src->chan);
2133
o += fprintf(stderr,"|");
2138
static int print_indent(int p, int c)
2142
o += fprintf(stderr, " ");
2146
void r600_bytecode_disasm(struct r600_bytecode *bc)
2148
const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
2149
static int index = 0;
2150
struct r600_bytecode_cf *cf = NULL;
2151
struct r600_bytecode_alu *alu = NULL;
2152
struct r600_bytecode_vtx *vtx = NULL;
2153
struct r600_bytecode_tex *tex = NULL;
2154
struct r600_bytecode_gds *gds = NULL;
2156
unsigned i, id, ngr = 0, last;
2157
uint32_t literal[4];
2161
switch (bc->chip_class) {
2176
fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2177
bc->ndw, bc->ngpr, bc->nstack);
2178
fprintf(stderr, "shader %d -- %c\n", index++, chip);
2180
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2182
if (cf->op == CF_NATIVE) {
2183
fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
2184
bc->bytecode[id + 1]);
2186
const struct cf_op_info *cfop = r600_isa_cf(cf->op);
2187
if (cfop->flags & CF_ALU) {
2188
if (cf->eg_alu_extended) {
2189
fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
2190
bc->bytecode[id + 1], "ALU_EXT");
2193
fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2194
bc->bytecode[id + 1], cfop->name);
2195
fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
2196
for (i = 0; i < 4; ++i) {
2197
if (cf->kcache[i].mode) {
2198
int c_start = (cf->kcache[i].addr << 4);
2199
int c_end = c_start + (cf->kcache[i].mode << 4);
2200
fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
2201
i, cf->kcache[i].bank, c_start, c_end,
2202
cf->kcache[i].index_mode ? " " : "",
2203
cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
2206
fprintf(stderr, "\n");
2207
} else if (cfop->flags & CF_FETCH) {
2208
fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2209
bc->bytecode[id + 1], cfop->name);
2210
fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
2212
fprintf(stderr, "VPM ");
2213
if (cf->end_of_program)
2214
fprintf(stderr, "EOP ");
2215
fprintf(stderr, "\n");
2217
} else if (cfop->flags & CF_EXP) {
2219
const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
2220
o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2221
bc->bytecode[id + 1], cfop->name);
2222
o += print_indent(o, 43);
2223
o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2224
if (cf->output.burst_count > 1) {
2225
o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2226
cf->output.array_base + cf->output.burst_count - 1);
2228
o += print_indent(o, 55);
2229
o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2230
cf->output.gpr + cf->output.burst_count - 1);
2232
o += fprintf(stderr, "%d ", cf->output.array_base);
2233
o += print_indent(o, 55);
2234
o += fprintf(stderr, "R%d.", cf->output.gpr);
2237
o += print_swizzle(cf->output.swizzle_x);
2238
o += print_swizzle(cf->output.swizzle_y);
2239
o += print_swizzle(cf->output.swizzle_z);
2240
o += print_swizzle(cf->output.swizzle_w);
2242
print_indent(o, 67);
2244
fprintf(stderr, " ES:%X ", cf->output.elem_size);
2246
fprintf(stderr, "MARK ");
2248
fprintf(stderr, "NO_BARRIER ");
2249
if (cf->end_of_program)
2250
fprintf(stderr, "EOP ");
2251
fprintf(stderr, "\n");
2252
} else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
2254
const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2256
o += fprintf(stderr, "%04d %08X %08X %s ", id,
2257
bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
2258
o += print_indent(o, 43);
2259
o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2261
if (r600_isa_cf(cf->op)->flags & CF_RAT) {
2262
o += fprintf(stderr, "RAT%d", cf->rat.id);
2263
if (cf->rat.index_mode) {
2264
o += fprintf(stderr, "[IDX%d]", cf->rat.index_mode - 1);
2266
o += fprintf(stderr, " INST: %d ", cf->rat.inst);
2269
if (cf->output.burst_count > 1) {
2270
o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2271
cf->output.array_base + cf->output.burst_count - 1);
2272
o += print_indent(o, 55);
2273
o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2274
cf->output.gpr + cf->output.burst_count - 1);
2276
o += fprintf(stderr, "%d ", cf->output.array_base);
2277
o += print_indent(o, 55);
2278
o += fprintf(stderr, "R%d.", cf->output.gpr);
2280
for (i = 0; i < 4; ++i) {
2281
if (cf->output.comp_mask & (1 << i))
2282
o += print_swizzle(i);
2284
o += print_swizzle(7);
2287
if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND ||
2288
cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND)
2289
o += fprintf(stderr, " R%d", cf->output.index_gpr);
2291
o += print_indent(o, 67);
2293
fprintf(stderr, " ES:%i ", cf->output.elem_size);
2294
if (cf->output.array_size != 0xFFF)
2295
fprintf(stderr, "AS:%i ", cf->output.array_size);
2297
fprintf(stderr, "MARK ");
2299
fprintf(stderr, "NO_BARRIER ");
2300
if (cf->end_of_program)
2301
fprintf(stderr, "EOP ");
2303
if (cf->output.mark)
2304
fprintf(stderr, "MARK ");
2306
fprintf(stderr, "\n");
2308
fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2309
bc->bytecode[id + 1], cfop->name);
2310
fprintf(stderr, "@%d ", cf->cf_addr);
2312
fprintf(stderr, "CND:%X ", cf->cond);
2314
fprintf(stderr, "POP:%X ", cf->pop_count);
2315
if (cf->count && (cfop->flags & CF_EMIT))
2316
fprintf(stderr, "STREAM%d ", cf->count);
2318
fprintf(stderr, "VPM ");
2319
if (cf->end_of_program)
2320
fprintf(stderr, "EOP ");
2321
fprintf(stderr, "\n");
2328
LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2329
const char *omod_str[] = {"","*2","*4","/2"};
2330
const struct alu_op_info *aop = r600_isa_alu(alu->op);
2333
r600_bytecode_alu_nliterals(alu, literal, &nliteral);
2334
o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2336
o += fprintf(stderr, "%4d ", ++ngr);
2338
o += fprintf(stderr, " ");
2339
o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2340
alu->update_pred ? 'P':' ',
2341
alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2343
o += fprintf(stderr, "%s%s%s ", aop->name,
2344
omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2346
o += print_indent(o,60);
2347
o += print_dst(alu);
2348
for (i = 0; i < aop->src_count; ++i) {
2349
o += fprintf(stderr, i == 0 ? ", ": ", ");
2350
o += print_src(alu, i);
2353
if (alu->bank_swizzle) {
2354
o += print_indent(o,75);
2355
o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2358
fprintf(stderr, "\n");
2362
for (i = 0; i < nliteral; i++, id++) {
2363
float *f = (float*)(bc->bytecode + id);
2364
o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2365
print_indent(o, 60);
2366
fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2374
LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2376
o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2377
bc->bytecode[id + 1], bc->bytecode[id + 2]);
2379
o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2381
o += print_indent(o, 50);
2383
o += fprintf(stderr, "R%d.", tex->dst_gpr);
2384
o += print_swizzle(tex->dst_sel_x);
2385
o += print_swizzle(tex->dst_sel_y);
2386
o += print_swizzle(tex->dst_sel_z);
2387
o += print_swizzle(tex->dst_sel_w);
2389
o += fprintf(stderr, ", R%d.", tex->src_gpr);
2390
o += print_swizzle(tex->src_sel_x);
2391
o += print_swizzle(tex->src_sel_y);
2392
o += print_swizzle(tex->src_sel_z);
2393
o += print_swizzle(tex->src_sel_w);
2395
o += fprintf(stderr, ", RID:%d", tex->resource_id);
2396
o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2398
if (tex->sampler_index_mode)
2399
fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2402
fprintf(stderr, "LB:%d ", tex->lod_bias);
2404
fprintf(stderr, "CT:%c%c%c%c ",
2405
tex->coord_type_x ? 'N' : 'U',
2406
tex->coord_type_y ? 'N' : 'U',
2407
tex->coord_type_z ? 'N' : 'U',
2408
tex->coord_type_w ? 'N' : 'U');
2411
fprintf(stderr, "OX:%d ", tex->offset_x);
2413
fprintf(stderr, "OY:%d ", tex->offset_y);
2415
fprintf(stderr, "OZ:%d ", tex->offset_z);
2418
fprintf(stderr, "\n");
2421
LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2423
const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2424
o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2425
bc->bytecode[id + 1], bc->bytecode[id + 2]);
2427
o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2429
o += print_indent(o, 50);
2431
o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2432
o += print_swizzle(vtx->dst_sel_x);
2433
o += print_swizzle(vtx->dst_sel_y);
2434
o += print_swizzle(vtx->dst_sel_z);
2435
o += print_swizzle(vtx->dst_sel_w);
2437
o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2438
o += print_swizzle(vtx->src_sel_x);
2439
if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
2440
o += print_swizzle(vtx->src_sel_y);
2443
fprintf(stderr, " +%db", vtx->offset);
2445
o += print_indent(o, 55);
2447
fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2449
fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2451
if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2452
fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2454
if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2455
fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2457
if (r600_isa_fetch(vtx->op)->flags & FF_MEM) {
2459
fprintf(stderr, "UNCACHED ");
2461
fprintf(stderr, "INDEXED:%d ", vtx->indexed);
2463
fprintf(stderr, "ELEM_SIZE:%d ", vtx->elem_size);
2464
if (vtx->burst_count)
2465
fprintf(stderr, "BURST_COUNT:%d ", vtx->burst_count);
2466
fprintf(stderr, "ARRAY_BASE:%d ", vtx->array_base);
2467
fprintf(stderr, "ARRAY_SIZE:%d ", vtx->array_size);
2470
fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2471
fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2472
fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2473
fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2474
fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2479
LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
2481
o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2482
bc->bytecode[id + 1], bc->bytecode[id + 2]);
2484
o += fprintf(stderr, "%s ", r600_isa_fetch(gds->op)->name);
2486
if (gds->op != FETCH_OP_TF_WRITE) {
2487
o += fprintf(stderr, "R%d.", gds->dst_gpr);
2488
o += print_swizzle(gds->dst_sel_x);
2489
o += print_swizzle(gds->dst_sel_y);
2490
o += print_swizzle(gds->dst_sel_z);
2491
o += print_swizzle(gds->dst_sel_w);
2494
o += fprintf(stderr, ", R%d.", gds->src_gpr);
2495
o += print_swizzle(gds->src_sel_x);
2496
o += print_swizzle(gds->src_sel_y);
2497
o += print_swizzle(gds->src_sel_z);
2499
if (gds->op != FETCH_OP_TF_WRITE) {
2500
o += fprintf(stderr, ", R%d.", gds->src_gpr2);
2502
if (gds->alloc_consume) {
2503
o += fprintf(stderr, " UAV: %d", gds->uav_id);
2504
if (gds->uav_index_mode)
2505
o += fprintf(stderr, "[%s]", index_mode[gds->uav_index_mode]);
2507
fprintf(stderr, "\n");
2512
fprintf(stderr, "--------------------------------------\n");
2515
void r600_vertex_data_type(enum pipe_format pformat,
2517
unsigned *num_format, unsigned *format_comp, unsigned *endian)
2519
const struct util_format_description *desc;
2525
*endian = ENDIAN_NONE;
2527
if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2528
*format = FMT_10_11_11_FLOAT;
2529
*endian = r600_endian_swap(32);
2533
if (pformat == PIPE_FORMAT_B5G6R5_UNORM) {
2534
*format = FMT_5_6_5;
2535
*endian = r600_endian_swap(16);
2539
if (pformat == PIPE_FORMAT_B5G5R5A1_UNORM) {
2540
*format = FMT_1_5_5_5;
2541
*endian = r600_endian_swap(16);
2545
if (pformat == PIPE_FORMAT_A1B5G5R5_UNORM) {
2546
*format = FMT_5_5_5_1;
2550
desc = util_format_description(pformat);
2551
if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2555
/* Find the first non-VOID channel. */
2556
for (i = 0; i < 4; i++) {
2557
if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2562
*endian = r600_endian_swap(desc->channel[i].size);
2564
switch (desc->channel[i].type) {
2565
/* Half-floats, floats, ints */
2566
case UTIL_FORMAT_TYPE_FLOAT:
2567
switch (desc->channel[i].size) {
2569
switch (desc->nr_channels) {
2571
*format = FMT_16_FLOAT;
2574
*format = FMT_16_16_FLOAT;
2578
*format = FMT_16_16_16_16_FLOAT;
2583
switch (desc->nr_channels) {
2585
*format = FMT_32_FLOAT;
2588
*format = FMT_32_32_FLOAT;
2591
*format = FMT_32_32_32_FLOAT;
2594
*format = FMT_32_32_32_32_FLOAT;
2603
case UTIL_FORMAT_TYPE_UNSIGNED:
2605
case UTIL_FORMAT_TYPE_SIGNED:
2606
switch (desc->channel[i].size) {
2608
switch (desc->nr_channels) {
2613
*format = FMT_4_4_4_4;
2618
switch (desc->nr_channels) {
2627
*format = FMT_8_8_8_8;
2632
if (desc->nr_channels != 4)
2635
*format = FMT_2_10_10_10;
2638
switch (desc->nr_channels) {
2643
*format = FMT_16_16;
2647
*format = FMT_16_16_16_16;
2652
switch (desc->nr_channels) {
2657
*format = FMT_32_32;
2660
*format = FMT_32_32_32;
2663
*format = FMT_32_32_32_32;
2675
if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2680
if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2681
desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2682
if (!desc->channel[i].normalized) {
2683
if (desc->channel[i].pure_integer)
2691
R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2694
void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2696
const struct pipe_vertex_element *elements)
2698
struct r600_context *rctx = (struct r600_context *)ctx;
2699
struct r600_bytecode bc;
2700
struct r600_bytecode_vtx vtx;
2701
const struct util_format_description *desc;
2702
unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2703
unsigned format, num_format, format_comp, endian;
2705
int i, j, r, fs_size;
2706
struct r600_fetch_shader *shader;
2707
unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB ||
2708
(rctx->screen->b.debug_flags & DBG_NIR);
2709
unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2713
memset(&bc, 0, sizeof(bc));
2714
r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2715
rctx->screen->has_compressed_msaa_texturing);
2719
for (i = 0; i < count; i++) {
2720
if (elements[i].instance_divisor > 1) {
2721
if (rctx->b.chip_class == CAYMAN) {
2722
for (j = 0; j < 4; j++) {
2723
struct r600_bytecode_alu alu;
2724
memset(&alu, 0, sizeof(alu));
2725
alu.op = ALU_OP2_MULHI_UINT;
2727
alu.src[0].chan = 3;
2728
alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2729
alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2730
alu.dst.sel = i + 1;
2732
alu.dst.write = j == 3;
2734
if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2735
r600_bytecode_clear(&bc);
2740
struct r600_bytecode_alu alu;
2741
memset(&alu, 0, sizeof(alu));
2742
alu.op = ALU_OP2_MULHI_UINT;
2744
alu.src[0].chan = 3;
2745
alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2746
alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2747
alu.dst.sel = i + 1;
2751
if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2752
r600_bytecode_clear(&bc);
2759
for (i = 0; i < count; i++) {
2760
r600_vertex_data_type(elements[i].src_format,
2761
&format, &num_format, &format_comp, &endian);
2763
desc = util_format_description(elements[i].src_format);
2765
r600_bytecode_clear(&bc);
2766
R600_ERR("unknown format %d\n", elements[i].src_format);
2770
if (elements[i].src_offset > 65535) {
2771
r600_bytecode_clear(&bc);
2772
R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2776
memset(&vtx, 0, sizeof(vtx));
2777
vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2778
vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2779
vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2780
vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2781
vtx.mega_fetch_count = 0x1F;
2782
vtx.dst_gpr = i + 1;
2783
vtx.dst_sel_x = desc->swizzle[0];
2784
vtx.dst_sel_y = desc->swizzle[1];
2785
vtx.dst_sel_z = desc->swizzle[2];
2786
vtx.dst_sel_w = desc->swizzle[3];
2787
vtx.data_format = format;
2788
vtx.num_format_all = num_format;
2789
vtx.format_comp_all = format_comp;
2790
vtx.offset = elements[i].src_offset;
2791
vtx.endian = endian;
2793
if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2794
r600_bytecode_clear(&bc);
2799
r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2801
if ((r = r600_bytecode_build(&bc))) {
2802
r600_bytecode_clear(&bc);
2806
if (rctx->screen->b.debug_flags & DBG_FS) {
2807
fprintf(stderr, "--------------------------------------------------------------\n");
2808
fprintf(stderr, "Vertex elements state:\n");
2809
for (i = 0; i < count; i++) {
2810
fprintf(stderr, " ");
2811
util_dump_vertex_element(stderr, elements+i);
2812
fprintf(stderr, "\n");
2816
r600_bytecode_disasm(&bc);
2818
fprintf(stderr, "______________________________________________________________\n");
2820
r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2826
/* Allocate the CSO. */
2827
shader = CALLOC_STRUCT(r600_fetch_shader);
2829
r600_bytecode_clear(&bc);
2833
u_suballocator_alloc(&rctx->allocator_fetch_shader, fs_size, 256,
2835
(struct pipe_resource**)&shader->buffer);
2836
if (!shader->buffer) {
2837
r600_bytecode_clear(&bc);
2842
bytecode = r600_buffer_map_sync_with_rings
2843
(&rctx->b, shader->buffer,
2844
PIPE_MAP_WRITE | PIPE_MAP_UNSYNCHRONIZED | RADEON_MAP_TEMPORARY);
2845
bytecode += shader->offset / 4;
2847
if (R600_BIG_ENDIAN) {
2848
for (i = 0; i < fs_size / 4; ++i) {
2849
bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2852
memcpy(bytecode, bc.bytecode, fs_size);
2854
rctx->b.ws->buffer_unmap(rctx->b.ws, shader->buffer->buf);
2856
r600_bytecode_clear(&bc);
2860
void r600_bytecode_alu_read(struct r600_bytecode *bc,
2861
struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2864
alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2865
alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2866
alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2867
alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2868
alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2869
alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2870
alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2871
alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2872
alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2873
alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2874
alu->last = G_SQ_ALU_WORD0_LAST(word0);
2877
alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2878
if (alu->bank_swizzle)
2879
alu->bank_swizzle_force = alu->bank_swizzle;
2880
alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2881
alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2882
alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2883
alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2884
if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2887
alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2888
alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2889
alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2890
alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2891
alu->op = r600_isa_alu_by_opcode(bc->isa,
2892
G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2895
else /*ALU_DWORD1_OP2*/
2897
alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2898
alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2899
alu->op = r600_isa_alu_by_opcode(bc->isa,
2900
G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2901
alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2902
alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2903
alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2905
G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2910
void r600_bytecode_export_read(struct r600_bytecode *bc,
2911
struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2913
output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2914
output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2915
output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2916
output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2918
output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2919
output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2920
output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2921
output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2922
output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2923
output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2924
output->op = r600_isa_cf_by_opcode(bc->isa,
2925
G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2926
output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2927
output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2928
output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
added
removed
src/gallium/drivers/r600/r600_asm.c
