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Viewing changes to src/amd/vulkan/radv_perfcounter.c

  • Committer: mmach
  • Date: 2022-09-22 19:56:13 UTC
  • Revision ID: netbit73@gmail.com-20220922195613-wtik9mmy20tmor0i
2022-09-22 21:17:09

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src/amd/vulkan/radv_perfcounter.c
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/*
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 * Copyright © 2021 Valve Corporation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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 * IN THE SOFTWARE.
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 */
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#include <inttypes.h>
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#include "radv_cs.h"
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#include "radv_private.h"
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#include "sid.h"
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void
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radv_perfcounter_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders)
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{
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   radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2);
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   radeon_emit(cs, shaders & 0x7f);
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   radeon_emit(cs, 0xffffffff);
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}
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void
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radv_perfcounter_emit_reset(struct radeon_cmdbuf *cs)
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{
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   radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
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                              S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET) |
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                              S_036020_SPM_PERFMON_STATE(V_036020_STRM_PERFMON_STATE_DISABLE_AND_RESET));
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}
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void
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radv_perfcounter_emit_start(struct radv_device *device, struct radeon_cmdbuf *cs, int family)
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{
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   /* Start SPM counters. */
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   radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
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                              S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET) |
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                              S_036020_SPM_PERFMON_STATE(V_036020_STRM_PERFMON_STATE_START_COUNTING));
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   /* Start windowed performance counters. */
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   if (family == RADV_QUEUE_GENERAL) {
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      radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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      radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_START) | EVENT_INDEX(0));
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   }
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   radeon_set_sh_reg(cs, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, S_00B82C_PERFCOUNT_ENABLE(1));
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}
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void
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radv_perfcounter_emit_stop(struct radv_device *device, struct radeon_cmdbuf *cs, int family)
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{
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   /* Stop windowed performance counters. */
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   if (family == RADV_QUEUE_GENERAL) {
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      radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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      radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0));
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   }
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   radeon_set_sh_reg(cs, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, S_00B82C_PERFCOUNT_ENABLE(0));
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   /* Stop SPM counters. */
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   radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
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                              S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET) |
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                              S_036020_SPM_PERFMON_STATE(device->physical_device->rad_info.never_stop_sq_perf_counters ?
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                                                            V_036020_STRM_PERFMON_STATE_START_COUNTING :
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                                                            V_036020_STRM_PERFMON_STATE_STOP_COUNTING));
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}