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* Copyright © 2021 Google
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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#ifndef RADV_RT_COMMON_H
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#define RADV_RT_COMMON_H
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#include "nir/nir_builder.h"
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#include "nir/nir_vulkan.h"
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#include "compiler/spirv/spirv.h"
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#include "radv_private.h"
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void nir_sort_hit_pair(nir_builder *b, nir_variable *var_distances, nir_variable *var_indices,
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uint32_t chan_1, uint32_t chan_2);
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nir_ssa_def *intersect_ray_amd_software_box(struct radv_device *device, nir_builder *b,
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nir_ssa_def *bvh_node, nir_ssa_def *ray_tmax,
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nir_ssa_def *origin, nir_ssa_def *dir,
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nir_ssa_def *inv_dir);
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nir_ssa_def *intersect_ray_amd_software_tri(struct radv_device *device, nir_builder *b,
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nir_ssa_def *bvh_node, nir_ssa_def *ray_tmax,
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nir_ssa_def *origin, nir_ssa_def *dir,
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nir_ssa_def *inv_dir);
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nir_ssa_def *build_addr_to_node(nir_builder *b, nir_ssa_def *addr);
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nir_ssa_def *build_node_to_addr(struct radv_device *device, nir_builder *b, nir_ssa_def *node);
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nir_ssa_def *nir_build_vec3_mat_mult(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *matrix[],
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nir_ssa_def *nir_build_vec3_mat_mult_pre(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *matrix[]);
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void nir_build_wto_matrix_load(nir_builder *b, nir_ssa_def *instance_addr, nir_ssa_def **out);
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nir_ssa_def *hit_is_opaque(nir_builder *b, nir_ssa_def *sbt_offset_and_flags, nir_ssa_def *flags,
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nir_ssa_def *geometry_id_and_flags);
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nir_ssa_def *create_bvh_descriptor(nir_builder *b);
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* A top-level AS can contain 2^24 children and a bottom-level AS can contain 2^24
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* triangles. At a branching factor of 4, that means we may need up to 24 levels of box
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* nodes + 1 triangle node
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* + 1 instance node. Furthermore, when processing a box node, worst case we actually
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* push all 4 children and remove one, so the DFS stack depth is box nodes * 3 + 2.
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#define MAX_STACK_ENTRY_COUNT 76