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* Copyright (C) 2019 Rob Clark <robclark@freedesktop.org>
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* Rob Clark <robclark@freedesktop.org>
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#ifndef FD6_PERFCNTR_H_
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#define FD6_PERFCNTR_H_
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#include "util/half_float.h"
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#include "util/u_math.h"
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#include "adreno_common.xml.h"
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#include "adreno_pm4.xml.h"
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#define REG(_x) REG_A6XX_ ## _x
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#include "freedreno_perfcntr.h"
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static const struct fd_perfcntr_counter cp_counters[] = {
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//RESERVED: for kernel
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// COUNTER(CP_PERFCTR_CP_SEL(0), RBBM_PERFCTR_CP(0), RBBM_PERFCTR_CP(0)+1),
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COUNTER(CP_PERFCTR_CP_SEL(1), RBBM_PERFCTR_CP(1), RBBM_PERFCTR_CP(1)+1),
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COUNTER(CP_PERFCTR_CP_SEL(2), RBBM_PERFCTR_CP(2), RBBM_PERFCTR_CP(2)+1),
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COUNTER(CP_PERFCTR_CP_SEL(3), RBBM_PERFCTR_CP(3), RBBM_PERFCTR_CP(3)+1),
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COUNTER(CP_PERFCTR_CP_SEL(4), RBBM_PERFCTR_CP(4), RBBM_PERFCTR_CP(4)+1),
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COUNTER(CP_PERFCTR_CP_SEL(5), RBBM_PERFCTR_CP(5), RBBM_PERFCTR_CP(5)+1),
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COUNTER(CP_PERFCTR_CP_SEL(6), RBBM_PERFCTR_CP(6), RBBM_PERFCTR_CP(6)+1),
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COUNTER(CP_PERFCTR_CP_SEL(7), RBBM_PERFCTR_CP(7), RBBM_PERFCTR_CP(7)+1),
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COUNTER(CP_PERFCTR_CP_SEL(8), RBBM_PERFCTR_CP(8), RBBM_PERFCTR_CP(8)+1),
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COUNTER(CP_PERFCTR_CP_SEL(9), RBBM_PERFCTR_CP(9), RBBM_PERFCTR_CP(9)+1),
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COUNTER(CP_PERFCTR_CP_SEL(10), RBBM_PERFCTR_CP(10), RBBM_PERFCTR_CP(10)+1),
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COUNTER(CP_PERFCTR_CP_SEL(11), RBBM_PERFCTR_CP(11), RBBM_PERFCTR_CP(11)+1),
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COUNTER(CP_PERFCTR_CP_SEL(12), RBBM_PERFCTR_CP(12), RBBM_PERFCTR_CP(12)+1),
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COUNTER(CP_PERFCTR_CP_SEL(13), RBBM_PERFCTR_CP(13), RBBM_PERFCTR_CP(13)+1),
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static const struct fd_perfcntr_countable cp_countables[] = {
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COUNTABLE(PERF_CP_ALWAYS_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_BUSY_GFX_CORE_IDLE, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_BUSY_CYCLES, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_NUM_PREEMPTIONS, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_PREEMPTION_REACTION_DELAY, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_PREEMPTION_SWITCH_OUT_TIME, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_PREEMPTION_SWITCH_IN_TIME, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_DEAD_DRAWS_IN_BIN_RENDER, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_PREDICATED_DRAWS_KILLED, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_MODE_SWITCH, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_ZPASS_DONE, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_CONTEXT_DONE, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_CACHE_FLUSH, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_LONG_PREEMPTIONS, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_I_CACHE_STARVE, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_IDLE, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_PM4_STARVE_RB_IB, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_PM4_STARVE_SDS, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_MRB_STARVE, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_RRB_STARVE, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_VSD_STARVE, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_VSD_DECODE_STARVE, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_PIPE_OUT_STALL, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_SYNC_STALL, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_PM4_WFI_STALL, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_SYS_WFI_STALL, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_T4_EXEC, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_LOAD_STATE_EXEC, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_SAVE_SDS_STATE, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_DRAW_EXEC, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_CTXT_REG_BUNCH_EXEC, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_EXEC_PROFILED, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_MEMORY_POOL_EMPTY, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_MEMORY_POOL_SYNC_STALL, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_MEMORY_POOL_ABOVE_THRESH, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_AHB_WR_STALL_PRE_DRAWS, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_AHB_STALL_SQE_GMU, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_AHB_STALL_SQE_WR_OTHER, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_AHB_STALL_SQE_RD_OTHER, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_CLUSTER0_EMPTY, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_CLUSTER1_EMPTY, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_CLUSTER2_EMPTY, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_CLUSTER3_EMPTY, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_CLUSTER4_EMPTY, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_CLUSTER5_EMPTY, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_PM4_DATA, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_PM4_HEADERS, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_VBIF_READ_BEATS, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_VBIF_WRITE_BEATS, UINT64, AVERAGE),
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COUNTABLE(PERF_CP_SQE_INSTR_COUNTER, UINT64, AVERAGE),
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static const struct fd_perfcntr_counter ccu_counters[] = {
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COUNTER(RB_PERFCTR_CCU_SEL(0), RBBM_PERFCTR_CCU(0), RBBM_PERFCTR_CCU(0)+1),
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COUNTER(RB_PERFCTR_CCU_SEL(1), RBBM_PERFCTR_CCU(1), RBBM_PERFCTR_CCU(1)+1),
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COUNTER(RB_PERFCTR_CCU_SEL(2), RBBM_PERFCTR_CCU(2), RBBM_PERFCTR_CCU(2)+1),
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COUNTER(RB_PERFCTR_CCU_SEL(3), RBBM_PERFCTR_CCU(3), RBBM_PERFCTR_CCU(3)+1),
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COUNTER(RB_PERFCTR_CCU_SEL(4), RBBM_PERFCTR_CCU(4), RBBM_PERFCTR_CCU(4)+1),
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static const struct fd_perfcntr_countable ccu_countables[] = {
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COUNTABLE(PERF_CCU_BUSY_CYCLES, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_STARVE_CYCLES_FLAG_RETURN, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_DEPTH_BLOCKS, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_COLOR_BLOCKS, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_DEPTH_BLOCK_HIT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_COLOR_BLOCK_HIT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_PARTIAL_BLOCK_READ, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_GMEM_READ, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_GMEM_WRITE, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_DEPTH_READ_FLAG0_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_DEPTH_READ_FLAG1_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_DEPTH_READ_FLAG2_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_DEPTH_READ_FLAG3_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_DEPTH_READ_FLAG4_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_DEPTH_READ_FLAG5_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_DEPTH_READ_FLAG6_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_DEPTH_READ_FLAG8_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_COLOR_READ_FLAG0_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_COLOR_READ_FLAG1_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_COLOR_READ_FLAG2_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_COLOR_READ_FLAG3_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_COLOR_READ_FLAG4_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_COLOR_READ_FLAG5_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_COLOR_READ_FLAG6_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_COLOR_READ_FLAG8_COUNT, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_2D_RD_REQ, UINT64, AVERAGE),
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COUNTABLE(PERF_CCU_2D_WR_REQ, UINT64, AVERAGE),
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static const struct fd_perfcntr_counter tse_counters[] = {
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COUNTER(GRAS_PERFCTR_TSE_SEL(0), RBBM_PERFCTR_TSE(0), RBBM_PERFCTR_TSE(0)+1),
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COUNTER(GRAS_PERFCTR_TSE_SEL(1), RBBM_PERFCTR_TSE(1), RBBM_PERFCTR_TSE(1)+1),
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COUNTER(GRAS_PERFCTR_TSE_SEL(2), RBBM_PERFCTR_TSE(2), RBBM_PERFCTR_TSE(2)+1),
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COUNTER(GRAS_PERFCTR_TSE_SEL(3), RBBM_PERFCTR_TSE(3), RBBM_PERFCTR_TSE(3)+1),
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static const struct fd_perfcntr_countable tse_countables[] = {
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COUNTABLE(PERF_TSE_BUSY_CYCLES, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_CLIPPING_CYCLES, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_STALL_CYCLES_RAS, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_ZPLANE, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_STARVE_CYCLES_PC, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_INPUT_PRIM, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_INPUT_NULL_PRIM, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_TRIVAL_REJ_PRIM, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_CLIPPED_PRIM, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_ZERO_AREA_PRIM, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_FACENESS_CULLED_PRIM, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_ZERO_PIXEL_PRIM, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_OUTPUT_NULL_PRIM, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_OUTPUT_VISIBLE_PRIM, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_CINVOCATION, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_CPRIMITIVES, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_2D_INPUT_PRIM, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_2D_ALIVE_CYCLES, UINT64, AVERAGE),
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COUNTABLE(PERF_TSE_CLIP_PLANES, UINT64, AVERAGE),
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static const struct fd_perfcntr_counter ras_counters[] = {
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COUNTER(GRAS_PERFCTR_RAS_SEL(0), RBBM_PERFCTR_RAS(0), RBBM_PERFCTR_RAS(0)+1),
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COUNTER(GRAS_PERFCTR_RAS_SEL(1), RBBM_PERFCTR_RAS(1), RBBM_PERFCTR_RAS(1)+1),
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COUNTER(GRAS_PERFCTR_RAS_SEL(2), RBBM_PERFCTR_RAS(2), RBBM_PERFCTR_RAS(2)+1),
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COUNTER(GRAS_PERFCTR_RAS_SEL(3), RBBM_PERFCTR_RAS(3), RBBM_PERFCTR_RAS(3)+1),
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static const struct fd_perfcntr_countable ras_countables[] = {
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COUNTABLE(PERF_RAS_BUSY_CYCLES, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_SUPERTILE_ACTIVE_CYCLES, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_STALL_CYCLES_LRZ, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_STARVE_CYCLES_TSE, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_SUPER_TILES, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_8X4_TILES, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_MASKGEN_ACTIVE, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_FULLY_COVERED_SUPER_TILES, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_FULLY_COVERED_8X4_TILES, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_PRIM_KILLED_INVISILBE, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_LRZ_INTF_WORKING_CYCLES, UINT64, AVERAGE),
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COUNTABLE(PERF_RAS_BLOCKS, UINT64, AVERAGE),
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static const struct fd_perfcntr_counter lrz_counters[] = {
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COUNTER(GRAS_PERFCTR_LRZ_SEL(0), RBBM_PERFCTR_LRZ(0), RBBM_PERFCTR_LRZ(0)+1),
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COUNTER(GRAS_PERFCTR_LRZ_SEL(1), RBBM_PERFCTR_LRZ(1), RBBM_PERFCTR_LRZ(1)+1),
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COUNTER(GRAS_PERFCTR_LRZ_SEL(2), RBBM_PERFCTR_LRZ(2), RBBM_PERFCTR_LRZ(2)+1),
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COUNTER(GRAS_PERFCTR_LRZ_SEL(3), RBBM_PERFCTR_LRZ(3), RBBM_PERFCTR_LRZ(3)+1),
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static const struct fd_perfcntr_countable lrz_countables[] = {
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COUNTABLE(PERF_LRZ_BUSY_CYCLES, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_STARVE_CYCLES_RAS, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_STALL_CYCLES_RB, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_STALL_CYCLES_VSC, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_STALL_CYCLES_VPC, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_LRZ_READ, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_LRZ_WRITE, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_READ_LATENCY, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_MERGE_CACHE_UPDATING, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_MASKGEN, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_LRZ, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_FULL_8X8_TILES, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_PARTIAL_8X8_TILES, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_TILE_KILLED, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_TOTAL_PIXEL, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_FULLY_COVERED_TILES, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_PARTIAL_COVERED_TILES, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_FEEDBACK_ACCEPT, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_FEEDBACK_DISCARD, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_FEEDBACK_STALL, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_STALL_CYCLES_RB_ZPLANE, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_STALL_CYCLES_RB_BPLANE, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_STALL_CYCLES_VC, UINT64, AVERAGE),
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COUNTABLE(PERF_LRZ_RAS_MASK_TRANS, UINT64, AVERAGE),
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static const struct fd_perfcntr_counter hlsq_counters[] = {
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COUNTER(HLSQ_PERFCTR_HLSQ_SEL(0), RBBM_PERFCTR_HLSQ(0), RBBM_PERFCTR_HLSQ(0)+1),
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COUNTER(HLSQ_PERFCTR_HLSQ_SEL(1), RBBM_PERFCTR_HLSQ(1), RBBM_PERFCTR_HLSQ(1)+1),
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COUNTER(HLSQ_PERFCTR_HLSQ_SEL(2), RBBM_PERFCTR_HLSQ(2), RBBM_PERFCTR_HLSQ(2)+1),
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COUNTER(HLSQ_PERFCTR_HLSQ_SEL(3), RBBM_PERFCTR_HLSQ(3), RBBM_PERFCTR_HLSQ(3)+1),
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COUNTER(HLSQ_PERFCTR_HLSQ_SEL(4), RBBM_PERFCTR_HLSQ(4), RBBM_PERFCTR_HLSQ(4)+1),
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COUNTER(HLSQ_PERFCTR_HLSQ_SEL(5), RBBM_PERFCTR_HLSQ(5), RBBM_PERFCTR_HLSQ(5)+1),
248
// TODO did we loose some HLSQ counters or are they just missing from xml
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// COUNTER(HLSQ_PERFCTR_HLSQ_SEL(6), RBBM_PERFCTR_HLSQ(6), RBBM_PERFCTR_HLSQ(6)+1),
250
// COUNTER(HLSQ_PERFCTR_HLSQ_SEL(7), RBBM_PERFCTR_HLSQ(7), RBBM_PERFCTR_HLSQ(7)+1),
253
static const struct fd_perfcntr_countable hlsq_countables[] = {
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COUNTABLE(PERF_HLSQ_BUSY_CYCLES, UINT64, AVERAGE),
255
COUNTABLE(PERF_HLSQ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
256
COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_STATE, UINT64, AVERAGE),
257
COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE, UINT64, AVERAGE),
258
COUNTABLE(PERF_HLSQ_UCHE_LATENCY_CYCLES, UINT64, AVERAGE),
259
COUNTABLE(PERF_HLSQ_UCHE_LATENCY_COUNT, UINT64, AVERAGE),
260
COUNTABLE(PERF_HLSQ_FS_STAGE_1X_WAVES, UINT64, AVERAGE),
261
COUNTABLE(PERF_HLSQ_FS_STAGE_2X_WAVES, UINT64, AVERAGE),
262
COUNTABLE(PERF_HLSQ_QUADS, UINT64, AVERAGE),
263
COUNTABLE(PERF_HLSQ_CS_INVOCATIONS, UINT64, AVERAGE),
264
COUNTABLE(PERF_HLSQ_COMPUTE_DRAWCALLS, UINT64, AVERAGE),
265
COUNTABLE(PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING, UINT64, AVERAGE),
266
COUNTABLE(PERF_HLSQ_DUAL_FS_PROG_ACTIVE, UINT64, AVERAGE),
267
COUNTABLE(PERF_HLSQ_DUAL_VS_PROG_ACTIVE, UINT64, AVERAGE),
268
COUNTABLE(PERF_HLSQ_FS_BATCH_COUNT_ZERO, UINT64, AVERAGE),
269
COUNTABLE(PERF_HLSQ_VS_BATCH_COUNT_ZERO, UINT64, AVERAGE),
270
COUNTABLE(PERF_HLSQ_WAVE_PENDING_NO_QUAD, UINT64, AVERAGE),
271
COUNTABLE(PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE, UINT64, AVERAGE),
272
COUNTABLE(PERF_HLSQ_STALL_CYCLES_VPC, UINT64, AVERAGE),
273
COUNTABLE(PERF_HLSQ_PIXELS, UINT64, AVERAGE),
274
COUNTABLE(PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC, UINT64, AVERAGE),
277
static const struct fd_perfcntr_counter pc_counters[] = {
278
COUNTER(PC_PERFCTR_PC_SEL(0), RBBM_PERFCTR_PC(0), RBBM_PERFCTR_PC(0)+1),
279
COUNTER(PC_PERFCTR_PC_SEL(1), RBBM_PERFCTR_PC(1), RBBM_PERFCTR_PC(1)+1),
280
COUNTER(PC_PERFCTR_PC_SEL(2), RBBM_PERFCTR_PC(2), RBBM_PERFCTR_PC(2)+1),
281
COUNTER(PC_PERFCTR_PC_SEL(3), RBBM_PERFCTR_PC(3), RBBM_PERFCTR_PC(3)+1),
282
COUNTER(PC_PERFCTR_PC_SEL(4), RBBM_PERFCTR_PC(4), RBBM_PERFCTR_PC(4)+1),
283
COUNTER(PC_PERFCTR_PC_SEL(5), RBBM_PERFCTR_PC(5), RBBM_PERFCTR_PC(5)+1),
284
COUNTER(PC_PERFCTR_PC_SEL(6), RBBM_PERFCTR_PC(6), RBBM_PERFCTR_PC(6)+1),
285
COUNTER(PC_PERFCTR_PC_SEL(7), RBBM_PERFCTR_PC(7), RBBM_PERFCTR_PC(7)+1),
288
static const struct fd_perfcntr_countable pc_countables[] = {
289
COUNTABLE(PERF_PC_BUSY_CYCLES, UINT64, AVERAGE),
290
COUNTABLE(PERF_PC_WORKING_CYCLES, UINT64, AVERAGE),
291
COUNTABLE(PERF_PC_STALL_CYCLES_VFD, UINT64, AVERAGE),
292
COUNTABLE(PERF_PC_STALL_CYCLES_TSE, UINT64, AVERAGE),
293
COUNTABLE(PERF_PC_STALL_CYCLES_VPC, UINT64, AVERAGE),
294
COUNTABLE(PERF_PC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
295
COUNTABLE(PERF_PC_STALL_CYCLES_TESS, UINT64, AVERAGE),
296
COUNTABLE(PERF_PC_STALL_CYCLES_TSE_ONLY, UINT64, AVERAGE),
297
COUNTABLE(PERF_PC_STALL_CYCLES_VPC_ONLY, UINT64, AVERAGE),
298
COUNTABLE(PERF_PC_PASS1_TF_STALL_CYCLES, UINT64, AVERAGE),
299
COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_INDEX, UINT64, AVERAGE),
300
COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR, UINT64, AVERAGE),
301
COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM, UINT64, AVERAGE),
302
COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_POSITION, UINT64, AVERAGE),
303
COUNTABLE(PERF_PC_STARVE_CYCLES_DI, UINT64, AVERAGE),
304
COUNTABLE(PERF_PC_VIS_STREAMS_LOADED, UINT64, AVERAGE),
305
COUNTABLE(PERF_PC_INSTANCES, UINT64, AVERAGE),
306
COUNTABLE(PERF_PC_VPC_PRIMITIVES, UINT64, AVERAGE),
307
COUNTABLE(PERF_PC_DEAD_PRIM, UINT64, AVERAGE),
308
COUNTABLE(PERF_PC_LIVE_PRIM, UINT64, AVERAGE),
309
COUNTABLE(PERF_PC_VERTEX_HITS, UINT64, AVERAGE),
310
COUNTABLE(PERF_PC_IA_VERTICES, UINT64, AVERAGE),
311
COUNTABLE(PERF_PC_IA_PRIMITIVES, UINT64, AVERAGE),
312
COUNTABLE(PERF_PC_GS_PRIMITIVES, UINT64, AVERAGE),
313
COUNTABLE(PERF_PC_HS_INVOCATIONS, UINT64, AVERAGE),
314
COUNTABLE(PERF_PC_DS_INVOCATIONS, UINT64, AVERAGE),
315
COUNTABLE(PERF_PC_VS_INVOCATIONS, UINT64, AVERAGE),
316
COUNTABLE(PERF_PC_GS_INVOCATIONS, UINT64, AVERAGE),
317
COUNTABLE(PERF_PC_DS_PRIMITIVES, UINT64, AVERAGE),
318
COUNTABLE(PERF_PC_VPC_POS_DATA_TRANSACTION, UINT64, AVERAGE),
319
COUNTABLE(PERF_PC_3D_DRAWCALLS, UINT64, AVERAGE),
320
COUNTABLE(PERF_PC_2D_DRAWCALLS, UINT64, AVERAGE),
321
COUNTABLE(PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS, UINT64, AVERAGE),
322
COUNTABLE(PERF_TESS_BUSY_CYCLES, UINT64, AVERAGE),
323
COUNTABLE(PERF_TESS_WORKING_CYCLES, UINT64, AVERAGE),
324
COUNTABLE(PERF_TESS_STALL_CYCLES_PC, UINT64, AVERAGE),
325
COUNTABLE(PERF_TESS_STARVE_CYCLES_PC, UINT64, AVERAGE),
326
COUNTABLE(PERF_PC_TSE_TRANSACTION, UINT64, AVERAGE),
327
COUNTABLE(PERF_PC_TSE_VERTEX, UINT64, AVERAGE),
328
COUNTABLE(PERF_PC_TESS_PC_UV_TRANS, UINT64, AVERAGE),
329
COUNTABLE(PERF_PC_TESS_PC_UV_PATCHES, UINT64, AVERAGE),
330
COUNTABLE(PERF_PC_TESS_FACTOR_TRANS, UINT64, AVERAGE),
333
static const struct fd_perfcntr_counter rb_counters[] = {
334
COUNTER(RB_PERFCTR_RB_SEL(0), RBBM_PERFCTR_RB(0), RBBM_PERFCTR_RB(0)+1),
335
COUNTER(RB_PERFCTR_RB_SEL(1), RBBM_PERFCTR_RB(1), RBBM_PERFCTR_RB(1)+1),
336
COUNTER(RB_PERFCTR_RB_SEL(2), RBBM_PERFCTR_RB(2), RBBM_PERFCTR_RB(2)+1),
337
COUNTER(RB_PERFCTR_RB_SEL(3), RBBM_PERFCTR_RB(3), RBBM_PERFCTR_RB(3)+1),
338
COUNTER(RB_PERFCTR_RB_SEL(4), RBBM_PERFCTR_RB(4), RBBM_PERFCTR_RB(4)+1),
339
COUNTER(RB_PERFCTR_RB_SEL(5), RBBM_PERFCTR_RB(5), RBBM_PERFCTR_RB(5)+1),
340
COUNTER(RB_PERFCTR_RB_SEL(6), RBBM_PERFCTR_RB(6), RBBM_PERFCTR_RB(6)+1),
341
COUNTER(RB_PERFCTR_RB_SEL(7), RBBM_PERFCTR_RB(7), RBBM_PERFCTR_RB(7)+1),
344
static const struct fd_perfcntr_countable rb_countables[] = {
345
COUNTABLE(PERF_RB_BUSY_CYCLES, UINT64, AVERAGE),
346
COUNTABLE(PERF_RB_STALL_CYCLES_HLSQ, UINT64, AVERAGE),
347
COUNTABLE(PERF_RB_STALL_CYCLES_FIFO0_FULL, UINT64, AVERAGE),
348
COUNTABLE(PERF_RB_STALL_CYCLES_FIFO1_FULL, UINT64, AVERAGE),
349
COUNTABLE(PERF_RB_STALL_CYCLES_FIFO2_FULL, UINT64, AVERAGE),
350
COUNTABLE(PERF_RB_STARVE_CYCLES_SP, UINT64, AVERAGE),
351
COUNTABLE(PERF_RB_STARVE_CYCLES_LRZ_TILE, UINT64, AVERAGE),
352
COUNTABLE(PERF_RB_STARVE_CYCLES_CCU, UINT64, AVERAGE),
353
COUNTABLE(PERF_RB_STARVE_CYCLES_Z_PLANE, UINT64, AVERAGE),
354
COUNTABLE(PERF_RB_STARVE_CYCLES_BARY_PLANE, UINT64, AVERAGE),
355
COUNTABLE(PERF_RB_Z_WORKLOAD, UINT64, AVERAGE),
356
COUNTABLE(PERF_RB_HLSQ_ACTIVE, UINT64, AVERAGE),
357
COUNTABLE(PERF_RB_Z_READ, UINT64, AVERAGE),
358
COUNTABLE(PERF_RB_Z_WRITE, UINT64, AVERAGE),
359
COUNTABLE(PERF_RB_C_READ, UINT64, AVERAGE),
360
COUNTABLE(PERF_RB_C_WRITE, UINT64, AVERAGE),
361
COUNTABLE(PERF_RB_TOTAL_PASS, UINT64, AVERAGE),
362
COUNTABLE(PERF_RB_Z_PASS, UINT64, AVERAGE),
363
COUNTABLE(PERF_RB_Z_FAIL, UINT64, AVERAGE),
364
COUNTABLE(PERF_RB_S_FAIL, UINT64, AVERAGE),
365
COUNTABLE(PERF_RB_BLENDED_FXP_COMPONENTS, UINT64, AVERAGE),
366
COUNTABLE(PERF_RB_BLENDED_FP16_COMPONENTS, UINT64, AVERAGE),
367
COUNTABLE(PERF_RB_PS_INVOCATIONS, UINT64, AVERAGE),
368
COUNTABLE(PERF_RB_2D_ALIVE_CYCLES, UINT64, AVERAGE),
369
COUNTABLE(PERF_RB_2D_STALL_CYCLES_A2D, UINT64, AVERAGE),
370
COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SRC, UINT64, AVERAGE),
371
COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SP, UINT64, AVERAGE),
372
COUNTABLE(PERF_RB_2D_STARVE_CYCLES_DST, UINT64, AVERAGE),
373
COUNTABLE(PERF_RB_2D_VALID_PIXELS, UINT64, AVERAGE),
374
COUNTABLE(PERF_RB_3D_PIXELS, UINT64, AVERAGE),
375
COUNTABLE(PERF_RB_BLENDER_WORKING_CYCLES, UINT64, AVERAGE),
376
COUNTABLE(PERF_RB_ZPROC_WORKING_CYCLES, UINT64, AVERAGE),
377
COUNTABLE(PERF_RB_CPROC_WORKING_CYCLES, UINT64, AVERAGE),
378
COUNTABLE(PERF_RB_SAMPLER_WORKING_CYCLES, UINT64, AVERAGE),
379
COUNTABLE(PERF_RB_STALL_CYCLES_CCU_COLOR_READ, UINT64, AVERAGE),
380
COUNTABLE(PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE, UINT64, AVERAGE),
381
COUNTABLE(PERF_RB_STALL_CYCLES_CCU_DEPTH_READ, UINT64, AVERAGE),
382
COUNTABLE(PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE, UINT64, AVERAGE),
383
COUNTABLE(PERF_RB_STALL_CYCLES_VPC, UINT64, AVERAGE),
384
COUNTABLE(PERF_RB_2D_INPUT_TRANS, UINT64, AVERAGE),
385
COUNTABLE(PERF_RB_2D_OUTPUT_RB_DST_TRANS, UINT64, AVERAGE),
386
COUNTABLE(PERF_RB_2D_OUTPUT_RB_SRC_TRANS, UINT64, AVERAGE),
387
COUNTABLE(PERF_RB_BLENDED_FP32_COMPONENTS, UINT64, AVERAGE),
388
COUNTABLE(PERF_RB_COLOR_PIX_TILES, UINT64, AVERAGE),
389
COUNTABLE(PERF_RB_STALL_CYCLES_CCU, UINT64, AVERAGE),
390
COUNTABLE(PERF_RB_EARLY_Z_ARB3_GRANT, UINT64, AVERAGE),
391
COUNTABLE(PERF_RB_LATE_Z_ARB3_GRANT, UINT64, AVERAGE),
392
COUNTABLE(PERF_RB_EARLY_Z_SKIP_GRANT, UINT64, AVERAGE),
395
UNUSED static const struct fd_perfcntr_counter rbbm_counters[] = {
396
//RESERVED: for kernel
397
// COUNTER(RBBM_PERFCTR_RBBM_SEL(0), RBBM_PERFCTR_RBBM(0), RBBM_PERFCTR_RBBM(0)+1),
398
COUNTER(RBBM_PERFCTR_RBBM_SEL(1), RBBM_PERFCTR_RBBM(1), RBBM_PERFCTR_RBBM(1)+1),
399
COUNTER(RBBM_PERFCTR_RBBM_SEL(2), RBBM_PERFCTR_RBBM(2), RBBM_PERFCTR_RBBM(2)+1),
400
COUNTER(RBBM_PERFCTR_RBBM_SEL(3), RBBM_PERFCTR_RBBM(3), RBBM_PERFCTR_RBBM(3)+1),
403
UNUSED static const struct fd_perfcntr_countable rbbm_countables[] = {
404
COUNTABLE(PERF_RBBM_ALWAYS_COUNT, UINT64, AVERAGE),
405
COUNTABLE(PERF_RBBM_ALWAYS_ON, UINT64, AVERAGE),
406
COUNTABLE(PERF_RBBM_TSE_BUSY, UINT64, AVERAGE),
407
COUNTABLE(PERF_RBBM_RAS_BUSY, UINT64, AVERAGE),
408
COUNTABLE(PERF_RBBM_PC_DCALL_BUSY, UINT64, AVERAGE),
409
COUNTABLE(PERF_RBBM_PC_VSD_BUSY, UINT64, AVERAGE),
410
COUNTABLE(PERF_RBBM_STATUS_MASKED, UINT64, AVERAGE),
411
COUNTABLE(PERF_RBBM_COM_BUSY, UINT64, AVERAGE),
412
COUNTABLE(PERF_RBBM_DCOM_BUSY, UINT64, AVERAGE),
413
COUNTABLE(PERF_RBBM_VBIF_BUSY, UINT64, AVERAGE),
414
COUNTABLE(PERF_RBBM_VSC_BUSY, UINT64, AVERAGE),
415
COUNTABLE(PERF_RBBM_TESS_BUSY, UINT64, AVERAGE),
416
COUNTABLE(PERF_RBBM_UCHE_BUSY, UINT64, AVERAGE),
417
COUNTABLE(PERF_RBBM_HLSQ_BUSY, UINT64, AVERAGE),
420
static const struct fd_perfcntr_counter sp_counters[] = {
421
//RESERVED: for kernel
422
// COUNTER(SP_PERFCTR_SP_SEL(0), RBBM_PERFCTR_SP(0), RBBM_PERFCTR_SP(0)+1),
423
COUNTER(SP_PERFCTR_SP_SEL(1), RBBM_PERFCTR_SP(1), RBBM_PERFCTR_SP(1)+1),
424
COUNTER(SP_PERFCTR_SP_SEL(2), RBBM_PERFCTR_SP(2), RBBM_PERFCTR_SP(2)+1),
425
COUNTER(SP_PERFCTR_SP_SEL(3), RBBM_PERFCTR_SP(3), RBBM_PERFCTR_SP(3)+1),
426
COUNTER(SP_PERFCTR_SP_SEL(4), RBBM_PERFCTR_SP(4), RBBM_PERFCTR_SP(4)+1),
427
COUNTER(SP_PERFCTR_SP_SEL(5), RBBM_PERFCTR_SP(5), RBBM_PERFCTR_SP(5)+1),
428
COUNTER(SP_PERFCTR_SP_SEL(6), RBBM_PERFCTR_SP(6), RBBM_PERFCTR_SP(6)+1),
429
COUNTER(SP_PERFCTR_SP_SEL(7), RBBM_PERFCTR_SP(7), RBBM_PERFCTR_SP(7)+1),
430
COUNTER(SP_PERFCTR_SP_SEL(8), RBBM_PERFCTR_SP(8), RBBM_PERFCTR_SP(8)+1),
431
COUNTER(SP_PERFCTR_SP_SEL(9), RBBM_PERFCTR_SP(9), RBBM_PERFCTR_SP(9)+1),
432
COUNTER(SP_PERFCTR_SP_SEL(10), RBBM_PERFCTR_SP(10), RBBM_PERFCTR_SP(10)+1),
433
COUNTER(SP_PERFCTR_SP_SEL(11), RBBM_PERFCTR_SP(11), RBBM_PERFCTR_SP(11)+1),
434
COUNTER(SP_PERFCTR_SP_SEL(12), RBBM_PERFCTR_SP(12), RBBM_PERFCTR_SP(12)+1),
435
COUNTER(SP_PERFCTR_SP_SEL(13), RBBM_PERFCTR_SP(13), RBBM_PERFCTR_SP(13)+1),
436
COUNTER(SP_PERFCTR_SP_SEL(14), RBBM_PERFCTR_SP(14), RBBM_PERFCTR_SP(14)+1),
437
COUNTER(SP_PERFCTR_SP_SEL(15), RBBM_PERFCTR_SP(15), RBBM_PERFCTR_SP(15)+1),
438
COUNTER(SP_PERFCTR_SP_SEL(16), RBBM_PERFCTR_SP(16), RBBM_PERFCTR_SP(16)+1),
439
COUNTER(SP_PERFCTR_SP_SEL(17), RBBM_PERFCTR_SP(17), RBBM_PERFCTR_SP(17)+1),
440
COUNTER(SP_PERFCTR_SP_SEL(18), RBBM_PERFCTR_SP(18), RBBM_PERFCTR_SP(18)+1),
441
COUNTER(SP_PERFCTR_SP_SEL(19), RBBM_PERFCTR_SP(19), RBBM_PERFCTR_SP(19)+1),
442
COUNTER(SP_PERFCTR_SP_SEL(20), RBBM_PERFCTR_SP(20), RBBM_PERFCTR_SP(20)+1),
443
COUNTER(SP_PERFCTR_SP_SEL(21), RBBM_PERFCTR_SP(21), RBBM_PERFCTR_SP(21)+1),
444
COUNTER(SP_PERFCTR_SP_SEL(22), RBBM_PERFCTR_SP(22), RBBM_PERFCTR_SP(22)+1),
445
COUNTER(SP_PERFCTR_SP_SEL(23), RBBM_PERFCTR_SP(23), RBBM_PERFCTR_SP(23)+1),
448
static const struct fd_perfcntr_countable sp_countables[] = {
449
COUNTABLE(PERF_SP_BUSY_CYCLES, UINT64, AVERAGE),
450
COUNTABLE(PERF_SP_ALU_WORKING_CYCLES, UINT64, AVERAGE),
451
COUNTABLE(PERF_SP_EFU_WORKING_CYCLES, UINT64, AVERAGE),
452
COUNTABLE(PERF_SP_STALL_CYCLES_VPC, UINT64, AVERAGE),
453
COUNTABLE(PERF_SP_STALL_CYCLES_TP, UINT64, AVERAGE),
454
COUNTABLE(PERF_SP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
455
COUNTABLE(PERF_SP_STALL_CYCLES_RB, UINT64, AVERAGE),
456
COUNTABLE(PERF_SP_NON_EXECUTION_CYCLES, UINT64, AVERAGE),
457
COUNTABLE(PERF_SP_WAVE_CONTEXTS, UINT64, AVERAGE),
458
COUNTABLE(PERF_SP_WAVE_CONTEXT_CYCLES, UINT64, AVERAGE),
459
COUNTABLE(PERF_SP_FS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
460
COUNTABLE(PERF_SP_FS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
461
COUNTABLE(PERF_SP_VS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
462
COUNTABLE(PERF_SP_VS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
463
COUNTABLE(PERF_SP_FS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
464
COUNTABLE(PERF_SP_VS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
465
COUNTABLE(PERF_SP_WAVE_CTRL_CYCLES, UINT64, AVERAGE),
466
COUNTABLE(PERF_SP_WAVE_LOAD_CYCLES, UINT64, AVERAGE),
467
COUNTABLE(PERF_SP_WAVE_EMIT_CYCLES, UINT64, AVERAGE),
468
COUNTABLE(PERF_SP_WAVE_NOP_CYCLES, UINT64, AVERAGE),
469
COUNTABLE(PERF_SP_WAVE_WAIT_CYCLES, UINT64, AVERAGE),
470
COUNTABLE(PERF_SP_WAVE_FETCH_CYCLES, UINT64, AVERAGE),
471
COUNTABLE(PERF_SP_WAVE_IDLE_CYCLES, UINT64, AVERAGE),
472
COUNTABLE(PERF_SP_WAVE_END_CYCLES, UINT64, AVERAGE),
473
COUNTABLE(PERF_SP_WAVE_LONG_SYNC_CYCLES, UINT64, AVERAGE),
474
COUNTABLE(PERF_SP_WAVE_SHORT_SYNC_CYCLES, UINT64, AVERAGE),
475
COUNTABLE(PERF_SP_WAVE_JOIN_CYCLES, UINT64, AVERAGE),
476
COUNTABLE(PERF_SP_LM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
477
COUNTABLE(PERF_SP_LM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
478
COUNTABLE(PERF_SP_LM_ATOMICS, UINT64, AVERAGE),
479
COUNTABLE(PERF_SP_GM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
480
COUNTABLE(PERF_SP_GM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
481
COUNTABLE(PERF_SP_GM_ATOMICS, UINT64, AVERAGE),
482
COUNTABLE(PERF_SP_VS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
483
COUNTABLE(PERF_SP_VS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
484
COUNTABLE(PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
485
COUNTABLE(PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
486
COUNTABLE(PERF_SP_FS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
487
COUNTABLE(PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS, UINT64, AVERAGE),
488
COUNTABLE(PERF_SP_FS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
489
COUNTABLE(PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
490
COUNTABLE(PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
491
COUNTABLE(PERF_SP_FS_STAGE_BARY_INSTRUCTIONS, UINT64, AVERAGE),
492
COUNTABLE(PERF_SP_VS_INSTRUCTIONS, UINT64, AVERAGE),
493
COUNTABLE(PERF_SP_FS_INSTRUCTIONS, UINT64, AVERAGE),
494
COUNTABLE(PERF_SP_ADDR_LOCK_COUNT, UINT64, AVERAGE),
495
COUNTABLE(PERF_SP_UCHE_READ_TRANS, UINT64, AVERAGE),
496
COUNTABLE(PERF_SP_UCHE_WRITE_TRANS, UINT64, AVERAGE),
497
COUNTABLE(PERF_SP_EXPORT_VPC_TRANS, UINT64, AVERAGE),
498
COUNTABLE(PERF_SP_EXPORT_RB_TRANS, UINT64, AVERAGE),
499
COUNTABLE(PERF_SP_PIXELS_KILLED, UINT64, AVERAGE),
500
COUNTABLE(PERF_SP_ICL1_REQUESTS, UINT64, AVERAGE),
501
COUNTABLE(PERF_SP_ICL1_MISSES, UINT64, AVERAGE),
502
COUNTABLE(PERF_SP_HS_INSTRUCTIONS, UINT64, AVERAGE),
503
COUNTABLE(PERF_SP_DS_INSTRUCTIONS, UINT64, AVERAGE),
504
COUNTABLE(PERF_SP_GS_INSTRUCTIONS, UINT64, AVERAGE),
505
COUNTABLE(PERF_SP_CS_INSTRUCTIONS, UINT64, AVERAGE),
506
COUNTABLE(PERF_SP_GPR_READ, UINT64, AVERAGE),
507
COUNTABLE(PERF_SP_GPR_WRITE, UINT64, AVERAGE),
508
COUNTABLE(PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS, UINT64, AVERAGE),
509
COUNTABLE(PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS, UINT64, AVERAGE),
510
COUNTABLE(PERF_SP_LM_BANK_CONFLICTS, UINT64, AVERAGE),
511
COUNTABLE(PERF_SP_TEX_CONTROL_WORKING_CYCLES, UINT64, AVERAGE),
512
COUNTABLE(PERF_SP_LOAD_CONTROL_WORKING_CYCLES, UINT64, AVERAGE),
513
COUNTABLE(PERF_SP_FLOW_CONTROL_WORKING_CYCLES, UINT64, AVERAGE),
514
COUNTABLE(PERF_SP_LM_WORKING_CYCLES, UINT64, AVERAGE),
515
COUNTABLE(PERF_SP_DISPATCHER_WORKING_CYCLES, UINT64, AVERAGE),
516
COUNTABLE(PERF_SP_SEQUENCER_WORKING_CYCLES, UINT64, AVERAGE),
517
COUNTABLE(PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP, UINT64, AVERAGE),
518
COUNTABLE(PERF_SP_STARVE_CYCLES_HLSQ, UINT64, AVERAGE),
519
COUNTABLE(PERF_SP_NON_EXECUTION_LS_CYCLES, UINT64, AVERAGE),
520
COUNTABLE(PERF_SP_WORKING_EU, UINT64, AVERAGE),
521
COUNTABLE(PERF_SP_ANY_EU_WORKING, UINT64, AVERAGE),
522
COUNTABLE(PERF_SP_WORKING_EU_FS_STAGE, UINT64, AVERAGE),
523
COUNTABLE(PERF_SP_ANY_EU_WORKING_FS_STAGE, UINT64, AVERAGE),
524
COUNTABLE(PERF_SP_WORKING_EU_VS_STAGE, UINT64, AVERAGE),
525
COUNTABLE(PERF_SP_ANY_EU_WORKING_VS_STAGE, UINT64, AVERAGE),
526
COUNTABLE(PERF_SP_WORKING_EU_CS_STAGE, UINT64, AVERAGE),
527
COUNTABLE(PERF_SP_ANY_EU_WORKING_CS_STAGE, UINT64, AVERAGE),
528
COUNTABLE(PERF_SP_GPR_READ_PREFETCH, UINT64, AVERAGE),
529
COUNTABLE(PERF_SP_GPR_READ_CONFLICT, UINT64, AVERAGE),
530
COUNTABLE(PERF_SP_GPR_WRITE_CONFLICT, UINT64, AVERAGE),
531
COUNTABLE(PERF_SP_GM_LOAD_LATENCY_CYCLES, UINT64, AVERAGE),
532
COUNTABLE(PERF_SP_GM_LOAD_LATENCY_SAMPLES, UINT64, AVERAGE),
533
COUNTABLE(PERF_SP_EXECUTABLE_WAVES, UINT64, AVERAGE),
536
static const struct fd_perfcntr_counter tp_counters[] = {
537
COUNTER(TPL1_PERFCTR_TP_SEL(0), RBBM_PERFCTR_TP(0), RBBM_PERFCTR_TP(0)+1),
538
COUNTER(TPL1_PERFCTR_TP_SEL(1), RBBM_PERFCTR_TP(1), RBBM_PERFCTR_TP(1)+1),
539
COUNTER(TPL1_PERFCTR_TP_SEL(2), RBBM_PERFCTR_TP(2), RBBM_PERFCTR_TP(2)+1),
540
COUNTER(TPL1_PERFCTR_TP_SEL(3), RBBM_PERFCTR_TP(3), RBBM_PERFCTR_TP(3)+1),
541
COUNTER(TPL1_PERFCTR_TP_SEL(4), RBBM_PERFCTR_TP(4), RBBM_PERFCTR_TP(4)+1),
542
COUNTER(TPL1_PERFCTR_TP_SEL(5), RBBM_PERFCTR_TP(5), RBBM_PERFCTR_TP(5)+1),
543
COUNTER(TPL1_PERFCTR_TP_SEL(6), RBBM_PERFCTR_TP(6), RBBM_PERFCTR_TP(6)+1),
544
COUNTER(TPL1_PERFCTR_TP_SEL(7), RBBM_PERFCTR_TP(7), RBBM_PERFCTR_TP(7)+1),
545
COUNTER(TPL1_PERFCTR_TP_SEL(8), RBBM_PERFCTR_TP(8), RBBM_PERFCTR_TP(8)+1),
546
COUNTER(TPL1_PERFCTR_TP_SEL(9), RBBM_PERFCTR_TP(9), RBBM_PERFCTR_TP(9)+1),
547
COUNTER(TPL1_PERFCTR_TP_SEL(10), RBBM_PERFCTR_TP(10), RBBM_PERFCTR_TP(10)+1),
548
COUNTER(TPL1_PERFCTR_TP_SEL(11), RBBM_PERFCTR_TP(11), RBBM_PERFCTR_TP(11)+1),
551
static const struct fd_perfcntr_countable tp_countables[] = {
552
COUNTABLE(PERF_TP_BUSY_CYCLES, UINT64, AVERAGE),
553
COUNTABLE(PERF_TP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
554
COUNTABLE(PERF_TP_LATENCY_CYCLES, UINT64, AVERAGE),
555
COUNTABLE(PERF_TP_LATENCY_TRANS, UINT64, AVERAGE),
556
COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_SAMPLES, UINT64, AVERAGE),
557
COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_LATENCY, UINT64, AVERAGE),
558
COUNTABLE(PERF_TP_L1_CACHELINE_REQUESTS, UINT64, AVERAGE),
559
COUNTABLE(PERF_TP_L1_CACHELINE_MISSES, UINT64, AVERAGE),
560
COUNTABLE(PERF_TP_SP_TP_TRANS, UINT64, AVERAGE),
561
COUNTABLE(PERF_TP_TP_SP_TRANS, UINT64, AVERAGE),
562
COUNTABLE(PERF_TP_OUTPUT_PIXELS, UINT64, AVERAGE),
563
COUNTABLE(PERF_TP_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
564
COUNTABLE(PERF_TP_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
565
COUNTABLE(PERF_TP_QUADS_RECEIVED, UINT64, AVERAGE),
566
COUNTABLE(PERF_TP_QUADS_OFFSET, UINT64, AVERAGE),
567
COUNTABLE(PERF_TP_QUADS_SHADOW, UINT64, AVERAGE),
568
COUNTABLE(PERF_TP_QUADS_ARRAY, UINT64, AVERAGE),
569
COUNTABLE(PERF_TP_QUADS_GRADIENT, UINT64, AVERAGE),
570
COUNTABLE(PERF_TP_QUADS_1D, UINT64, AVERAGE),
571
COUNTABLE(PERF_TP_QUADS_2D, UINT64, AVERAGE),
572
COUNTABLE(PERF_TP_QUADS_BUFFER, UINT64, AVERAGE),
573
COUNTABLE(PERF_TP_QUADS_3D, UINT64, AVERAGE),
574
COUNTABLE(PERF_TP_QUADS_CUBE, UINT64, AVERAGE),
575
COUNTABLE(PERF_TP_DIVERGENT_QUADS_RECEIVED, UINT64, AVERAGE),
576
COUNTABLE(PERF_TP_PRT_NON_RESIDENT_EVENTS, UINT64, AVERAGE),
577
COUNTABLE(PERF_TP_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
578
COUNTABLE(PERF_TP_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
579
COUNTABLE(PERF_TP_OUTPUT_PIXELS_MIP, UINT64, AVERAGE),
580
COUNTABLE(PERF_TP_OUTPUT_PIXELS_ANISO, UINT64, AVERAGE),
581
COUNTABLE(PERF_TP_OUTPUT_PIXELS_ZERO_LOD, UINT64, AVERAGE),
582
COUNTABLE(PERF_TP_FLAG_CACHE_REQUESTS, UINT64, AVERAGE),
583
COUNTABLE(PERF_TP_FLAG_CACHE_MISSES, UINT64, AVERAGE),
584
COUNTABLE(PERF_TP_L1_5_L2_REQUESTS, UINT64, AVERAGE),
585
COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS, UINT64, AVERAGE),
586
COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
587
COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
588
COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
589
COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
590
COUNTABLE(PERF_TP_TPA2TPC_TRANS, UINT64, AVERAGE),
591
COUNTABLE(PERF_TP_L1_MISSES_ASTC_1TILE, UINT64, AVERAGE),
592
COUNTABLE(PERF_TP_L1_MISSES_ASTC_2TILE, UINT64, AVERAGE),
593
COUNTABLE(PERF_TP_L1_MISSES_ASTC_4TILE, UINT64, AVERAGE),
594
COUNTABLE(PERF_TP_L1_5_L2_COMPRESS_REQS, UINT64, AVERAGE),
595
COUNTABLE(PERF_TP_L1_5_L2_COMPRESS_MISS, UINT64, AVERAGE),
596
COUNTABLE(PERF_TP_L1_BANK_CONFLICT, UINT64, AVERAGE),
597
COUNTABLE(PERF_TP_L1_5_MISS_LATENCY_CYCLES, UINT64, AVERAGE),
598
COUNTABLE(PERF_TP_L1_5_MISS_LATENCY_TRANS, UINT64, AVERAGE),
599
COUNTABLE(PERF_TP_QUADS_CONSTANT_MULTIPLIED, UINT64, AVERAGE),
600
COUNTABLE(PERF_TP_FRONTEND_WORKING_CYCLES, UINT64, AVERAGE),
601
COUNTABLE(PERF_TP_L1_TAG_WORKING_CYCLES, UINT64, AVERAGE),
602
COUNTABLE(PERF_TP_L1_DATA_WRITE_WORKING_CYCLES, UINT64, AVERAGE),
603
COUNTABLE(PERF_TP_PRE_L1_DECOM_WORKING_CYCLES, UINT64, AVERAGE),
604
COUNTABLE(PERF_TP_BACKEND_WORKING_CYCLES, UINT64, AVERAGE),
605
COUNTABLE(PERF_TP_FLAG_CACHE_WORKING_CYCLES, UINT64, AVERAGE),
606
COUNTABLE(PERF_TP_L1_5_CACHE_WORKING_CYCLES, UINT64, AVERAGE),
607
COUNTABLE(PERF_TP_STARVE_CYCLES_SP, UINT64, AVERAGE),
608
COUNTABLE(PERF_TP_STARVE_CYCLES_UCHE, UINT64, AVERAGE),
611
static const struct fd_perfcntr_counter uche_counters[] = {
612
COUNTER(UCHE_PERFCTR_UCHE_SEL(0), RBBM_PERFCTR_UCHE(0), RBBM_PERFCTR_UCHE(0)+1),
613
COUNTER(UCHE_PERFCTR_UCHE_SEL(1), RBBM_PERFCTR_UCHE(1), RBBM_PERFCTR_UCHE(1)+1),
614
COUNTER(UCHE_PERFCTR_UCHE_SEL(2), RBBM_PERFCTR_UCHE(2), RBBM_PERFCTR_UCHE(2)+1),
615
COUNTER(UCHE_PERFCTR_UCHE_SEL(3), RBBM_PERFCTR_UCHE(3), RBBM_PERFCTR_UCHE(3)+1),
616
COUNTER(UCHE_PERFCTR_UCHE_SEL(4), RBBM_PERFCTR_UCHE(4), RBBM_PERFCTR_UCHE(4)+1),
617
COUNTER(UCHE_PERFCTR_UCHE_SEL(5), RBBM_PERFCTR_UCHE(5), RBBM_PERFCTR_UCHE(5)+1),
618
COUNTER(UCHE_PERFCTR_UCHE_SEL(6), RBBM_PERFCTR_UCHE(6), RBBM_PERFCTR_UCHE(6)+1),
619
COUNTER(UCHE_PERFCTR_UCHE_SEL(7), RBBM_PERFCTR_UCHE(7), RBBM_PERFCTR_UCHE(7)+1),
620
COUNTER(UCHE_PERFCTR_UCHE_SEL(8), RBBM_PERFCTR_UCHE(8), RBBM_PERFCTR_UCHE(8)+1),
621
COUNTER(UCHE_PERFCTR_UCHE_SEL(9), RBBM_PERFCTR_UCHE(9), RBBM_PERFCTR_UCHE(9)+1),
622
COUNTER(UCHE_PERFCTR_UCHE_SEL(10), RBBM_PERFCTR_UCHE(10), RBBM_PERFCTR_UCHE(10)+1),
623
COUNTER(UCHE_PERFCTR_UCHE_SEL(11), RBBM_PERFCTR_UCHE(11), RBBM_PERFCTR_UCHE(11)+1),
626
static const struct fd_perfcntr_countable uche_countables[] = {
627
COUNTABLE(PERF_UCHE_BUSY_CYCLES, UINT64, AVERAGE),
628
COUNTABLE(PERF_UCHE_STALL_CYCLES_ARBITER, UINT64, AVERAGE),
629
COUNTABLE(PERF_UCHE_VBIF_LATENCY_CYCLES, UINT64, AVERAGE),
630
COUNTABLE(PERF_UCHE_VBIF_LATENCY_SAMPLES, UINT64, AVERAGE),
631
COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_TP, UINT64, AVERAGE),
632
COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_VFD, UINT64, AVERAGE),
633
COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_HLSQ, UINT64, AVERAGE),
634
COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_LRZ, UINT64, AVERAGE),
635
COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_SP, UINT64, AVERAGE),
636
COUNTABLE(PERF_UCHE_READ_REQUESTS_TP, UINT64, AVERAGE),
637
COUNTABLE(PERF_UCHE_READ_REQUESTS_VFD, UINT64, AVERAGE),
638
COUNTABLE(PERF_UCHE_READ_REQUESTS_HLSQ, UINT64, AVERAGE),
639
COUNTABLE(PERF_UCHE_READ_REQUESTS_LRZ, UINT64, AVERAGE),
640
COUNTABLE(PERF_UCHE_READ_REQUESTS_SP, UINT64, AVERAGE),
641
COUNTABLE(PERF_UCHE_WRITE_REQUESTS_LRZ, UINT64, AVERAGE),
642
COUNTABLE(PERF_UCHE_WRITE_REQUESTS_SP, UINT64, AVERAGE),
643
COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VPC, UINT64, AVERAGE),
644
COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VSC, UINT64, AVERAGE),
645
COUNTABLE(PERF_UCHE_EVICTS, UINT64, AVERAGE),
646
COUNTABLE(PERF_UCHE_BANK_REQ0, UINT64, AVERAGE),
647
COUNTABLE(PERF_UCHE_BANK_REQ1, UINT64, AVERAGE),
648
COUNTABLE(PERF_UCHE_BANK_REQ2, UINT64, AVERAGE),
649
COUNTABLE(PERF_UCHE_BANK_REQ3, UINT64, AVERAGE),
650
COUNTABLE(PERF_UCHE_BANK_REQ4, UINT64, AVERAGE),
651
COUNTABLE(PERF_UCHE_BANK_REQ5, UINT64, AVERAGE),
652
COUNTABLE(PERF_UCHE_BANK_REQ6, UINT64, AVERAGE),
653
COUNTABLE(PERF_UCHE_BANK_REQ7, UINT64, AVERAGE),
654
COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH0, UINT64, AVERAGE),
655
COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH1, UINT64, AVERAGE),
656
COUNTABLE(PERF_UCHE_GMEM_READ_BEATS, UINT64, AVERAGE),
657
COUNTABLE(PERF_UCHE_TPH_REF_FULL, UINT64, AVERAGE),
658
COUNTABLE(PERF_UCHE_TPH_VICTIM_FULL, UINT64, AVERAGE),
659
COUNTABLE(PERF_UCHE_TPH_EXT_FULL, UINT64, AVERAGE),
660
COUNTABLE(PERF_UCHE_VBIF_STALL_WRITE_DATA, UINT64, AVERAGE),
661
COUNTABLE(PERF_UCHE_DCMP_LATENCY_SAMPLES, UINT64, AVERAGE),
662
COUNTABLE(PERF_UCHE_DCMP_LATENCY_CYCLES, UINT64, AVERAGE),
663
COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_PC, UINT64, AVERAGE),
664
COUNTABLE(PERF_UCHE_READ_REQUESTS_PC, UINT64, AVERAGE),
665
COUNTABLE(PERF_UCHE_RAM_READ_REQ, UINT64, AVERAGE),
666
COUNTABLE(PERF_UCHE_RAM_WRITE_REQ, UINT64, AVERAGE),
669
static const struct fd_perfcntr_counter vfd_counters[] = {
670
COUNTER(VFD_PERFCTR_VFD_SEL(0), RBBM_PERFCTR_VFD(0), RBBM_PERFCTR_VFD(0)+1),
671
COUNTER(VFD_PERFCTR_VFD_SEL(1), RBBM_PERFCTR_VFD(1), RBBM_PERFCTR_VFD(1)+1),
672
COUNTER(VFD_PERFCTR_VFD_SEL(2), RBBM_PERFCTR_VFD(2), RBBM_PERFCTR_VFD(2)+1),
673
COUNTER(VFD_PERFCTR_VFD_SEL(3), RBBM_PERFCTR_VFD(3), RBBM_PERFCTR_VFD(3)+1),
674
COUNTER(VFD_PERFCTR_VFD_SEL(4), RBBM_PERFCTR_VFD(4), RBBM_PERFCTR_VFD(4)+1),
675
COUNTER(VFD_PERFCTR_VFD_SEL(5), RBBM_PERFCTR_VFD(5), RBBM_PERFCTR_VFD(5)+1),
676
COUNTER(VFD_PERFCTR_VFD_SEL(6), RBBM_PERFCTR_VFD(6), RBBM_PERFCTR_VFD(6)+1),
677
COUNTER(VFD_PERFCTR_VFD_SEL(7), RBBM_PERFCTR_VFD(7), RBBM_PERFCTR_VFD(7)+1),
680
static const struct fd_perfcntr_countable vfd_countables[] = {
681
COUNTABLE(PERF_VFD_BUSY_CYCLES, UINT64, AVERAGE),
682
COUNTABLE(PERF_VFD_STALL_CYCLES_UCHE, UINT64, AVERAGE),
683
COUNTABLE(PERF_VFD_STALL_CYCLES_VPC_ALLOC, UINT64, AVERAGE),
684
COUNTABLE(PERF_VFD_STALL_CYCLES_SP_INFO, UINT64, AVERAGE),
685
COUNTABLE(PERF_VFD_STALL_CYCLES_SP_ATTR, UINT64, AVERAGE),
686
COUNTABLE(PERF_VFD_STARVE_CYCLES_UCHE, UINT64, AVERAGE),
687
COUNTABLE(PERF_VFD_RBUFFER_FULL, UINT64, AVERAGE),
688
COUNTABLE(PERF_VFD_ATTR_INFO_FIFO_FULL, UINT64, AVERAGE),
689
COUNTABLE(PERF_VFD_DECODED_ATTRIBUTE_BYTES, UINT64, AVERAGE),
690
COUNTABLE(PERF_VFD_NUM_ATTRIBUTES, UINT64, AVERAGE),
691
COUNTABLE(PERF_VFD_UPPER_SHADER_FIBERS, UINT64, AVERAGE),
692
COUNTABLE(PERF_VFD_LOWER_SHADER_FIBERS, UINT64, AVERAGE),
693
COUNTABLE(PERF_VFD_MODE_0_FIBERS, UINT64, AVERAGE),
694
COUNTABLE(PERF_VFD_MODE_1_FIBERS, UINT64, AVERAGE),
695
COUNTABLE(PERF_VFD_MODE_2_FIBERS, UINT64, AVERAGE),
696
COUNTABLE(PERF_VFD_MODE_3_FIBERS, UINT64, AVERAGE),
697
COUNTABLE(PERF_VFD_MODE_4_FIBERS, UINT64, AVERAGE),
698
COUNTABLE(PERF_VFD_TOTAL_VERTICES, UINT64, AVERAGE),
699
COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD, UINT64, AVERAGE),
700
COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_INDEX, UINT64, AVERAGE),
701
COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_PROG, UINT64, AVERAGE),
702
COUNTABLE(PERF_VFDP_STARVE_CYCLES_PC, UINT64, AVERAGE),
703
COUNTABLE(PERF_VFDP_VS_STAGE_WAVES, UINT64, AVERAGE),
706
static const struct fd_perfcntr_counter vpc_counters[] = {
707
COUNTER(VPC_PERFCTR_VPC_SEL(0), RBBM_PERFCTR_VPC(0), RBBM_PERFCTR_VPC(0)+1),
708
COUNTER(VPC_PERFCTR_VPC_SEL(1), RBBM_PERFCTR_VPC(1), RBBM_PERFCTR_VPC(1)+1),
709
COUNTER(VPC_PERFCTR_VPC_SEL(2), RBBM_PERFCTR_VPC(2), RBBM_PERFCTR_VPC(2)+1),
710
COUNTER(VPC_PERFCTR_VPC_SEL(3), RBBM_PERFCTR_VPC(3), RBBM_PERFCTR_VPC(3)+1),
711
COUNTER(VPC_PERFCTR_VPC_SEL(4), RBBM_PERFCTR_VPC(4), RBBM_PERFCTR_VPC(4)+1),
712
COUNTER(VPC_PERFCTR_VPC_SEL(5), RBBM_PERFCTR_VPC(5), RBBM_PERFCTR_VPC(5)+1),
715
static const struct fd_perfcntr_countable vpc_countables[] = {
716
COUNTABLE(PERF_VPC_BUSY_CYCLES, UINT64, AVERAGE),
717
COUNTABLE(PERF_VPC_WORKING_CYCLES, UINT64, AVERAGE),
718
COUNTABLE(PERF_VPC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
719
COUNTABLE(PERF_VPC_STALL_CYCLES_VFD_WACK, UINT64, AVERAGE),
720
COUNTABLE(PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC, UINT64, AVERAGE),
721
COUNTABLE(PERF_VPC_STALL_CYCLES_PC, UINT64, AVERAGE),
722
COUNTABLE(PERF_VPC_STALL_CYCLES_SP_LM, UINT64, AVERAGE),
723
COUNTABLE(PERF_VPC_STARVE_CYCLES_SP, UINT64, AVERAGE),
724
COUNTABLE(PERF_VPC_STARVE_CYCLES_LRZ, UINT64, AVERAGE),
725
COUNTABLE(PERF_VPC_PC_PRIMITIVES, UINT64, AVERAGE),
726
COUNTABLE(PERF_VPC_SP_COMPONENTS, UINT64, AVERAGE),
727
COUNTABLE(PERF_VPC_STALL_CYCLES_VPCRAM_POS, UINT64, AVERAGE),
728
COUNTABLE(PERF_VPC_LRZ_ASSIGN_PRIMITIVES, UINT64, AVERAGE),
729
COUNTABLE(PERF_VPC_RB_VISIBLE_PRIMITIVES, UINT64, AVERAGE),
730
COUNTABLE(PERF_VPC_LM_TRANSACTION, UINT64, AVERAGE),
731
COUNTABLE(PERF_VPC_STREAMOUT_TRANSACTION, UINT64, AVERAGE),
732
COUNTABLE(PERF_VPC_VS_BUSY_CYCLES, UINT64, AVERAGE),
733
COUNTABLE(PERF_VPC_PS_BUSY_CYCLES, UINT64, AVERAGE),
734
COUNTABLE(PERF_VPC_VS_WORKING_CYCLES, UINT64, AVERAGE),
735
COUNTABLE(PERF_VPC_PS_WORKING_CYCLES, UINT64, AVERAGE),
736
COUNTABLE(PERF_VPC_STARVE_CYCLES_RB, UINT64, AVERAGE),
737
COUNTABLE(PERF_VPC_NUM_VPCRAM_READ_POS, UINT64, AVERAGE),
738
COUNTABLE(PERF_VPC_WIT_FULL_CYCLES, UINT64, AVERAGE),
739
COUNTABLE(PERF_VPC_VPCRAM_FULL_CYCLES, UINT64, AVERAGE),
740
COUNTABLE(PERF_VPC_LM_FULL_WAIT_FOR_INTP_END, UINT64, AVERAGE),
741
COUNTABLE(PERF_VPC_NUM_VPCRAM_WRITE, UINT64, AVERAGE),
742
COUNTABLE(PERF_VPC_NUM_VPCRAM_READ_SO, UINT64, AVERAGE),
743
COUNTABLE(PERF_VPC_NUM_ATTR_REQ_LM, UINT64, AVERAGE),
746
static const struct fd_perfcntr_counter vsc_counters[] = {
747
COUNTER(VSC_PERFCTR_VSC_SEL(0), RBBM_PERFCTR_VSC(0), RBBM_PERFCTR_VSC(0)+1),
748
COUNTER(VSC_PERFCTR_VSC_SEL(1), RBBM_PERFCTR_VSC(1), RBBM_PERFCTR_VSC(1)+1),
751
static const struct fd_perfcntr_countable vsc_countables[] = {
752
COUNTABLE(PERF_VSC_BUSY_CYCLES, UINT64, AVERAGE),
753
COUNTABLE(PERF_VSC_WORKING_CYCLES, UINT64, AVERAGE),
754
COUNTABLE(PERF_VSC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
755
COUNTABLE(PERF_VSC_EOT_NUM, UINT64, AVERAGE),
756
COUNTABLE(PERF_VSC_INPUT_TILES, UINT64, AVERAGE),
759
const struct fd_perfcntr_group a6xx_perfcntr_groups[] = {
760
GROUP("CP", cp_counters, cp_countables),
761
GROUP("CCU", ccu_counters, ccu_countables),
762
GROUP("TSE", tse_counters, tse_countables),
763
GROUP("RAS", ras_counters, ras_countables),
764
GROUP("LRZ", lrz_counters, lrz_countables),
765
GROUP("HLSQ", hlsq_counters, hlsq_countables),
766
GROUP("PC", pc_counters, pc_countables),
767
GROUP("RB", rb_counters, rb_countables),
768
// GROUP("RBBM", rbbm_counters, rbbm_countables),
769
GROUP("SP", sp_counters, sp_countables),
770
GROUP("TP", tp_counters, tp_countables),
771
GROUP("UCHE", uche_counters, uche_countables),
772
GROUP("VFD", vfd_counters, vfd_countables),
773
GROUP("VPC", vpc_counters, vpc_countables),
774
GROUP("VSC", vsc_counters, vsc_countables),
775
// GROUP("VBIF", vbif_counters, vbif_countables),
778
const unsigned a6xx_num_perfcntr_groups = ARRAY_SIZE(a6xx_perfcntr_groups);
780
#endif /* FD6_PERFCNTR_H_ */
added
removed
src/freedreno/perfcntrs/fd6_perfcntr.c
