1
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
11
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000040UD { align1 1N switch };
12
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000440UD { align1 1N switch };
13
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch };
14
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000480UD { align1 1N switch };