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* Copyright © Microsoft Corporation
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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#include "vk_command_pool.h"
28
#include "vk_command_buffer.h"
29
#include "vk_cmd_queue.h"
30
#include "vk_debug_report.h"
31
#include "vk_device.h"
34
#include "vk_physical_device.h"
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#include "vk_sync_binary.h"
38
#include "vk_shader_module.h"
39
#include "wsi_common.h"
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#include "util/bitset.h"
42
#include "util/blob.h"
43
#include "util/hash_table.h"
44
#include "util/u_dynarray.h"
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#include "shader_enums.h"
49
#include "dzn_entrypoints.h"
52
#include <vulkan/vulkan.h>
53
#include <vulkan/vk_icd.h>
57
#define D3D12_IGNORE_SDK_LAYERS
58
#include <directx/d3d12.h>
59
#include <wrl/client.h>
61
#include "spirv_to_dxil.h"
63
using Microsoft::WRL::ComPtr;
65
#define DZN_SWAP(a, b) \
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#define dzn_stub() unreachable("Unsupported feature")
74
struct dxil_validator;
79
struct dzn_meta_indirect_draw {
80
ID3D12RootSignature *root_sig;
81
ID3D12PipelineState *pipeline_state;
91
static inline enum dzn_index_type
92
dzn_index_type_from_size(uint8_t index_size)
95
case 0: return DZN_NO_INDEX;
96
case 2: return DZN_INDEX_2B;
97
case 4: return DZN_INDEX_4B;
98
default: unreachable("Invalid index size");
102
static inline enum dzn_index_type
103
dzn_index_type_from_dxgi_format(DXGI_FORMAT format)
106
case DXGI_FORMAT_UNKNOWN: return DZN_NO_INDEX;
107
case DXGI_FORMAT_R16_UINT: return DZN_INDEX_2B;
108
case DXGI_FORMAT_R32_UINT: return DZN_INDEX_4B;
109
default: unreachable("Invalid index format");
113
static inline uint8_t
114
dzn_index_size(enum dzn_index_type type)
117
case DZN_NO_INDEX: return 0;
118
case DZN_INDEX_2B: return 2;
119
case DZN_INDEX_4B: return 4;
120
default: unreachable("Invalid index type");
124
struct dzn_meta_triangle_fan_rewrite_index {
125
ID3D12RootSignature *root_sig;
126
ID3D12PipelineState *pipeline_state;
127
ID3D12CommandSignature *cmd_sig;
130
struct dzn_meta_blit_key {
133
DXGI_FORMAT out_format;
134
uint32_t samples : 6;
136
uint32_t out_type : 4;
137
uint32_t sampler_dim : 4;
138
uint32_t src_is_array : 1;
139
uint32_t resolve : 1;
140
uint32_t linear_filter : 1;
141
uint32_t padding : 11;
147
struct dzn_meta_blit {
148
ID3D12RootSignature *root_sig;
149
ID3D12PipelineState *pipeline_state;
152
struct dzn_meta_blits {
154
D3D12_SHADER_BYTECODE vs;
155
struct hash_table *fs;
157
struct hash_table_u64 *contexts;
160
const dzn_meta_blit *
161
dzn_meta_blits_get_context(dzn_device *device, const dzn_meta_blit_key *key);
163
#define MAX_SYNC_TYPES 3
164
#define MAX_QUEUE_FAMILIES 3
166
struct dzn_physical_device {
167
struct vk_physical_device vk;
168
struct list_head link;
170
struct vk_device_extension_table supported_extensions;
171
struct vk_physical_device_dispatch_table dispatch;
173
IDXGIAdapter1 *adapter;
174
DXGI_ADAPTER_DESC1 adapter_desc;
176
uint32_t queue_family_count;
178
VkQueueFamilyProperties props;
179
D3D12_COMMAND_QUEUE_DESC desc;
180
} queue_families[MAX_QUEUE_FAMILIES];
182
uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
183
uint8_t device_uuid[VK_UUID_SIZE];
184
uint8_t driver_uuid[VK_UUID_SIZE];
186
struct wsi_device wsi_device;
190
D3D_FEATURE_LEVEL feature_level;
191
D3D12_FEATURE_DATA_ARCHITECTURE1 architecture;
192
D3D12_FEATURE_DATA_D3D12_OPTIONS options;
193
VkPhysicalDeviceMemoryProperties memory;
194
D3D12_HEAP_FLAGS heap_flags_for_mem_type[VK_MAX_MEMORY_TYPES];
195
const struct vk_sync_type *sync_types[MAX_SYNC_TYPES + 1];
196
float timestamp_period;
199
D3D12_FEATURE_DATA_FORMAT_SUPPORT
200
dzn_physical_device_get_format_support(dzn_physical_device *pdev,
204
dzn_physical_device_get_mem_type_mask_for_resource(const dzn_physical_device *pdev,
205
const D3D12_RESOURCE_DESC *desc);
207
#define dzn_debug_ignored_stype(sType) \
208
mesa_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
211
dxgi_get_factory(bool debug);
213
PFN_D3D12_SERIALIZE_VERSIONED_ROOT_SIGNATURE
214
d3d12_get_serialize_root_sig(void);
217
d3d12_enable_debug_layer();
220
d3d12_enable_gpu_validation();
223
d3d12_create_device(IUnknown *adapter, bool experimental_features);
228
ID3D12CommandQueue *cmdqueue;
230
uint64_t fence_point = 0;
235
struct vk_device_extension_table enabled_extensions;
236
struct vk_device_dispatch_table cmd_dispatch;
240
struct dzn_meta_indirect_draw indirect_draws[DZN_NUM_INDIRECT_DRAW_TYPES];
241
struct dzn_meta_triangle_fan_rewrite_index triangle_fan[DZN_NUM_INDEX_TYPE];
242
struct dzn_meta_blits blits;
245
#define DZN_QUERY_REFS_SECTION_SIZE 4096
246
#define DZN_QUERY_REFS_ALL_ONES_OFFSET 0
247
#define DZN_QUERY_REFS_ALL_ZEROS_OFFSET (DZN_QUERY_REFS_ALL_ONES_OFFSET + DZN_QUERY_REFS_SECTION_SIZE)
248
#define DZN_QUERY_REFS_RES_SIZE (DZN_QUERY_REFS_ALL_ZEROS_OFFSET + DZN_QUERY_REFS_SECTION_SIZE)
249
ID3D12Resource *refs;
253
void dzn_meta_finish(dzn_device *device);
255
VkResult dzn_meta_init(dzn_device *device);
257
const dzn_meta_blit *
258
dzn_meta_blits_get_context(dzn_device *device,
259
const dzn_meta_blit_key *key);
261
ID3D12RootSignature *
262
dzn_device_create_root_sig(dzn_device *device,
263
const D3D12_VERSIONED_ROOT_SIGNATURE_DESC *desc);
265
struct dzn_device_memory {
266
struct vk_object_base base;
268
struct list_head link;
272
D3D12_RESOURCE_STATES initial_state; /* initial state for this memory type */
274
/* A buffer-resource spanning the entire heap, used for mapping memory */
275
ID3D12Resource *map_res;
277
VkDeviceSize map_size;
281
enum dzn_cmd_bindpoint_dirty {
282
DZN_CMD_BINDPOINT_DIRTY_PIPELINE = 1 << 0,
283
DZN_CMD_BINDPOINT_DIRTY_HEAPS = 1 << 1,
284
DZN_CMD_BINDPOINT_DIRTY_SYSVALS = 1 << 2,
288
DZN_CMD_DIRTY_VIEWPORTS = 1 << 0,
289
DZN_CMD_DIRTY_SCISSORS = 1 << 1,
290
DZN_CMD_DIRTY_IB = 1 << 2,
291
DZN_CMD_DIRTY_STENCIL_REF = 1 << 3,
292
DZN_CMD_DIRTY_STENCIL_COMPARE_MASK = 1 << 4,
293
DZN_CMD_DIRTY_STENCIL_WRITE_MASK = 1 << 5,
294
DZN_CMD_DIRTY_BLEND_CONSTANTS = 1 << 6,
299
#define MAX_SCISSOR 16
301
#define MAX_DYNAMIC_UNIFORM_BUFFERS 8
302
#define MAX_DYNAMIC_STORAGE_BUFFERS 4
303
#define MAX_DYNAMIC_BUFFERS \
304
(MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
305
#define MAX_PUSH_CONSTANT_DWORDS 32
307
#define NUM_BIND_POINT VK_PIPELINE_BIND_POINT_COMPUTE + 1
308
#define NUM_POOL_TYPES D3D12_DESCRIPTOR_HEAP_TYPE_SAMPLER + 1
310
#define dzn_foreach_pool_type(type) \
311
for (D3D12_DESCRIPTOR_HEAP_TYPE type = D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV; \
312
type <= D3D12_DESCRIPTOR_HEAP_TYPE_SAMPLER; \
313
type = (D3D12_DESCRIPTOR_HEAP_TYPE)(type + 1))
315
struct dzn_cmd_event_signal {
316
struct dzn_event *event;
320
struct dzn_cmd_buffer;
322
struct dzn_attachment {
333
VkImageAspectFlags aspects;
334
D3D12_RESOURCE_STATES before, last, after;
336
D3D12_RESOURCE_STATES before, last, after;
340
struct dzn_attachment_ref {
342
D3D12_RESOURCE_STATES before, during;
344
D3D12_RESOURCE_STATES before, during;
346
VkImageAspectFlags aspects;
349
struct dzn_descriptor_state {
351
const struct dzn_descriptor_set *set;
352
uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
354
struct dzn_descriptor_heap *heaps[NUM_POOL_TYPES];
358
struct dzn_image_view;
360
struct dzn_buffer_desc {
361
VkDescriptorType type;
362
const struct dzn_buffer *buffer;
367
struct dzn_descriptor_heap {
369
ID3D12DescriptorHeap *heap;
370
D3D12_DESCRIPTOR_HEAP_TYPE type;
377
D3D12_CPU_DESCRIPTOR_HANDLE
378
dzn_descriptor_heap_get_cpu_handle(const dzn_descriptor_heap *heap, uint32_t slot);
380
D3D12_GPU_DESCRIPTOR_HANDLE
381
dzn_descriptor_heap_get_gpu_handle(const dzn_descriptor_heap *heap, uint32_t slot);
384
dzn_descriptor_heap_write_image_view_desc(dzn_descriptor_heap *heap,
385
uint32_t heap_offset,
387
bool cube_as_2darray,
388
const dzn_image_view *iview);
391
dzn_descriptor_heap_write_buffer_desc(dzn_descriptor_heap *heap,
392
uint32_t heap_offset,
394
const dzn_buffer_desc *bdesc);
397
dzn_descriptor_heap_copy(dzn_descriptor_heap *dst_heap, uint32_t dst_heap_offset,
398
const dzn_descriptor_heap *src_heap, uint32_t src_heap_offset,
399
uint32_t desc_count);
401
struct dzn_descriptor_heap_pool_entry {
402
struct list_head link;
403
dzn_descriptor_heap heap;
406
struct dzn_descriptor_heap_pool {
407
const VkAllocationCallbacks *alloc;
408
D3D12_DESCRIPTOR_HEAP_TYPE type;
410
struct list_head active_heaps, free_heaps;
416
dzn_descriptor_heap_pool_init(dzn_descriptor_heap_pool *pool,
418
D3D12_DESCRIPTOR_HEAP_TYPE type,
420
const VkAllocationCallbacks *alloc);
423
dzn_descriptor_heap_pool_finish(dzn_descriptor_heap_pool *pool);
426
dzn_descriptor_heap_pool_reset(dzn_descriptor_heap_pool *pool);
429
dzn_descriptor_heap_pool_alloc_slots(dzn_descriptor_heap_pool *pool,
432
dzn_descriptor_heap **heap,
433
uint32_t *first_slot);
435
struct dzn_cmd_buffer_query_range {
436
struct dzn_query_pool *qpool;
437
uint32_t start, count;
440
struct dzn_cmd_buffer_query_pool_state {
441
struct util_dynarray reset, collect, wait, signal;
444
struct dzn_internal_resource {
445
struct list_head link;
449
enum dzn_event_state {
450
DZN_EVENT_STATE_EXTERNAL_WAIT = -1,
451
DZN_EVENT_STATE_RESET = 0,
452
DZN_EVENT_STATE_SET = 1,
455
struct dzn_cmd_buffer_push_constant_state {
458
uint32_t values[MAX_PUSH_CONSTANT_DWORDS];
461
struct dzn_cmd_buffer_state {
462
struct dzn_framebuffer *framebuffer;
463
D3D12_RECT render_area;
464
const struct dzn_pipeline *pipeline;
465
dzn_descriptor_heap *heaps[NUM_POOL_TYPES];
466
struct dzn_render_pass *pass;
468
BITSET_DECLARE(dirty, MAX_VBS);
469
D3D12_VERTEX_BUFFER_VIEW views[MAX_VBS];
472
D3D12_INDEX_BUFFER_VIEW view;
477
uint32_t ref, compare_mask, write_mask;
484
D3D12_VIEWPORT viewports[MAX_VP];
485
D3D12_RECT scissors[MAX_SCISSOR];
487
struct dzn_cmd_buffer_push_constant_state gfx, compute;
492
struct dzn_pipeline *pipeline;
493
struct dzn_descriptor_state desc_state;
495
} bindpoint[NUM_BIND_POINT];
497
struct dxil_spirv_vertex_runtime_data gfx;
498
struct dxil_spirv_compute_runtime_data compute;
502
struct dzn_cmd_buffer_rtv_key {
503
const struct dzn_image *image;
504
D3D12_RENDER_TARGET_VIEW_DESC desc;
507
struct dzn_cmd_buffer_rtv_entry {
508
struct dzn_cmd_buffer_rtv_key key;
509
D3D12_CPU_DESCRIPTOR_HANDLE handle;
512
struct dzn_cmd_buffer_dsv_key {
513
const struct dzn_image *image;
514
D3D12_DEPTH_STENCIL_VIEW_DESC desc;
517
struct dzn_cmd_buffer_dsv_entry {
518
struct dzn_cmd_buffer_dsv_key key;
519
D3D12_CPU_DESCRIPTOR_HANDLE handle;
522
struct dzn_cmd_buffer {
523
struct vk_command_buffer vk;
525
struct dzn_cmd_buffer_state state;
528
struct hash_table *ht;
529
struct util_dynarray reset;
530
struct util_dynarray wait;
531
struct util_dynarray signal;
535
struct hash_table *ht;
536
struct util_dynarray wait;
537
struct util_dynarray signal;
541
struct hash_table *ht;
542
dzn_descriptor_heap_pool pool;
545
dzn_descriptor_heap_pool cbv_srv_uav_pool, sampler_pool;
547
struct list_head internal_bufs;
549
ID3D12CommandAllocator *cmdalloc;
550
ID3D12GraphicsCommandList1 *cmdlist;
553
struct dzn_descriptor_pool {
554
struct vk_object_base base;
555
VkAllocationCallbacks alloc;
558
uint32_t used_set_count;
559
dzn_descriptor_set *sets;
560
dzn_descriptor_heap heaps[NUM_POOL_TYPES];
561
uint32_t desc_count[NUM_POOL_TYPES];
562
uint32_t used_desc_count[NUM_POOL_TYPES];
563
uint32_t free_offset[NUM_POOL_TYPES];
564
mtx_t defragment_lock;
567
#define MAX_SHADER_VISIBILITIES (D3D12_SHADER_VISIBILITY_PIXEL + 1)
569
struct dzn_descriptor_set_layout_binding {
570
VkDescriptorType type;
571
D3D12_SHADER_VISIBILITY visibility;
572
uint32_t base_shader_register;
573
uint32_t range_idx[NUM_POOL_TYPES];
576
uint32_t static_sampler_idx;
577
uint32_t immutable_sampler_idx;
579
uint32_t dynamic_buffer_idx;
583
struct dzn_descriptor_set_layout {
584
struct vk_object_base base;
585
uint32_t range_count[MAX_SHADER_VISIBILITIES][NUM_POOL_TYPES];
586
const D3D12_DESCRIPTOR_RANGE1 *ranges[MAX_SHADER_VISIBILITIES][NUM_POOL_TYPES];
587
uint32_t range_desc_count[NUM_POOL_TYPES];
588
uint32_t static_sampler_count;
589
const D3D12_STATIC_SAMPLER_DESC *static_samplers;
590
uint32_t immutable_sampler_count;
591
const dzn_sampler **immutable_samplers;
593
uint32_t bindings[MAX_DYNAMIC_BUFFERS];
596
uint32_t range_offset;
598
uint32_t binding_count;
599
const struct dzn_descriptor_set_layout_binding *bindings;
602
struct dzn_descriptor_set {
603
struct vk_object_base base;
604
struct dzn_buffer_desc dynamic_buffers[MAX_DYNAMIC_BUFFERS];
605
dzn_descriptor_pool *pool;
606
uint32_t heap_offsets[NUM_POOL_TYPES];
607
uint32_t heap_sizes[NUM_POOL_TYPES];
608
const struct dzn_descriptor_set_layout *layout;
611
struct dzn_pipeline_layout {
612
struct vk_object_base base;
615
uint32_t heap_offsets[NUM_POOL_TYPES];
618
} dynamic_buffer_heap_offsets[MAX_DYNAMIC_BUFFERS];
619
uint32_t dynamic_buffer_count;
620
uint32_t range_desc_count[NUM_POOL_TYPES];
622
dxil_spirv_vulkan_descriptor_set binding_translation[MAX_SETS];
624
uint32_t desc_count[NUM_POOL_TYPES];
626
uint32_t param_count;
627
uint32_t sets_param_count;
628
uint32_t sysval_cbv_param_idx;
629
uint32_t push_constant_cbv_param_idx;
630
D3D12_DESCRIPTOR_HEAP_TYPE type[MAX_SHADER_VISIBILITIES];
631
ID3D12RootSignature *sig;
635
dzn_pipeline_layout *
636
dzn_pipeline_layout_ref(dzn_pipeline_layout *layout);
639
dzn_pipeline_layout_unref(dzn_pipeline_layout *layout);
642
#define MAX_INPUT_ATTACHMENTS 4
645
uint32_t color_count;
646
struct dzn_attachment_ref colors[MAX_RTS];
647
struct dzn_attachment_ref resolve[MAX_RTS];
648
struct dzn_attachment_ref zs;
649
uint32_t input_count;
650
struct dzn_attachment_ref inputs[MAX_INPUT_ATTACHMENTS];
653
struct dzn_render_pass {
654
struct vk_object_base base;
655
uint32_t attachment_count;
656
struct dzn_attachment *attachments;
657
uint32_t subpass_count;
658
struct dzn_subpass *subpasses;
661
struct dzn_pipeline_cache {
662
struct vk_object_base base;
665
enum dzn_register_space {
666
DZN_REGISTER_SPACE_SYSVALS = MAX_SETS,
667
DZN_REGISTER_SPACE_PUSH_CONSTANT,
670
struct dzn_pipeline {
671
struct vk_object_base base;
672
VkPipelineBindPoint type;
675
uint32_t sets_param_count;
676
uint32_t sysval_cbv_param_idx;
677
uint32_t push_constant_cbv_param_idx;
678
D3D12_DESCRIPTOR_HEAP_TYPE type[MAX_SHADER_VISIBILITIES];
679
ID3D12RootSignature *sig;
682
uint32_t heap_offsets[NUM_POOL_TYPES];
685
} dynamic_buffer_heap_offsets[MAX_DYNAMIC_BUFFERS];
686
uint32_t dynamic_buffer_count;
687
uint32_t range_desc_count[NUM_POOL_TYPES];
689
uint32_t desc_count[NUM_POOL_TYPES];
690
ID3D12PipelineState *state;
693
enum dzn_indirect_draw_cmd_sig_type {
694
DZN_INDIRECT_DRAW_CMD_SIG,
695
DZN_INDIRECT_INDEXED_DRAW_CMD_SIG,
696
DZN_INDIRECT_DRAW_TRIANGLE_FAN_CMD_SIG,
697
DZN_NUM_INDIRECT_DRAW_CMD_SIGS,
700
struct dzn_graphics_pipeline {
704
uint32_t strides[MAX_VBS];
709
D3D_PRIMITIVE_TOPOLOGY topology;
715
D3D12_VIEWPORT desc[MAX_VP];
721
D3D12_RECT desc[MAX_SCISSOR];
727
bool independent_front_back;
729
bool dynamic_write_mask;
730
bool dynamic_compare_mask;
734
uint32_t compare_mask;
741
bool dynamic_constants;
745
ID3D12CommandSignature *indirect_cmd_sigs[DZN_NUM_INDIRECT_DRAW_CMD_SIGS];
748
ID3D12CommandSignature *
749
dzn_graphics_pipeline_get_indirect_cmd_sig(dzn_graphics_pipeline *pipeline,
750
enum dzn_indirect_draw_cmd_sig_type cmd_sig_type);
752
struct dzn_compute_pipeline {
758
ID3D12CommandSignature *indirect_cmd_sig;
761
ID3D12CommandSignature *
762
dzn_compute_pipeline_get_indirect_cmd_sig(dzn_compute_pipeline *pipeline);
764
#define MAX_MIP_LEVELS 14
770
uint32_t row_stride = 0;
773
D3D12_RESOURCE_DESC desc;
775
dzn_device_memory *mem;
776
VkDeviceSize mem_offset;
780
dzn_image_get_dxgi_format(VkFormat format,
781
VkImageUsageFlags usage,
782
VkImageAspectFlags aspects);
785
dzn_image_get_plane_format(VkFormat fmt, VkImageAspectFlags aspect);
788
dzn_image_get_placed_footprint_format(VkFormat fmt, VkImageAspectFlags aspect);
790
D3D12_DEPTH_STENCIL_VIEW_DESC
791
dzn_image_get_dsv_desc(const dzn_image *image,
792
const VkImageSubresourceRange *range,
795
D3D12_RENDER_TARGET_VIEW_DESC
796
dzn_image_get_rtv_desc(const dzn_image *image,
797
const VkImageSubresourceRange *range,
800
D3D12_RESOURCE_STATES
801
dzn_image_layout_to_state(VkImageLayout layout, VkImageAspectFlagBits aspect);
804
dzn_image_layers_get_subresource_index(const dzn_image *image,
805
const VkImageSubresourceLayers *subres,
806
VkImageAspectFlagBits aspect,
809
dzn_image_range_get_subresource_index(const dzn_image *image,
810
const VkImageSubresourceRange *range,
811
VkImageAspectFlagBits aspect,
812
uint32_t level, uint32_t layer);
814
D3D12_TEXTURE_COPY_LOCATION
815
dzn_image_get_copy_loc(const dzn_image *image,
816
const VkImageSubresourceLayers *layers,
817
VkImageAspectFlagBits aspect,
820
struct dzn_image_view {
821
struct vk_image_view vk;
822
D3D12_SHADER_RESOURCE_VIEW_DESC srv_desc;
823
D3D12_UNORDERED_ACCESS_VIEW_DESC uav_desc;
824
D3D12_RENDER_TARGET_VIEW_DESC rtv_desc;
825
D3D12_DEPTH_STENCIL_VIEW_DESC dsv_desc;
829
dzn_image_view_init(dzn_device *device,
830
dzn_image_view *iview,
831
const VkImageViewCreateInfo *info);
834
dzn_image_view_finish(dzn_image_view *iview);
837
struct vk_object_base base;
841
D3D12_RESOURCE_DESC desc;
844
VkBufferCreateFlags create_flags;
845
VkBufferUsageFlags usage;
849
dzn_buffer_get_dxgi_format(VkFormat format);
851
D3D12_TEXTURE_COPY_LOCATION
852
dzn_buffer_get_copy_loc(const dzn_buffer *buf, VkFormat format,
853
const VkBufferImageCopy2KHR *info,
854
VkImageAspectFlagBits aspect,
857
D3D12_TEXTURE_COPY_LOCATION
858
dzn_buffer_get_line_copy_loc(const dzn_buffer *buf, VkFormat format,
859
const VkBufferImageCopy2KHR *region,
860
const D3D12_TEXTURE_COPY_LOCATION *loc,
861
uint32_t y, uint32_t z, uint32_t *start_x);
864
dzn_buffer_supports_region_copy(const D3D12_TEXTURE_COPY_LOCATION *loc);
866
struct dzn_buffer_view {
867
struct vk_object_base base;
869
const dzn_buffer *buffer;
871
D3D12_SHADER_RESOURCE_VIEW_DESC srv_desc;
872
D3D12_UNORDERED_ACCESS_VIEW_DESC uav_desc;
875
struct dzn_framebuffer {
876
struct vk_object_base base;
878
uint32_t width, height, layers;
880
uint32_t attachment_count;
881
struct dzn_image_view **attachments;
885
struct vk_object_base base;
886
D3D12_SAMPLER_DESC desc;
887
D3D12_STATIC_BORDER_COLOR static_border_color = D3D12_STATIC_BORDER_COLOR_OPAQUE_BLACK;
890
/* This is defined as a macro so that it works for both
891
* VkImageSubresourceRange and VkImageSubresourceLayers
893
#define dzn_get_layer_count(_image, _range) \
894
((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
895
(_image)->vk.array_layers - (_range)->baseArrayLayer : (_range)->layerCount)
897
#define dzn_get_level_count(_image, _range) \
898
((_range)->levelCount == VK_REMAINING_MIP_LEVELS ? \
899
(_image)->vk.mip_levels - (_range)->baseMipLevel : (_range)->levelCount)
904
DXGI_FORMAT dzn_pipe_to_dxgi_format(enum pipe_format in);
905
D3D12_FILTER dzn_translate_sampler_filter(const VkSamplerCreateInfo *create_info);
906
D3D12_COMPARISON_FUNC dzn_translate_compare_op(VkCompareOp in);
907
void dzn_translate_viewport(D3D12_VIEWPORT *out, const VkViewport *in);
908
void dzn_translate_rect(D3D12_RECT *out, const VkRect2D *in);
913
#define dzn_foreach_aspect(aspect, mask) \
914
for (VkImageAspectFlagBits aspect = VK_IMAGE_ASPECT_COLOR_BIT; \
915
aspect <= VK_IMAGE_ASPECT_STENCIL_BIT; \
916
aspect = (VkImageAspectFlagBits)(aspect << 1)) \
919
VkResult dzn_wsi_init(struct dzn_physical_device *physical_device);
920
void dzn_wsi_finish(struct dzn_physical_device *physical_device);
922
struct dzn_app_info {
923
const char *app_name;
924
uint32_t app_version;
925
const char *engine_name;
926
uint32_t engine_version;
927
uint32_t api_version;
930
enum dzn_debug_flags {
931
DZN_DEBUG_SYNC = 1 << 0,
932
DZN_DEBUG_NIR = 1 << 1,
933
DZN_DEBUG_DXIL = 1 << 2,
934
DZN_DEBUG_WARP = 1 << 3,
935
DZN_DEBUG_INTERNAL = 1 << 4,
936
DZN_DEBUG_SIG = 1 << 5,
937
DZN_DEBUG_GBV = 1 << 6,
938
DZN_DEBUG_D3D12 = 1 << 7,
941
struct dzn_instance {
942
struct vk_instance vk;
944
struct dxil_validator *dxil_validator;
946
PFN_D3D12_SERIALIZE_VERSIONED_ROOT_SIGNATURE serialize_root_sig;
948
bool physical_devices_enumerated;
949
uint32_t debug_flags;
951
struct vk_sync_binary_type sync_binary_type;
953
struct list_head physical_devices;
957
struct vk_object_base base;
966
extern const struct vk_sync_type dzn_sync_type;
969
D3D12_QUERY_TYPE type;
971
uint64_t fence_value;
974
struct dzn_query_pool {
975
struct vk_object_base base;
977
D3D12_QUERY_HEAP_TYPE heap_type;
978
ID3D12QueryHeap *heap;
979
uint32_t query_count;
980
struct dzn_query *queries;
982
ID3D12Resource *resolve_buffer;
983
ID3D12Resource *collect_buffer;
984
VkQueryPipelineStatisticFlags pipeline_statistics;
986
uint64_t *collect_map;
990
dzn_query_pool_get_query_type(const dzn_query_pool *qpool, VkQueryControlFlags flag);
993
dzn_query_pool_get_result_offset(const dzn_query_pool *qpool, uint32_t query);
996
dzn_query_pool_get_availability_offset(const dzn_query_pool *qpool, uint32_t query);
999
dzn_query_pool_get_result_size(const dzn_query_pool *qpool, uint32_t count);
1001
VK_DEFINE_HANDLE_CASTS(dzn_cmd_buffer, vk.base, VkCommandBuffer, VK_OBJECT_TYPE_COMMAND_BUFFER)
1002
VK_DEFINE_HANDLE_CASTS(dzn_device, vk.base, VkDevice, VK_OBJECT_TYPE_DEVICE)
1003
VK_DEFINE_HANDLE_CASTS(dzn_instance, vk.base, VkInstance, VK_OBJECT_TYPE_INSTANCE)
1004
VK_DEFINE_HANDLE_CASTS(dzn_physical_device, vk.base, VkPhysicalDevice, VK_OBJECT_TYPE_PHYSICAL_DEVICE)
1005
VK_DEFINE_HANDLE_CASTS(dzn_queue, vk.base, VkQueue, VK_OBJECT_TYPE_QUEUE)
1007
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_buffer, base, VkBuffer, VK_OBJECT_TYPE_BUFFER)
1008
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_buffer_view, base, VkBufferView, VK_OBJECT_TYPE_BUFFER_VIEW)
1009
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_device_memory, base, VkDeviceMemory, VK_OBJECT_TYPE_DEVICE_MEMORY)
1010
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_descriptor_pool, base, VkDescriptorPool, VK_OBJECT_TYPE_DESCRIPTOR_POOL)
1011
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_descriptor_set, base, VkDescriptorSet, VK_OBJECT_TYPE_DESCRIPTOR_SET)
1012
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_descriptor_set_layout, base, VkDescriptorSetLayout, VK_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT)
1013
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_event, base, VkEvent, VK_OBJECT_TYPE_EVENT)
1014
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_framebuffer, base, VkFramebuffer, VK_OBJECT_TYPE_FRAMEBUFFER)
1015
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_image, vk.base, VkImage, VK_OBJECT_TYPE_IMAGE)
1016
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_image_view, vk.base, VkImageView, VK_OBJECT_TYPE_IMAGE_VIEW)
1017
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_pipeline, base, VkPipeline, VK_OBJECT_TYPE_PIPELINE)
1018
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_graphics_pipeline, base.base, VkPipeline, VK_OBJECT_TYPE_PIPELINE)
1019
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_compute_pipeline, base.base, VkPipeline, VK_OBJECT_TYPE_PIPELINE)
1020
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_pipeline_cache, base, VkPipelineCache, VK_OBJECT_TYPE_PIPELINE_CACHE)
1021
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_pipeline_layout, base, VkPipelineLayout, VK_OBJECT_TYPE_PIPELINE_LAYOUT)
1022
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_query_pool, base, VkQueryPool, VK_OBJECT_TYPE_QUERY_POOL)
1023
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_render_pass, base, VkRenderPass, VK_OBJECT_TYPE_RENDER_PASS)
1024
VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_sampler, base, VkSampler, VK_OBJECT_TYPE_SAMPLER)
1026
#endif /* DZN_PRIVATE_H */