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* Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* Rob Clark <robclark@freedesktop.org>
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#include "util/half_float.h"
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#include "util/u_math.h"
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#include "ir3_compiler.h"
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#include "ir3_shader.h"
37
__typeof(a) __tmp = (a); \
48
struct ir3_shader_variant *so;
52
/* is it a type preserving mov, with ok flags?
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* @instr: the mov to consider removing
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* @dst_instr: the instruction consuming the mov (instr)
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* TODO maybe drop allow_flags since this is only false when dst is
61
is_eligible_mov(struct ir3_instruction *instr,
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struct ir3_instruction *dst_instr, bool allow_flags)
64
if (is_same_type_mov(instr)) {
65
struct ir3_register *dst = instr->dsts[0];
66
struct ir3_register *src = instr->srcs[0];
67
struct ir3_instruction *src_instr = ssa(src);
69
/* only if mov src is SSA (not const/immed): */
74
if (dst->flags & IR3_REG_RELATIV)
76
if (src->flags & IR3_REG_RELATIV)
79
if (src->flags & IR3_REG_ARRAY)
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if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG | IR3_REG_SABS |
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IR3_REG_SNEG | IR3_REG_BNOT))
92
/* we can end up with extra cmps.s from frontend, which uses a
94
* cmps.s p0.x, cond, 0
96
* as a way to mov into the predicate register. But frequently 'cond'
97
* is itself a cmps.s/cmps.f/cmps.u. So detect this special case.
100
is_foldable_double_cmp(struct ir3_instruction *cmp)
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struct ir3_instruction *cond = ssa(cmp->srcs[0]);
103
return (cmp->dsts[0]->num == regid(REG_P0, 0)) && cond &&
104
(cmp->srcs[1]->flags & IR3_REG_IMMED) &&
105
(cmp->srcs[1]->iim_val == 0) &&
106
(cmp->cat2.condition == IR3_COND_NE) &&
107
(!cond->address || cond->address->def->instr->block == cmp->block);
110
/* propagate register flags from src to dst.. negates need special
111
* handling to cancel each other out.
114
combine_flags(unsigned *dstflags, struct ir3_instruction *src)
116
unsigned srcflags = src->srcs[0]->flags;
118
/* if what we are combining into already has (abs) flags,
119
* we can drop (neg) from src:
121
if (*dstflags & IR3_REG_FABS)
122
srcflags &= ~IR3_REG_FNEG;
123
if (*dstflags & IR3_REG_SABS)
124
srcflags &= ~IR3_REG_SNEG;
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if (srcflags & IR3_REG_FABS)
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*dstflags |= IR3_REG_FABS;
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if (srcflags & IR3_REG_SABS)
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*dstflags |= IR3_REG_SABS;
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if (srcflags & IR3_REG_FNEG)
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*dstflags ^= IR3_REG_FNEG;
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if (srcflags & IR3_REG_SNEG)
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*dstflags ^= IR3_REG_SNEG;
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if (srcflags & IR3_REG_BNOT)
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*dstflags ^= IR3_REG_BNOT;
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*dstflags &= ~IR3_REG_SSA;
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*dstflags |= srcflags & IR3_REG_SSA;
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*dstflags |= srcflags & IR3_REG_CONST;
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*dstflags |= srcflags & IR3_REG_IMMED;
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*dstflags |= srcflags & IR3_REG_RELATIV;
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*dstflags |= srcflags & IR3_REG_ARRAY;
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*dstflags |= srcflags & IR3_REG_SHARED;
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/* if src of the src is boolean we can drop the (abs) since we know
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* the source value is already a postitive integer. This cleans
147
* up the absnegs that get inserted when converting between nir and
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* native boolean (see ir3_b2n/n2b)
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struct ir3_instruction *srcsrc = ssa(src->srcs[0]);
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if (srcsrc && is_bool(srcsrc))
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*dstflags &= ~IR3_REG_SABS;
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/* Tries lowering an immediate register argument to a const buffer access by
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* adding to the list of immediates to be pushed to the const buffer when
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* switching to this shader.
160
lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n,
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struct ir3_register *reg, unsigned new_flags)
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if (!(new_flags & IR3_REG_IMMED))
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new_flags &= ~IR3_REG_IMMED;
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new_flags |= IR3_REG_CONST;
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if (!ir3_valid_flags(instr, n, new_flags))
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reg = ir3_reg_clone(ctx->shader, reg);
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/* Half constant registers seems to handle only 32-bit values
175
* within floating-point opcodes. So convert back to 32-bit values.
178
(is_cat2_float(instr->opc) || is_cat3_float(instr->opc)) ? true : false;
179
if (f_opcode && (new_flags & IR3_REG_HALF))
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reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
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/* in some cases, there are restrictions on (abs)/(neg) plus const..
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* so just evaluate those and clear the flags:
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if (new_flags & IR3_REG_SABS) {
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reg->iim_val = abs(reg->iim_val);
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new_flags &= ~IR3_REG_SABS;
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if (new_flags & IR3_REG_FABS) {
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reg->fim_val = fabs(reg->fim_val);
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new_flags &= ~IR3_REG_FABS;
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if (new_flags & IR3_REG_SNEG) {
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reg->iim_val = -reg->iim_val;
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new_flags &= ~IR3_REG_SNEG;
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if (new_flags & IR3_REG_FNEG) {
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reg->fim_val = -reg->fim_val;
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new_flags &= ~IR3_REG_FNEG;
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/* Reallocate for 4 more elements whenever it's necessary. Note that ir3
206
* printing relies on having groups of 4 dwords, so we fill the unused
207
* slots with a dummy value.
209
struct ir3_const_state *const_state = ir3_const_state(ctx->so);
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if (const_state->immediates_count == const_state->immediates_size) {
211
const_state->immediates = rerzalloc(
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const_state, const_state->immediates,
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__typeof__(const_state->immediates[0]), const_state->immediates_size,
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const_state->immediates_size + 4);
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const_state->immediates_size += 4;
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for (int i = const_state->immediates_count;
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i < const_state->immediates_size; i++)
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const_state->immediates[i] = 0xd0d0d0d0;
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for (i = 0; i < const_state->immediates_count; i++) {
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if (const_state->immediates[i] == reg->uim_val)
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if (i == const_state->immediates_count) {
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/* Add on a new immediate to be pushed, if we have space left in the
232
if (const_state->offsets.immediate + const_state->immediates_count / 4 >=
233
ir3_max_const(ctx->so))
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const_state->immediates[i] = reg->uim_val;
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const_state->immediates_count++;
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reg->flags = new_flags;
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reg->num = i + (4 * const_state->offsets.immediate);
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instr->srcs[n] = reg;
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unuse(struct ir3_instruction *instr)
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debug_assert(instr->use_count > 0);
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if (--instr->use_count == 0) {
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struct ir3_block *block = instr->block;
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instr->barrier_class = 0;
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instr->barrier_conflict = 0;
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/* we don't want to remove anything in keeps (which could
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* be things like array store's)
262
for (unsigned i = 0; i < block->keeps_count; i++) {
263
debug_assert(block->keeps[i] != instr);
269
* Handles the special case of the 2nd src (n == 1) to "normal" mad
270
* instructions, which cannot reference a constant. See if it is
271
* possible to swap the 1st and 2nd sources.
274
try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
276
if (!is_mad(instr->opc))
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/* If we've already tried, nothing more to gain.. we will only
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* have previously swapped if the original 2nd src was const or
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* immed. So swapping back won't improve anything and could
282
* result in an infinite "progress" loop.
284
if (instr->cat3.swapped)
287
/* cat3 doesn't encode immediate, but we can lower immediate
288
* to const if that helps:
290
if (new_flags & IR3_REG_IMMED) {
291
new_flags &= ~IR3_REG_IMMED;
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new_flags |= IR3_REG_CONST;
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/* If the reason we couldn't fold without swapping is something
296
* other than const source, then swapping won't help:
298
if (!(new_flags & IR3_REG_CONST))
301
instr->cat3.swapped = true;
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/* NOTE: pre-swap first two src's before valid_flags(),
304
* which might try to dereference the n'th src:
306
swap(instr->srcs[0], instr->srcs[1]);
309
/* can we propagate mov if we move 2nd src to first? */
310
ir3_valid_flags(instr, 0, new_flags) &&
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/* and does first src fit in second slot? */
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ir3_valid_flags(instr, 1, instr->srcs[1]->flags);
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/* put things back the way they were: */
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swap(instr->srcs[0], instr->srcs[1]);
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} /* otherwise leave things swapped */
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/* Values that are uniform inside a loop can become divergent outside
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* it if the loop has a divergent trip count. This means that we can't
324
* propagate a copy of a shared to non-shared register if it would
325
* make the shared reg's live range extend outside of its loop. Users
326
* outside the loop would see the value for the thread(s) that last
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* exited the loop, rather than for their own thread.
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is_valid_shared_copy(struct ir3_instruction *dst_instr,
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struct ir3_instruction *src_instr,
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struct ir3_register *src_reg)
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return !(src_reg->flags & IR3_REG_SHARED) ||
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dst_instr->block->loop_id == src_instr->block->loop_id;
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* Handle cp for a given src register. This additionally handles
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* the cases of collapsing immedate/const (which replace the src
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* register with a non-ssa src) or collapsing mov's from relative
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* src (which needs to also fixup the address src reference by the
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reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
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struct ir3_register *reg, unsigned n)
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struct ir3_instruction *src = ssa(reg);
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if (is_eligible_mov(src, instr, true)) {
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/* simple case, no immed/const/relativ, only mov's w/ ssa src: */
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struct ir3_register *src_reg = src->srcs[0];
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unsigned new_flags = reg->flags;
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if (!is_valid_shared_copy(instr, src, src_reg))
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combine_flags(&new_flags, src);
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if (ir3_valid_flags(instr, n, new_flags)) {
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if (new_flags & IR3_REG_ARRAY) {
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debug_assert(!(reg->flags & IR3_REG_ARRAY));
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reg->array = src_reg->array;
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reg->flags = new_flags;
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reg->def = src_reg->def;
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instr->barrier_class |= src->barrier_class;
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instr->barrier_conflict |= src->barrier_conflict;
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reg->def->instr->use_count++;
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} else if ((is_same_type_mov(src) || is_const_mov(src)) &&
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/* cannot collapse const/immed/etc into control flow: */
379
opc_cat(instr->opc) != 0) {
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/* immed/const/etc cases, which require some special handling: */
381
struct ir3_register *src_reg = src->srcs[0];
382
unsigned new_flags = reg->flags;
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if (!is_valid_shared_copy(instr, src, src_reg))
387
if (src_reg->flags & IR3_REG_ARRAY)
390
combine_flags(&new_flags, src);
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if (!ir3_valid_flags(instr, n, new_flags)) {
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/* See if lowering an immediate to const would help. */
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if (lower_immed(ctx, instr, n, src_reg, new_flags))
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/* special case for "normal" mad instructions, we can
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* try swapping the first two args if that fits better.
400
* the "plain" MAD's (ie. the ones that don't shift first
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* src prior to multiply) can swap their first two srcs if
402
* src[0] is !CONST and src[1] is CONST:
404
if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
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/* Here we handle the special case of mov from
412
* CONST and/or RELATIV. These need to be handled
413
* specially, because in the case of move from CONST
414
* there is no src ir3_instruction so we need to
415
* replace the ir3_register. And in the case of
416
* RELATIV we need to handle the address register
419
if (src_reg->flags & IR3_REG_CONST) {
420
/* an instruction cannot reference two different
423
if ((src_reg->flags & IR3_REG_RELATIV) &&
424
conflicts(instr->address, reg->def->instr->address))
427
/* These macros expand to a mov in an if statement */
428
if ((src_reg->flags & IR3_REG_RELATIV) &&
429
is_subgroup_cond_mov_macro(instr))
432
/* This seems to be a hw bug, or something where the timings
433
* just somehow don't work out. This restriction may only
434
* apply if the first src is also CONST.
436
if ((opc_cat(instr->opc) == 3) && (n == 2) &&
437
(src_reg->flags & IR3_REG_RELATIV) && (src_reg->array.offset == 0))
440
/* When narrowing constant from 32b to 16b, it seems
441
* to work only for float. So we should do this only with
444
if (src->cat1.dst_type == TYPE_F16) {
445
/* TODO: should we have a way to tell phi/collect to use a
446
* float move so that this is legal?
450
if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
452
if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
454
} else if (src->cat1.dst_type == TYPE_U16) {
455
/* Since we set CONSTANT_DEMOTION_ENABLE, a float reference of
456
* what was a U16 value read from the constbuf would incorrectly
457
* do 32f->16f conversion, when we want to read a 16f value.
459
if (is_cat2_float(instr->opc) || is_cat3_float(instr->opc))
461
if (instr->opc == OPC_MOV && type_float(instr->cat1.src_type))
465
src_reg = ir3_reg_clone(instr->block->shader, src_reg);
466
src_reg->flags = new_flags;
467
instr->srcs[n] = src_reg;
469
if (src_reg->flags & IR3_REG_RELATIV)
470
ir3_instr_set_address(instr, reg->def->instr->address->def->instr);
475
if (src_reg->flags & IR3_REG_IMMED) {
476
int32_t iim_val = src_reg->iim_val;
478
debug_assert((opc_cat(instr->opc) == 1) ||
479
(opc_cat(instr->opc) == 2) ||
480
(opc_cat(instr->opc) == 6) ||
482
(is_mad(instr->opc) && (n == 0)));
484
if ((opc_cat(instr->opc) == 2) &&
485
!ir3_cat2_int(instr->opc)) {
486
iim_val = ir3_flut(src_reg);
488
/* Fall back to trying to load the immediate as a const: */
489
return lower_immed(ctx, instr, n, src_reg, new_flags);
493
if (new_flags & IR3_REG_SABS)
494
iim_val = abs(iim_val);
496
if (new_flags & IR3_REG_SNEG)
499
if (new_flags & IR3_REG_BNOT)
502
if (ir3_valid_flags(instr, n, new_flags) &&
503
ir3_valid_immediate(instr, iim_val)) {
504
new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
505
src_reg = ir3_reg_clone(instr->block->shader, src_reg);
506
src_reg->flags = new_flags;
507
src_reg->iim_val = iim_val;
508
instr->srcs[n] = src_reg;
512
/* Fall back to trying to load the immediate as a const: */
513
return lower_immed(ctx, instr, n, src_reg, new_flags);
521
/* Handle special case of eliminating output mov, and similar cases where
522
* there isn't a normal "consuming" instruction. In this case we cannot
523
* collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
526
static struct ir3_instruction *
527
eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
529
if (is_eligible_mov(instr, NULL, false)) {
530
struct ir3_register *reg = instr->srcs[0];
531
if (!(reg->flags & IR3_REG_ARRAY)) {
532
struct ir3_instruction *src_instr = ssa(reg);
533
debug_assert(src_instr);
534
ctx->progress = true;
542
* Find instruction src's which are mov's that can be collapsed, replacing
543
* the mov dst with the mov src
546
instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
548
if (instr->srcs_count == 0)
551
if (ir3_instr_check_mark(instr))
554
/* walk down the graph from each src: */
558
foreach_src_n (reg, n, instr) {
559
struct ir3_instruction *src = ssa(reg);
566
/* TODO non-indirect access we could figure out which register
567
* we actually want and allow cp..
569
if ((reg->flags & IR3_REG_ARRAY) && src->opc != OPC_META_PHI)
572
/* Don't CP absneg into meta instructions, that won't end well: */
573
if (is_meta(instr) &&
574
(src->opc == OPC_ABSNEG_F || src->opc == OPC_ABSNEG_S))
577
/* Don't CP mova and mova1 into their users */
578
if (writes_addr0(src) || writes_addr1(src))
581
progress |= reg_cp(ctx, instr, reg, n);
582
ctx->progress |= progress;
586
/* After folding a mov's source we may wind up with a type-converting mov
587
* of an immediate. This happens e.g. with texture descriptors, since we
588
* narrow the descriptor (which may be a constant) to a half-reg in ir3.
589
* By converting the immediate in-place to the destination type, we can
590
* turn the mov into a same-type mov so that it can be further propagated.
592
if (instr->opc == OPC_MOV && (instr->srcs[0]->flags & IR3_REG_IMMED) &&
593
instr->cat1.src_type != instr->cat1.dst_type &&
594
/* Only do uint types for now, until we generate other types of
595
* mov's during instruction selection.
597
full_type(instr->cat1.src_type) == TYPE_U32 &&
598
full_type(instr->cat1.dst_type) == TYPE_U32) {
599
uint32_t uimm = instr->srcs[0]->uim_val;
600
if (instr->cat1.dst_type == TYPE_U16)
602
instr->srcs[0]->uim_val = uimm;
603
if (instr->dsts[0]->flags & IR3_REG_HALF)
604
instr->srcs[0]->flags |= IR3_REG_HALF;
606
instr->srcs[0]->flags &= ~IR3_REG_HALF;
607
instr->cat1.src_type = instr->cat1.dst_type;
608
ctx->progress = true;
611
/* Re-write the instruction writing predicate register to get rid
612
* of the double cmps.
614
if ((instr->opc == OPC_CMPS_S) && is_foldable_double_cmp(instr)) {
615
struct ir3_instruction *cond = ssa(instr->srcs[0]);
620
instr->opc = cond->opc;
621
instr->flags = cond->flags;
622
instr->cat2 = cond->cat2;
624
ir3_instr_set_address(instr, cond->address->def->instr);
625
instr->srcs[0] = ir3_reg_clone(ctx->shader, cond->srcs[0]);
626
instr->srcs[1] = ir3_reg_clone(ctx->shader, cond->srcs[1]);
627
instr->barrier_class |= cond->barrier_class;
628
instr->barrier_conflict |= cond->barrier_conflict;
630
ctx->progress = true;
637
/* Handle converting a sam.s2en (taking samp/tex idx params via register)
638
* into a normal sam (encoding immediate samp/tex idx) if they are
639
* immediate. This saves some instructions and regs in the common case
640
* where we know samp/tex at compile time. This needs to be done in the
641
* frontend for bindless tex, though, so don't replicate it here.
643
if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
644
!(instr->flags & IR3_INSTR_B) &&
645
!(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
646
/* The first src will be a collect, if both of it's
647
* two sources are mov from imm, then we can
649
struct ir3_instruction *samp_tex = ssa(instr->srcs[0]);
651
debug_assert(samp_tex->opc == OPC_META_COLLECT);
653
struct ir3_register *samp = samp_tex->srcs[0];
654
struct ir3_register *tex = samp_tex->srcs[1];
656
if ((samp->flags & IR3_REG_IMMED) && (tex->flags & IR3_REG_IMMED) &&
657
(samp->iim_val < 16) && (tex->iim_val < 16)) {
658
instr->flags &= ~IR3_INSTR_S2EN;
659
instr->cat5.samp = samp->iim_val;
660
instr->cat5.tex = tex->iim_val;
662
/* shuffle around the regs to remove the first src: */
664
for (unsigned i = 0; i < instr->srcs_count; i++) {
665
instr->srcs[i] = instr->srcs[i + 1];
668
ctx->progress = true;
674
ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
676
struct ir3_cp_ctx ctx = {
681
/* This is a bit annoying, and probably wouldn't be necessary if we
682
* tracked a reverse link from producing instruction to consumer.
683
* But we need to know when we've eliminated the last consumer of
684
* a mov, so we need to do a pass to first count consumers of a
687
foreach_block (block, &ir->block_list) {
688
foreach_instr (instr, &block->instr_list) {
690
/* by the way, we don't account for false-dep's, so the CP
691
* pass should always happen before false-dep's are inserted
693
debug_assert(instr->deps_count == 0);
695
foreach_ssa_src (src, instr) {
703
foreach_block (block, &ir->block_list) {
704
if (block->condition) {
705
instr_cp(&ctx, block->condition);
706
block->condition = eliminate_output_mov(&ctx, block->condition);
709
for (unsigned i = 0; i < block->keeps_count; i++) {
710
instr_cp(&ctx, block->keeps[i]);
711
block->keeps[i] = eliminate_output_mov(&ctx, block->keeps[i]);