1
<?xml version="1.0" encoding="UTF-8"?>
2
<database xmlns="http://nouveau.freedesktop.org/"
3
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5
<import file="freedreno_copyright.xml"/>
6
<import file="adreno/adreno_common.xml"/>
7
<import file="adreno/adreno_pm4.xml"/>
9
<!-- these might be same as a5xx -->
10
<enum name="a6xx_tile_mode">
11
<value name="TILE6_LINEAR" value="0"/>
12
<value name="TILE6_2" value="2"/>
13
<value name="TILE6_3" value="3"/>
16
<enum name="a6xx_format">
17
<value value="0x02" name="FMT6_A8_UNORM"/>
18
<value value="0x03" name="FMT6_8_UNORM"/>
19
<value value="0x04" name="FMT6_8_SNORM"/>
20
<value value="0x05" name="FMT6_8_UINT"/>
21
<value value="0x06" name="FMT6_8_SINT"/>
23
<value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
24
<value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
25
<value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
26
<value value="0x0e" name="FMT6_5_6_5_UNORM"/>
28
<value value="0x0f" name="FMT6_8_8_UNORM"/>
29
<value value="0x10" name="FMT6_8_8_SNORM"/>
30
<value value="0x11" name="FMT6_8_8_UINT"/>
31
<value value="0x12" name="FMT6_8_8_SINT"/>
32
<value value="0x13" name="FMT6_L8_A8_UNORM"/>
34
<value value="0x15" name="FMT6_16_UNORM"/>
35
<value value="0x16" name="FMT6_16_SNORM"/>
36
<value value="0x17" name="FMT6_16_FLOAT"/>
37
<value value="0x18" name="FMT6_16_UINT"/>
38
<value value="0x19" name="FMT6_16_SINT"/>
40
<value value="0x21" name="FMT6_8_8_8_UNORM"/>
41
<value value="0x22" name="FMT6_8_8_8_SNORM"/>
42
<value value="0x23" name="FMT6_8_8_8_UINT"/>
43
<value value="0x24" name="FMT6_8_8_8_SINT"/>
45
<value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
46
<value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
47
<value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
48
<value value="0x33" name="FMT6_8_8_8_8_UINT"/>
49
<value value="0x34" name="FMT6_8_8_8_8_SINT"/>
51
<value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
53
<value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
54
<value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
55
<value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
56
<value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
57
<value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
59
<value value="0x42" name="FMT6_11_11_10_FLOAT"/>
61
<value value="0x43" name="FMT6_16_16_UNORM"/>
62
<value value="0x44" name="FMT6_16_16_SNORM"/>
63
<value value="0x45" name="FMT6_16_16_FLOAT"/>
64
<value value="0x46" name="FMT6_16_16_UINT"/>
65
<value value="0x47" name="FMT6_16_16_SINT"/>
67
<value value="0x48" name="FMT6_32_UNORM"/>
68
<value value="0x49" name="FMT6_32_SNORM"/>
69
<value value="0x4a" name="FMT6_32_FLOAT"/>
70
<value value="0x4b" name="FMT6_32_UINT"/>
71
<value value="0x4c" name="FMT6_32_SINT"/>
72
<value value="0x4d" name="FMT6_32_FIXED"/>
74
<value value="0x58" name="FMT6_16_16_16_UNORM"/>
75
<value value="0x59" name="FMT6_16_16_16_SNORM"/>
76
<value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
77
<value value="0x5b" name="FMT6_16_16_16_UINT"/>
78
<value value="0x5c" name="FMT6_16_16_16_SINT"/>
80
<value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
81
<value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
82
<value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
83
<value value="0x63" name="FMT6_16_16_16_16_UINT"/>
84
<value value="0x64" name="FMT6_16_16_16_16_SINT"/>
86
<value value="0x65" name="FMT6_32_32_UNORM"/>
87
<value value="0x66" name="FMT6_32_32_SNORM"/>
88
<value value="0x67" name="FMT6_32_32_FLOAT"/>
89
<value value="0x68" name="FMT6_32_32_UINT"/>
90
<value value="0x69" name="FMT6_32_32_SINT"/>
91
<value value="0x6a" name="FMT6_32_32_FIXED"/>
93
<value value="0x70" name="FMT6_32_32_32_UNORM"/>
94
<value value="0x71" name="FMT6_32_32_32_SNORM"/>
95
<value value="0x72" name="FMT6_32_32_32_UINT"/>
96
<value value="0x73" name="FMT6_32_32_32_SINT"/>
97
<value value="0x74" name="FMT6_32_32_32_FLOAT"/>
98
<value value="0x75" name="FMT6_32_32_32_FIXED"/>
100
<value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
101
<value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
102
<value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
103
<value value="0x83" name="FMT6_32_32_32_32_UINT"/>
104
<value value="0x84" name="FMT6_32_32_32_32_SINT"/>
105
<value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
107
<value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->
108
<value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->
109
<value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->
110
<value value="0x8f" name="FMT6_NV21"/>
111
<value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->
113
<value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
115
<!-- Note: tiling/UBWC for these may be different from equivalent formats
116
For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM
118
<value value="0x94" name="FMT6_NV12_Y"/>
119
<value value="0x95" name="FMT6_NV12_UV"/>
120
<value value="0x96" name="FMT6_NV12_VU"/>
121
<value value="0x97" name="FMT6_NV12_4R"/>
122
<value value="0x98" name="FMT6_NV12_4R_Y"/>
123
<value value="0x99" name="FMT6_NV12_4R_UV"/>
124
<value value="0x9a" name="FMT6_P010"/>
125
<value value="0x9b" name="FMT6_P010_Y"/>
126
<value value="0x9c" name="FMT6_P010_UV"/>
127
<value value="0x9d" name="FMT6_TP10"/>
128
<value value="0x9e" name="FMT6_TP10_Y"/>
129
<value value="0x9f" name="FMT6_TP10_UV"/>
131
<value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
133
<value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
134
<value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
135
<value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
136
<value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
137
<value value="0xaf" name="FMT6_ETC1"/>
138
<value value="0xb0" name="FMT6_ETC2_RGB8"/>
139
<value value="0xb1" name="FMT6_ETC2_RGBA8"/>
140
<value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
141
<value value="0xb3" name="FMT6_DXT1"/>
142
<value value="0xb4" name="FMT6_DXT3"/>
143
<value value="0xb5" name="FMT6_DXT5"/>
144
<value value="0xb7" name="FMT6_RGTC1_UNORM"/>
145
<value value="0xb8" name="FMT6_RGTC1_SNORM"/>
146
<value value="0xbb" name="FMT6_RGTC2_UNORM"/>
147
<value value="0xbc" name="FMT6_RGTC2_SNORM"/>
148
<value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
149
<value value="0xbf" name="FMT6_BPTC_FLOAT"/>
150
<value value="0xc0" name="FMT6_BPTC"/>
151
<value value="0xc1" name="FMT6_ASTC_4x4"/>
152
<value value="0xc2" name="FMT6_ASTC_5x4"/>
153
<value value="0xc3" name="FMT6_ASTC_5x5"/>
154
<value value="0xc4" name="FMT6_ASTC_6x5"/>
155
<value value="0xc5" name="FMT6_ASTC_6x6"/>
156
<value value="0xc6" name="FMT6_ASTC_8x5"/>
157
<value value="0xc7" name="FMT6_ASTC_8x6"/>
158
<value value="0xc8" name="FMT6_ASTC_8x8"/>
159
<value value="0xc9" name="FMT6_ASTC_10x5"/>
160
<value value="0xca" name="FMT6_ASTC_10x6"/>
161
<value value="0xcb" name="FMT6_ASTC_10x8"/>
162
<value value="0xcc" name="FMT6_ASTC_10x10"/>
163
<value value="0xcd" name="FMT6_ASTC_12x10"/>
164
<value value="0xce" name="FMT6_ASTC_12x12"/>
166
<!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
167
<value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/>
169
<!-- Not a hw enum, used internally in driver -->
170
<value value="0xff" name="FMT6_NONE"/>
174
<!-- probably same as a5xx -->
175
<enum name="a6xx_polygon_mode">
176
<value name="POLYMODE6_POINTS" value="1"/>
177
<value name="POLYMODE6_LINES" value="2"/>
178
<value name="POLYMODE6_TRIANGLES" value="3"/>
181
<enum name="a6xx_depth_format">
182
<value name="DEPTH6_NONE" value="0"/>
183
<value name="DEPTH6_16" value="1"/>
184
<value name="DEPTH6_24_8" value="2"/>
185
<value name="DEPTH6_32" value="4"/>
188
<bitset name="a6x_cp_protect" inline="yes">
189
<bitfield name="BASE_ADDR" low="0" high="17"/>
190
<bitfield name="MASK_LEN" low="18" high="30"/>
191
<bitfield name="READ" pos="31" type="boolean"/>
194
<enum name="a6xx_shader_id">
195
<value value="0x9" name="A6XX_TP0_TMO_DATA"/>
196
<value value="0xa" name="A6XX_TP0_SMO_DATA"/>
197
<value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
198
<value value="0x19" name="A6XX_TP1_TMO_DATA"/>
199
<value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
200
<value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
201
<value value="0x29" name="A6XX_SP_INST_DATA"/>
202
<value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
203
<value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
204
<value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
205
<value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
206
<value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
207
<value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
208
<value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
209
<value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
210
<value value="0x32" name="A6XX_SP_UAV_DATA"/>
211
<value value="0x33" name="A6XX_SP_INST_TAG"/>
212
<value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
213
<value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
214
<value value="0x36" name="A6XX_SP_SMO_TAG"/>
215
<value value="0x37" name="A6XX_SP_STATE_DATA"/>
216
<value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
217
<value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
218
<value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
219
<value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
220
<value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
221
<value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
222
<value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
223
<value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
224
<value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
225
<value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
226
<value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
227
<value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
228
<value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
229
<value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
230
<value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
231
<value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
232
<value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
233
<value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
234
<value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
235
<value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
236
<value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
237
<value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
240
<enum name="a6xx_debugbus_id">
241
<value value="0x1" name="A6XX_DBGBUS_CP"/>
242
<value value="0x2" name="A6XX_DBGBUS_RBBM"/>
243
<value value="0x3" name="A6XX_DBGBUS_VBIF"/>
244
<value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
245
<value value="0x5" name="A6XX_DBGBUS_UCHE"/>
246
<value value="0x6" name="A6XX_DBGBUS_DPM"/>
247
<value value="0x7" name="A6XX_DBGBUS_TESS"/>
248
<value value="0x8" name="A6XX_DBGBUS_PC"/>
249
<value value="0x9" name="A6XX_DBGBUS_VFDP"/>
250
<value value="0xa" name="A6XX_DBGBUS_VPC"/>
251
<value value="0xb" name="A6XX_DBGBUS_TSE"/>
252
<value value="0xc" name="A6XX_DBGBUS_RAS"/>
253
<value value="0xd" name="A6XX_DBGBUS_VSC"/>
254
<value value="0xe" name="A6XX_DBGBUS_COM"/>
255
<value value="0x10" name="A6XX_DBGBUS_LRZ"/>
256
<value value="0x11" name="A6XX_DBGBUS_A2D"/>
257
<value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
258
<value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
259
<value value="0x14" name="A6XX_DBGBUS_RBP"/>
260
<value value="0x15" name="A6XX_DBGBUS_DCS"/>
261
<value value="0x16" name="A6XX_DBGBUS_DBGC"/>
262
<value value="0x17" name="A6XX_DBGBUS_CX"/>
263
<value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
264
<value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
265
<value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
266
<value value="0x1d" name="A6XX_DBGBUS_GPC"/>
267
<value value="0x1e" name="A6XX_DBGBUS_LARC"/>
268
<value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
269
<value value="0x20" name="A6XX_DBGBUS_RB_0"/>
270
<value value="0x21" name="A6XX_DBGBUS_RB_1"/>
271
<value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
272
<value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
273
<value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
274
<value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
275
<value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
276
<value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
277
<value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
278
<value value="0x40" name="A6XX_DBGBUS_SP_0"/>
279
<value value="0x41" name="A6XX_DBGBUS_SP_1"/>
280
<value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
281
<value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
282
<value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
283
<value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
286
<enum name="a6xx_cp_perfcounter_select">
287
<value value="0" name="PERF_CP_ALWAYS_COUNT"/>
288
<value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
289
<value value="2" name="PERF_CP_BUSY_CYCLES"/>
290
<value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
291
<value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
292
<value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
293
<value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
294
<value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
295
<value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
296
<value value="9" name="PERF_CP_MODE_SWITCH"/>
297
<value value="10" name="PERF_CP_ZPASS_DONE"/>
298
<value value="11" name="PERF_CP_CONTEXT_DONE"/>
299
<value value="12" name="PERF_CP_CACHE_FLUSH"/>
300
<value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
301
<value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
302
<value value="15" name="PERF_CP_SQE_IDLE"/>
303
<value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
304
<value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
305
<value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
306
<value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
307
<value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
308
<value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
309
<value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
310
<value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
311
<value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
312
<value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
313
<value value="26" name="PERF_CP_SQE_T4_EXEC"/>
314
<value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
315
<value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
316
<value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
317
<value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
318
<value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
319
<value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
320
<value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
321
<value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
322
<value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
323
<value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
324
<value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
325
<value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
326
<value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
327
<value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
328
<value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
329
<value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
330
<value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
331
<value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
332
<value value="45" name="PERF_CP_PM4_DATA"/>
333
<value value="46" name="PERF_CP_PM4_HEADERS"/>
334
<value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
335
<value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
336
<value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
339
<enum name="a6xx_rbbm_perfcounter_select">
340
<value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
341
<value value="1" name="PERF_RBBM_ALWAYS_ON"/>
342
<value value="2" name="PERF_RBBM_TSE_BUSY"/>
343
<value value="3" name="PERF_RBBM_RAS_BUSY"/>
344
<value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
345
<value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
346
<value value="6" name="PERF_RBBM_STATUS_MASKED"/>
347
<value value="7" name="PERF_RBBM_COM_BUSY"/>
348
<value value="8" name="PERF_RBBM_DCOM_BUSY"/>
349
<value value="9" name="PERF_RBBM_VBIF_BUSY"/>
350
<value value="10" name="PERF_RBBM_VSC_BUSY"/>
351
<value value="11" name="PERF_RBBM_TESS_BUSY"/>
352
<value value="12" name="PERF_RBBM_UCHE_BUSY"/>
353
<value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
356
<enum name="a6xx_pc_perfcounter_select">
357
<value value="0" name="PERF_PC_BUSY_CYCLES"/>
358
<value value="1" name="PERF_PC_WORKING_CYCLES"/>
359
<value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
360
<value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
361
<value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
362
<value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
363
<value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
364
<value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
365
<value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
366
<value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
367
<value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
368
<value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
369
<value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
370
<value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
371
<value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
372
<value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
373
<value value="16" name="PERF_PC_INSTANCES"/>
374
<value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
375
<value value="18" name="PERF_PC_DEAD_PRIM"/>
376
<value value="19" name="PERF_PC_LIVE_PRIM"/>
377
<value value="20" name="PERF_PC_VERTEX_HITS"/>
378
<value value="21" name="PERF_PC_IA_VERTICES"/>
379
<value value="22" name="PERF_PC_IA_PRIMITIVES"/>
380
<value value="23" name="PERF_PC_GS_PRIMITIVES"/>
381
<value value="24" name="PERF_PC_HS_INVOCATIONS"/>
382
<value value="25" name="PERF_PC_DS_INVOCATIONS"/>
383
<value value="26" name="PERF_PC_VS_INVOCATIONS"/>
384
<value value="27" name="PERF_PC_GS_INVOCATIONS"/>
385
<value value="28" name="PERF_PC_DS_PRIMITIVES"/>
386
<value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
387
<value value="30" name="PERF_PC_3D_DRAWCALLS"/>
388
<value value="31" name="PERF_PC_2D_DRAWCALLS"/>
389
<value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
390
<value value="33" name="PERF_TESS_BUSY_CYCLES"/>
391
<value value="34" name="PERF_TESS_WORKING_CYCLES"/>
392
<value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
393
<value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
394
<value value="37" name="PERF_PC_TSE_TRANSACTION"/>
395
<value value="38" name="PERF_PC_TSE_VERTEX"/>
396
<value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
397
<value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
398
<value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
401
<enum name="a6xx_vfd_perfcounter_select">
402
<value value="0" name="PERF_VFD_BUSY_CYCLES"/>
403
<value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
404
<value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
405
<value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
406
<value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
407
<value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
408
<value value="6" name="PERF_VFD_RBUFFER_FULL"/>
409
<value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
410
<value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
411
<value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
412
<value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
413
<value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
414
<value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
415
<value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
416
<value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
417
<value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
418
<value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
419
<value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
420
<value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
421
<value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
422
<value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
423
<value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
424
<value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
427
<enum name="a6xx_hlsq_perfcounter_select">
428
<value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
429
<value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
430
<value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
431
<value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
432
<value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
433
<value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
434
<value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
435
<value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
436
<value value="8" name="PERF_HLSQ_QUADS"/>
437
<value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
438
<value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
439
<value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
440
<value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
441
<value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
442
<value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
443
<value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
444
<value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
445
<value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
446
<value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
447
<value value="19" name="PERF_HLSQ_PIXELS"/>
448
<value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
451
<enum name="a6xx_vpc_perfcounter_select">
452
<value value="0" name="PERF_VPC_BUSY_CYCLES"/>
453
<value value="1" name="PERF_VPC_WORKING_CYCLES"/>
454
<value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
455
<value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
456
<value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
457
<value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
458
<value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
459
<value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
460
<value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
461
<value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
462
<value value="10" name="PERF_VPC_SP_COMPONENTS"/>
463
<value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
464
<value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
465
<value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
466
<value value="14" name="PERF_VPC_LM_TRANSACTION"/>
467
<value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
468
<value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
469
<value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
470
<value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
471
<value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
472
<value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
473
<value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
474
<value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
475
<value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
476
<value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
477
<value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
478
<value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
479
<value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
482
<enum name="a6xx_tse_perfcounter_select">
483
<value value="0" name="PERF_TSE_BUSY_CYCLES"/>
484
<value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
485
<value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
486
<value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
487
<value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
488
<value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
489
<value value="6" name="PERF_TSE_INPUT_PRIM"/>
490
<value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
491
<value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
492
<value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
493
<value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
494
<value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
495
<value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
496
<value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
497
<value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
498
<value value="15" name="PERF_TSE_CINVOCATION"/>
499
<value value="16" name="PERF_TSE_CPRIMITIVES"/>
500
<value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
501
<value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
502
<value value="19" name="PERF_TSE_CLIP_PLANES"/>
505
<enum name="a6xx_ras_perfcounter_select">
506
<value value="0" name="PERF_RAS_BUSY_CYCLES"/>
507
<value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
508
<value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
509
<value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
510
<value value="4" name="PERF_RAS_SUPER_TILES"/>
511
<value value="5" name="PERF_RAS_8X4_TILES"/>
512
<value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
513
<value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
514
<value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
515
<value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
516
<value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
517
<value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
518
<value value="12" name="PERF_RAS_BLOCKS"/>
521
<enum name="a6xx_uche_perfcounter_select">
522
<value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
523
<value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
524
<value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
525
<value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
526
<value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
527
<value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
528
<value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
529
<value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
530
<value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
531
<value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
532
<value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
533
<value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
534
<value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
535
<value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
536
<value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
537
<value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
538
<value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
539
<value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
540
<value value="18" name="PERF_UCHE_EVICTS"/>
541
<value value="19" name="PERF_UCHE_BANK_REQ0"/>
542
<value value="20" name="PERF_UCHE_BANK_REQ1"/>
543
<value value="21" name="PERF_UCHE_BANK_REQ2"/>
544
<value value="22" name="PERF_UCHE_BANK_REQ3"/>
545
<value value="23" name="PERF_UCHE_BANK_REQ4"/>
546
<value value="24" name="PERF_UCHE_BANK_REQ5"/>
547
<value value="25" name="PERF_UCHE_BANK_REQ6"/>
548
<value value="26" name="PERF_UCHE_BANK_REQ7"/>
549
<value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
550
<value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
551
<value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
552
<value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
553
<value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
554
<value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
555
<value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
556
<value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
557
<value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
558
<value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
559
<value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
560
<value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
561
<value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
564
<enum name="a6xx_tp_perfcounter_select">
565
<value value="0" name="PERF_TP_BUSY_CYCLES"/>
566
<value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
567
<value value="2" name="PERF_TP_LATENCY_CYCLES"/>
568
<value value="3" name="PERF_TP_LATENCY_TRANS"/>
569
<value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
570
<value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
571
<value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
572
<value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
573
<value value="8" name="PERF_TP_SP_TP_TRANS"/>
574
<value value="9" name="PERF_TP_TP_SP_TRANS"/>
575
<value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
576
<value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
577
<value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
578
<value value="13" name="PERF_TP_QUADS_RECEIVED"/>
579
<value value="14" name="PERF_TP_QUADS_OFFSET"/>
580
<value value="15" name="PERF_TP_QUADS_SHADOW"/>
581
<value value="16" name="PERF_TP_QUADS_ARRAY"/>
582
<value value="17" name="PERF_TP_QUADS_GRADIENT"/>
583
<value value="18" name="PERF_TP_QUADS_1D"/>
584
<value value="19" name="PERF_TP_QUADS_2D"/>
585
<value value="20" name="PERF_TP_QUADS_BUFFER"/>
586
<value value="21" name="PERF_TP_QUADS_3D"/>
587
<value value="22" name="PERF_TP_QUADS_CUBE"/>
588
<value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
589
<value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
590
<value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
591
<value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
592
<value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
593
<value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
594
<value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
595
<value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
596
<value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
597
<value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
598
<value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
599
<value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
600
<value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
601
<value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
602
<value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
603
<value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
604
<value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
605
<value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
606
<value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
607
<value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
608
<value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
609
<value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
610
<value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
611
<value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
612
<value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
613
<value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
614
<value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
615
<value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
616
<value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
617
<value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
618
<value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
619
<value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
620
<value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
621
<value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
624
<enum name="a6xx_sp_perfcounter_select">
625
<value value="0" name="PERF_SP_BUSY_CYCLES"/>
626
<value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
627
<value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
628
<value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
629
<value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
630
<value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
631
<value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
632
<value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
633
<value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
634
<value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
635
<value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
636
<value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
637
<value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
638
<value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
639
<value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
640
<value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
641
<value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
642
<value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
643
<value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
644
<value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
645
<value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
646
<value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
647
<value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
648
<value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
649
<value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
650
<value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
651
<value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
652
<value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
653
<value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
654
<value value="29" name="PERF_SP_LM_ATOMICS"/>
655
<value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
656
<value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
657
<value value="32" name="PERF_SP_GM_ATOMICS"/>
658
<value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
659
<value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
660
<value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
661
<value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
662
<value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
663
<value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
664
<value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
665
<value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
666
<value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
667
<value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
668
<value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
669
<value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
670
<value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
671
<value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
672
<value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
673
<value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
674
<value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
675
<value value="50" name="PERF_SP_PIXELS_KILLED"/>
676
<value value="51" name="PERF_SP_ICL1_REQUESTS"/>
677
<value value="52" name="PERF_SP_ICL1_MISSES"/>
678
<value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
679
<value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
680
<value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
681
<value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
682
<value value="57" name="PERF_SP_GPR_READ"/>
683
<value value="58" name="PERF_SP_GPR_WRITE"/>
684
<value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
685
<value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
686
<value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
687
<value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
688
<value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
689
<value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
690
<value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
691
<value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
692
<value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
693
<value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
694
<value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
695
<value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
696
<value value="71" name="PERF_SP_WORKING_EU"/>
697
<value value="72" name="PERF_SP_ANY_EU_WORKING"/>
698
<value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
699
<value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
700
<value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
701
<value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
702
<value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
703
<value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
704
<value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
705
<value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
706
<value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
707
<value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
708
<value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
709
<value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
712
<enum name="a6xx_rb_perfcounter_select">
713
<value value="0" name="PERF_RB_BUSY_CYCLES"/>
714
<value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
715
<value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
716
<value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
717
<value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
718
<value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
719
<value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
720
<value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
721
<value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
722
<value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
723
<value value="10" name="PERF_RB_Z_WORKLOAD"/>
724
<value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
725
<value value="12" name="PERF_RB_Z_READ"/>
726
<value value="13" name="PERF_RB_Z_WRITE"/>
727
<value value="14" name="PERF_RB_C_READ"/>
728
<value value="15" name="PERF_RB_C_WRITE"/>
729
<value value="16" name="PERF_RB_TOTAL_PASS"/>
730
<value value="17" name="PERF_RB_Z_PASS"/>
731
<value value="18" name="PERF_RB_Z_FAIL"/>
732
<value value="19" name="PERF_RB_S_FAIL"/>
733
<value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
734
<value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
735
<value value="22" name="PERF_RB_PS_INVOCATIONS"/>
736
<value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
737
<value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
738
<value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
739
<value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
740
<value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
741
<value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
742
<value value="29" name="PERF_RB_3D_PIXELS"/>
743
<value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
744
<value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
745
<value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
746
<value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
747
<value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
748
<value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
749
<value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
750
<value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
751
<value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
752
<value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
753
<value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
754
<value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
755
<value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
756
<value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
757
<value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
758
<value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
759
<value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
760
<value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
763
<enum name="a6xx_vsc_perfcounter_select">
764
<value value="0" name="PERF_VSC_BUSY_CYCLES"/>
765
<value value="1" name="PERF_VSC_WORKING_CYCLES"/>
766
<value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
767
<value value="3" name="PERF_VSC_EOT_NUM"/>
768
<value value="4" name="PERF_VSC_INPUT_TILES"/>
771
<enum name="a6xx_ccu_perfcounter_select">
772
<value value="0" name="PERF_CCU_BUSY_CYCLES"/>
773
<value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
774
<value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
775
<value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
776
<value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
777
<value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
778
<value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
779
<value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
780
<value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
781
<value value="9" name="PERF_CCU_GMEM_READ"/>
782
<value value="10" name="PERF_CCU_GMEM_WRITE"/>
783
<value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
784
<value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
785
<value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
786
<value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
787
<value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
788
<value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
789
<value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
790
<value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
791
<value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
792
<value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
793
<value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
794
<value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
795
<value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
796
<value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
797
<value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
798
<value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
799
<value value="27" name="PERF_CCU_2D_RD_REQ"/>
800
<value value="28" name="PERF_CCU_2D_WR_REQ"/>
803
<enum name="a6xx_lrz_perfcounter_select">
804
<value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
805
<value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
806
<value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
807
<value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
808
<value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
809
<value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
810
<value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
811
<value value="7" name="PERF_LRZ_LRZ_READ"/>
812
<value value="8" name="PERF_LRZ_LRZ_WRITE"/>
813
<value value="9" name="PERF_LRZ_READ_LATENCY"/>
814
<value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
815
<value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
816
<value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
817
<value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
818
<value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
819
<value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
820
<value value="16" name="PERF_LRZ_TILE_KILLED"/>
821
<value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
822
<value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
823
<value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
824
<value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
825
<value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
826
<value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
827
<value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
828
<value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
829
<value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
830
<value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
831
<value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
834
<enum name="a6xx_cmp_perfcounter_select">
835
<value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
836
<value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
837
<value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
838
<value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
839
<value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
840
<value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
841
<value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
842
<value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
843
<value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
844
<value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
845
<value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
846
<value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
847
<value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
848
<value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
849
<value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
850
<value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
851
<value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
852
<value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
853
<value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
854
<value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
855
<value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
856
<value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
857
<value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
858
<value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
859
<value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
860
<value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
861
<value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
862
<value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
863
<value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
864
<value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
865
<value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
866
<value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
867
<value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
868
<value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
869
<value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
870
<value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
871
<value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
872
<value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
873
<value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
874
<value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
878
Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
879
component type/size, so I think it relates to internal format used for
880
blending? The one exception is that 16b unorm and 32b float use the
881
same value... maybe 16b unorm is uncommon enough that it was just easier
882
to upconvert to 32b float internally?
884
8b unorm: 10 (sometimes 0, is the high bit part of something else?)
894
<enum name="a6xx_2d_ifmt">
895
<value value="0x10" name="R2D_UNORM8"/>
896
<value value="0x7" name="R2D_INT32"/>
897
<value value="0x6" name="R2D_INT16"/>
898
<value value="0x5" name="R2D_INT8"/>
899
<value value="0x4" name="R2D_FLOAT32"/>
900
<value value="0x3" name="R2D_FLOAT16"/>
901
<value value="0x1" name="R2D_UNORM8_SRGB"/>
902
<value value="0x0" name="R2D_RAW"/>
905
<enum name="a6xx_ztest_mode">
906
<doc>Allow early z-test and early-lrz (if applicable)</doc>
907
<value value="0x0" name="A6XX_EARLY_Z"/>
908
<doc>Disable early z-test and early-lrz test (if applicable)</doc>
909
<value value="0x1" name="A6XX_LATE_Z"/>
911
A special mode that allows early-lrz test but disables
912
early-z test. Which might sound a bit funny, since
913
lrz-test happens before z-test. But as long as a couple
914
conditions are maintained this allows using lrz-test in
915
cases where fragment shader has kill/discard:
917
1) Disable lrz-write in cases where it is uncertain during
918
binning pass that a fragment will pass. Ie. if frag
919
shader has-kill, writes-z, or alpha/stencil test is
920
enabled. (For correctness, lrz-write must be disabled
921
when blend is enabled.) This is analogous to how a
924
2) Disable lrz-write and test if a depth-test direction
925
reversal is detected. Due to condition (1), the contents
926
of the lrz buffer are a conservative estimation of the
927
depth buffer during the draw pass. Meaning that geometry
928
that we know for certain will not be visible will not pass
929
lrz-test. But geometry which may be (or contributes to
930
blend) will pass the lrz-test.
932
This allows us to keep early-lrz-test in cases where the frag
933
shader does not write-z (ie. we know the z-value before FS)
934
and does not have side-effects (image/ssbo writes, etc), but
935
does have kill/discard. Which turns out to be a common
936
enough case that it is useful to keep early-lrz test against
937
the conservative lrz buffer to discard fragments that we
938
know will definitely not be visible.
940
<value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>
943
<domain name="A6XX" width="32">
944
<bitset name="A6XX_RBBM_INT_0_MASK" inline="no">
945
<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
946
<bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
947
<bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
948
<bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
949
<bitfield name="CP_SW" pos="8" type="boolean"/>
950
<bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
951
<bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
952
<bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
953
<bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
954
<bitfield name="CP_IB2" pos="13" type="boolean"/>
955
<bitfield name="CP_IB1" pos="14" type="boolean"/>
956
<bitfield name="CP_RB" pos="15" type="boolean"/>
957
<bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
958
<bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
959
<bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
960
<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
961
<bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/>
962
<bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
963
<bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
964
<bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
965
<bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
966
<bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
967
<bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
970
<bitset name="A6XX_CP_INT">
971
<bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
972
<bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/>
973
<bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
974
<bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
975
<bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
976
<bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/>
977
<bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/>
980
<reg32 offset="0x0800" name="CP_RB_BASE"/>
981
<reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
982
<reg32 offset="0x0802" name="CP_RB_CNTL"/>
983
<reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
984
<reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
985
<reg32 offset="0x0806" name="CP_RB_RPTR"/>
986
<reg32 offset="0x0807" name="CP_RB_WPTR"/>
987
<reg32 offset="0x0808" name="CP_SQE_CNTL"/>
988
<reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
989
<bitfield name="IFPC" pos="0" type="boolean"/>
991
<reg32 offset="0x0821" name="CP_HW_FAULT"/>
992
<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
993
<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
994
<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
995
<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
996
<reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
997
<!-- all the threshold values seem to be in units of quad-dwords: -->
998
<reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
1000
b0..7 seems to contain the size of buffered by not yet processed
1001
RB level cmdstream.. it's possible that it is a low threshold
1002
and b8..15 is a high threshold?
1004
b16..23 identifies where IB1 data starts (and RB data ends?)
1006
b24..31 identifies where IB2 data starts (and IB1 data ends)
1008
<bitfield name="RB_LO" low="0" high="7" shr="2"/>
1009
<bitfield name="RB_HI" low="8" high="15" shr="2"/>
1010
<bitfield name="IB1_START" low="16" high="23" shr="2"/>
1011
<bitfield name="IB2_START" low="24" high="31" shr="2"/>
1013
<reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
1015
low bits identify where CP_SET_DRAW_STATE stateobj
1016
processing starts (and IB2 data ends). I'm guessing
1017
b8 is part of this since (from downstream kgsl):
1019
/* ROQ sizes are twice as big on a640/a680 than on a630 */
1020
if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
1021
kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
1022
kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
1025
<bitfield name="SDS_START" low="0" high="8" shr="2"/>
1026
<!-- total ROQ size: -->
1027
<bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
1029
<reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
1030
<reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
1031
<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1032
<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
1033
<reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
1035
<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
1036
<reg32 offset="0x0" name="REG" type="uint"/>
1038
<array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
1039
<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
1042
<reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
1043
<reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
1044
<reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
1045
<reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
1046
<reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
1047
<reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
1048
<reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
1049
<reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
1050
<reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
1051
<array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
1052
<reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1053
<reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1054
<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1055
<reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1056
<reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1057
<reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1058
<reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1059
<reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1060
<reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1061
<reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1062
<reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1063
<reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1064
<reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1065
<reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1066
<reg32 offset="0x0928" name="CP_IB1_BASE"/>
1067
<reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1068
<reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1069
<reg32 offset="0x092B" name="CP_IB2_BASE"/>
1070
<reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1071
<reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1072
<!-- SDS == CP_SET_DRAW_STATE: -->
1073
<reg32 offset="0x092e" name="CP_SDS_BASE"/>
1074
<reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
1075
<reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>
1076
<!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
1077
<reg32 offset="0x0931" name="CP_MRB_BASE"/>
1078
<reg32 offset="0x0932" name="CP_MRB_BASE_HI"/>
1079
<reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>
1081
VSD == Visibility Stream Decode
1082
This is used by CP to read the draw stream and skip empty draws
1084
<reg32 offset="0x0934" name="CP_VSD_BASE"/>
1085
<reg32 offset="0x0935" name="CP_VSD_BASE_HI"/>
1086
<reg32 offset="0x0946" name="CP_MRB_DWORDS"/>
1087
<reg32 offset="0x0947" name="CP_VSD_DWORDS"/>
1089
There are probably similar registers for RB and SDS, teasing out SDS will
1090
take a slightly better test case..
1092
<reg32 offset="0x0949" name="CP_CSQ_IB1_STAT">
1093
<doc>number of remaining dwords incl current dword being consumed?</doc>
1094
<bitfield name="REM" low="16" high="31"/>
1096
<reg32 offset="0x094a" name="CP_CSQ_IB2_STAT">
1097
<doc>number of remaining dwords incl current dword being consumed?</doc>
1098
<bitfield name="REM" low="16" high="31"/>
1100
<reg32 offset="0x094c" name="CP_MRQ_MRB_STAT">
1101
<doc>number of dwords that have already been read but haven't been consumed by $addr</doc>
1102
<bitfield name="REM" low="16" high="31"/>
1104
<reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1105
<reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1106
<reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1107
<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1108
<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1109
<reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
1110
<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
1111
<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1112
<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
1113
<reg32 offset="0x0210" name="RBBM_STATUS">
1114
<bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>
1115
<bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>
1116
<bitfield pos="21" name="HLSQ_BUSY" type="boolean"/>
1117
<bitfield pos="20" name="VSC_BUSY" type="boolean"/>
1118
<bitfield pos="19" name="TPL1_BUSY" type="boolean"/>
1119
<bitfield pos="18" name="SP_BUSY" type="boolean"/>
1120
<bitfield pos="17" name="UCHE_BUSY" type="boolean"/>
1121
<bitfield pos="16" name="VPC_BUSY" type="boolean"/>
1122
<bitfield pos="15" name="VFD_BUSY" type="boolean"/>
1123
<bitfield pos="14" name="TESS_BUSY" type="boolean"/>
1124
<bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/>
1125
<bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/>
1126
<bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/>
1127
<bitfield pos="10" name="LRZ_BUSY" type="boolean"/>
1128
<bitfield pos="9" name="A2D_BUSY" type="boolean"/>
1129
<bitfield pos="8" name="CCU_BUSY" type="boolean"/>
1130
<bitfield pos="7" name="RB_BUSY" type="boolean"/>
1131
<bitfield pos="6" name="RAS_BUSY" type="boolean"/>
1132
<bitfield pos="5" name="TSE_BUSY" type="boolean"/>
1133
<bitfield pos="4" name="VBIF_BUSY" type="boolean"/>
1134
<bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/>
1135
<bitfield pos="2" name="CP_BUSY" type="boolean"/>
1136
<bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
1137
<bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
1139
<reg32 offset="0x0213" name="RBBM_STATUS3">
1140
<bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
1142
<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1143
<array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14"/>
1144
<array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4"/>
1145
<array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8"/>
1146
<array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8"/>
1147
<array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6"/>
1148
<array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6"/>
1149
<array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5"/>
1150
<array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4"/>
1151
<array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4"/>
1152
<array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12"/>
1153
<array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12"/>
1154
<array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24"/>
1155
<array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8"/>
1156
<array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2"/>
1157
<array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4"/>
1158
<array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4"/>
1159
<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1160
<reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1161
<reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1162
<reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1163
<reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1164
<reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1165
<reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1166
<array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
1167
<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1168
<reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/>
1169
<reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/>
1170
<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1173
This block of registers aren't tied to perf counters. They
1174
count various geometry stats, for example number of
1175
vertices in, number of primnitives assembled etc.
1178
<reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
1179
<reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1180
<reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
1181
<reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1182
<reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
1183
<reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1184
<reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
1185
<reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1186
<reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
1187
<reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1188
<reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
1189
<reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1190
<reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
1191
<reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1192
<reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
1193
<reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1194
<reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
1195
<reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1196
<reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
1197
<reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1198
<reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1199
<reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1201
<reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1202
<reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1203
<reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1204
<reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1205
<reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1206
<reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1207
<reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1208
<reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
1209
<reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
1210
<bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
1212
<reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1213
<reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
1214
<reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1215
<reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1216
<reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1217
<reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1218
<reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1219
<reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1220
<reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1221
<reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1222
<reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1223
<reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1224
<reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1225
<reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1226
<reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1227
<reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1228
<reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1229
<reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1230
<reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1231
<reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1232
<reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1233
<reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1234
<reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1235
<reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1236
<reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1237
<reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1238
<reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1239
<reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1240
<reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1241
<reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1242
<reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1243
<reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1244
<reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1245
<reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1246
<reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1247
<reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1248
<reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1249
<reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1250
<reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1251
<reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1252
<reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1253
<reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1254
<reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1255
<reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1256
<reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1257
<reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1258
<reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1259
<reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1260
<reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1261
<reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1262
<reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1263
<reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1264
<reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1265
<reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1266
<reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1267
<reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1268
<reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1269
<reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1270
<reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1271
<reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1272
<reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1273
<reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1274
<reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1275
<reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1276
<reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1277
<reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1278
<reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1279
<reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1280
<reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1281
<reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1282
<reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1283
<reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1284
<reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1285
<reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1286
<reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1287
<reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1288
<reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1289
<reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1290
<reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1291
<reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1292
<reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1293
<reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1294
<reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1295
<reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1296
<reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1297
<reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1298
<reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1299
<reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1300
<reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1301
<reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1302
<reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1303
<reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1304
<reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1305
<reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1306
<reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1307
<reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1308
<reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1309
<reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1310
<reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1311
<reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1312
<reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1313
<reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1314
<reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1315
<reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1316
<reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1317
<reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1318
<reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1319
<reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1320
<reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1321
<reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1322
<reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1323
<reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1324
<reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1325
<reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1326
<reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>
1327
<reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
1328
<reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
1329
<reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/>
1331
<reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1332
<reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1333
<reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1334
<reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1335
<bitfield high="7" low="0" name="PING_INDEX"/>
1336
<bitfield high="15" low="8" name="PING_BLK_SEL"/>
1338
<reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1339
<bitfield high="5" low="0" name="TRACEEN"/>
1340
<bitfield high="14" low="12" name="GRANU"/>
1341
<bitfield high="31" low="28" name="SEGT"/>
1343
<reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1344
<bitfield high="27" low="24" name="ENABLE"/>
1346
<reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1347
<reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1348
<reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1349
<reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1350
<reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1351
<reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1352
<reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1353
<reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1354
<reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1355
<bitfield high="3" low="0" name="BYTEL0"/>
1356
<bitfield high="7" low="4" name="BYTEL1"/>
1357
<bitfield high="11" low="8" name="BYTEL2"/>
1358
<bitfield high="15" low="12" name="BYTEL3"/>
1359
<bitfield high="19" low="16" name="BYTEL4"/>
1360
<bitfield high="23" low="20" name="BYTEL5"/>
1361
<bitfield high="27" low="24" name="BYTEL6"/>
1362
<bitfield high="31" low="28" name="BYTEL7"/>
1364
<reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1365
<bitfield high="3" low="0" name="BYTEL8"/>
1366
<bitfield high="7" low="4" name="BYTEL9"/>
1367
<bitfield high="11" low="8" name="BYTEL10"/>
1368
<bitfield high="15" low="12" name="BYTEL11"/>
1369
<bitfield high="19" low="16" name="BYTEL12"/>
1370
<bitfield high="23" low="20" name="BYTEL13"/>
1371
<bitfield high="27" low="24" name="BYTEL14"/>
1372
<bitfield high="31" low="28" name="BYTEL15"/>
1374
<reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1375
<reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1376
<array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>
1377
<reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1378
<reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1379
<reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1380
<reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1381
<reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1382
<reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1383
<reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1384
<reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1385
<reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1386
<reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1387
<reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1388
<reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1389
<reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1390
<reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1391
<reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1392
<reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1393
<reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1394
<bitfield high="7" low="0" name="PERFSEL"/>
1396
<array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
1397
<reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
1399
<reg32 offset="0x3000" name="VBIF_VERSION"/>
1400
<reg32 offset="0x3001" name="VBIF_CLKON">
1401
<bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
1403
<reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1404
<reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1405
<reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1406
<reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1407
<reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1408
<reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1409
<bitfield low="0" high="3" name="DATA_SEL"/>
1411
<reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1412
<reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1413
<bitfield low="0" high="8" name="DATA_SEL"/>
1415
<reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1416
<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1417
<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1418
<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1419
<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1420
<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1421
<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1422
<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1423
<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1424
<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1425
<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1426
<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1427
<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1428
<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1429
<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1430
<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1431
<reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1432
<reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1433
<reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1434
<reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1435
<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1436
<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1438
<reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
1439
<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
1440
<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
1441
<reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
1442
<reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
1443
<reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
1444
<reg32 offset="0x3c45" name="GBIF_HALT"/>
1445
<reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
1446
<reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
1447
<reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
1448
<reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
1449
<reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
1450
<reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
1451
<reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
1452
<reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
1453
<reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
1454
<reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
1455
<reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
1456
<reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
1457
<reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
1458
<reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
1459
<reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
1460
<reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
1461
<reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
1462
<reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
1464
<reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>
1465
<reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1466
<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1467
<bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1469
<reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/>
1470
<reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1471
<bitfield name="NX" low="1" high="10" type="uint"/>
1472
<bitfield name="NY" low="11" high="20" type="uint"/>
1474
<array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1475
<reg32 offset="0x0" name="REG">
1477
Configures the mapping between VSC_PIPE buffer and
1478
bin, X/Y specify the bin index in the horiz/vert
1479
direction (0,0 is upper left, 0,1 is leftmost bin
1480
on second row, and so on). W/H specify the number
1481
of bins assigned to this VSC_PIPE in the horiz/vert
1484
<bitfield name="X" low="0" high="9" type="uint"/>
1485
<bitfield name="Y" low="10" high="19" type="uint"/>
1486
<bitfield name="W" low="20" high="25" type="uint"/>
1487
<bitfield name="H" low="26" high="31" type="uint"/>
1491
HW binning primitive & draw streams, which enable draws and primitives
1492
within a draw to be skipped in the main tile pass. See:
1493
https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
1495
Compared to a5xx and earlier, we just program the address of the first
1496
stream and hw adds (pipe_num * VSC_*_STRM_PITCH)
1498
LIMIT is set to PITCH - 64, to make room for a bit of overflow
1500
<reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/>
1501
<reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/>
1502
<reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT"/>
1503
<reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/>
1504
<reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/>
1505
<reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT"/>
1507
<array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1509
Seems to be a bitmap of which tiles mapped to the VSC
1510
pipe contain geometry.
1512
I suppose we can connect a maximum of 32 tiles to a
1515
<reg32 offset="0x0" name="REG"/>
1518
<array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32">
1520
Has the size of data written to corresponding VSC_PRIM_STRM
1523
<reg32 offset="0x0" name="REG"/>
1526
<array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32">
1528
Has the size of data written to corresponding VSC pipe, ie.
1529
same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI
1531
<reg32 offset="0x0" name="REG"/>
1534
<!-- always 0x03200000 ? -->
1535
<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1537
<!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
1538
<bitset name="a6xx_reg_xy" inline="yes">
1539
<bitfield name="X" low="0" high="13" type="uint"/>
1540
<bitfield name="Y" low="16" high="29" type="uint"/>
1543
<reg32 offset="0x8000" name="GRAS_CL_CNTL">
1544
<bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
1545
<bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
1546
<bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
1547
<!-- set with depthClampEnable, not clear what it does -->
1548
<bitfield name="UNK5" pos="5" type="boolean"/>
1549
<!-- controls near z clip behavior (set for vulkan) -->
1550
<bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1551
<!-- guess based on a3xx and meaning of bits 8 and 9
1552
if the guess is right then this is related to point sprite clipping -->
1553
<bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
1554
<bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
1555
<bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
1558
<bitset name="a6xx_gras_xs_cl_cntl" inline="yes">
1559
<bitfield name="CLIP_MASK" low="0" high="7"/>
1560
<bitfield name="CULL_MASK" low="8" high="15"/>
1562
<reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1563
<reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1564
<reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1565
<reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint"/>
1567
<reg32 offset="0x8005" name="GRAS_CNTL">
1568
<!-- see also RB_RENDER_CONTROL0 -->
1569
<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1570
<bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
1571
<bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
1572
<bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
1573
<bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
1574
<bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
1575
<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1577
<reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1578
<bitfield name="HORZ" low="0" high="8" type="uint"/>
1579
<bitfield name="VERT" low="10" high="18" type="uint"/>
1581
<!-- 0x8006-0x800f invalid -->
1582
<array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16">
1583
<reg32 offset="0" name="XOFFSET" type="float"/>
1584
<reg32 offset="1" name="XSCALE" type="float"/>
1585
<reg32 offset="2" name="YOFFSET" type="float"/>
1586
<reg32 offset="3" name="YSCALE" type="float"/>
1587
<reg32 offset="4" name="ZOFFSET" type="float"/>
1588
<reg32 offset="5" name="ZSCALE" type="float"/>
1590
<array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16">
1591
<reg32 offset="0" name="MIN" type="float"/>
1592
<reg32 offset="1" name="MAX" type="float"/>
1595
<reg32 offset="0x8090" name="GRAS_SU_CNTL">
1596
<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1597
<bitfield name="CULL_BACK" pos="1" type="boolean"/>
1598
<bitfield name="FRONT_CW" pos="2" type="boolean"/>
1599
<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1600
<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1601
<bitfield name="UNK12" pos="12"/>
1602
<bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
1603
<bitfield name="UNK15" low="15" high="16"/>
1605
This is set by the blob when multiview is enabled, but doesn't seem
1608
<bitfield name="UNK17" pos="17" type="boolean"/>
1609
<bitfield name="MULTIVIEW_ENABLE" pos="18" type="boolean"/>
1610
<bitfield name="UNK19" low="19" high="22"/>
1612
<reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1613
<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1614
<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1616
<reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4"/>
1617
<!-- 0x8093 invalid -->
1618
<reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1619
<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
1621
<reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1622
<reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1623
<reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1624
<!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1625
<reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1626
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1627
<bitfield name="UNK3" pos="3"/>
1630
<reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL">
1631
<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
1632
<bitfield name="SHIFTAMOUNT" low="1" high="2"/>
1633
<bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/>
1634
<bitfield name="UNK4" low="4" high="5"/>
1636
<reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL">
1637
<bitfield name="UNK0" pos="0" type="boolean"/>
1638
<bitfield name="LINELENGTHEN" pos="1" type="boolean"/>
1641
<bitset name="a6xx_gras_layer_cntl" inline="yes">
1642
<bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
1643
<bitfield name="WRITES_VIEW" pos="1" type="boolean"/>
1645
<reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1646
<reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1647
<reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1648
<!-- 0x809e/0x809f invalid -->
1650
<enum name="a6xx_sequenced_thread_dist">
1651
<value value="0x0" name="DIST_SCREEN_COORD"/>
1652
<value value="0x1" name="DIST_ALL_TO_RB0"/>
1655
<enum name="a6xx_single_prim_mode">
1656
<value value="0x0" name="NO_FLUSH"/>
1658
In addition to FLUSH_PER_OVERLAP, guarantee that UCHE
1659
and CCU don't get out of sync when fetching the previous
1660
value for the current pixel. With NO_FLUSH, there's the
1661
possibility that the flags for the current pixel are
1662
flushed before the data or vice-versa, leading to
1663
texture fetches via UCHE getting out of sync values.
1664
This mode should eliminate that. It's used in bypass
1665
mode for coherent blending
1666
(GL_KHR_blend_equation_advanced_coherent) as well as
1667
non-coherent blending.
1669
<value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/>
1671
Invalidate UCHE and wait for any pending work to finish
1672
if there was possibly an overlapping primitive prior to
1673
the current one. This is similar to a combination of
1674
GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and
1675
WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for
1677
(GL_KHR_blend_equation_advanced_coherent).
1679
<value value="0x3" name="FLUSH_PER_OVERLAP"/>
1682
<!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
1683
<enum name="a6xx_raster_mode">
1684
<value value="0x0" name="TYPE_TILED"/>
1685
<value value="0x1" name="TYPE_WRITER"/>
1688
<!-- I'm guessing this is the same as a3xx -->
1689
<enum name="a6xx_raster_direction">
1690
<value value="0x0" name="LR_TB"/>
1691
<value value="0x1" name="RL_TB"/>
1692
<value value="0x2" name="LR_BT"/>
1693
<value value="0x3" name="RB_BT"/>
1696
<reg32 offset="0x80a0" name="GRAS_SC_CNTL">
1697
<bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>
1698
<bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/>
1699
<bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/>
1700
<bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/>
1701
<bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/>
1702
<!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->
1703
<bitfield name="UNK9" low="9" high="11"/>
1704
<bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/>
1707
<enum name="a6xx_render_mode">
1708
<value value="0x0" name="RENDERING_PASS"/>
1709
<value value="0x1" name="BINNING_PASS"/>
1712
<enum name="a6xx_buffers_location">
1713
<value value="0" name="BUFFERS_IN_GMEM"/>
1714
<value value="3" name="BUFFERS_IN_SYSMEM"/>
1717
<reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1718
<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
1719
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
1720
<bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
1721
<bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
1722
<bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/>
1723
<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
1724
<bitfield name="UNK27" pos="27"/>
1727
<reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1728
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1729
<bitfield name="UNK2" pos="2"/>
1730
<bitfield name="UNK3" pos="3"/>
1732
<reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1733
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1734
<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1737
<bitset name="a6xx_sample_config" inline="yes">
1738
<bitfield name="UNK0" pos="0"/>
1739
<bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
1742
<bitset name="a6xx_sample_locations" inline="yes">
1743
<bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
1744
<bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
1745
<bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
1746
<bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
1747
<bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
1748
<bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
1749
<bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
1750
<bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
1753
<reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
1754
<reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
1755
<reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
1756
<!-- 0x80a7-0x80ae invalid -->
1757
<reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0"/>
1759
<bitset name="a6xx_scissor_xy" inline="yes">
1760
<bitfield name="X" low="0" high="15" type="uint"/>
1761
<bitfield name="Y" low="16" high="31" type="uint"/>
1763
<array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16">
1764
<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1765
<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1767
<array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16">
1768
<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1769
<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1772
<reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy"/>
1773
<reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy"/>
1774
<!-- 0x80f2-0x80ff invalid -->
1776
<reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
1778
These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
1779
look when we get around to enabling lrz
1781
<bitfield name="ENABLE" pos="0" type="boolean"/>
1782
<doc>LRZ write also disabled for blend/etc.</doc>
1783
<bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
1784
<doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
1785
<bitfield name="GREATER" pos="2" type="boolean"/>
1786
<bitfield name="FC_ENABLE" pos="3" type="boolean"/>
1787
<!-- set when depth-test + depth-write enabled -->
1788
<bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
1789
<bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
1790
<bitfield name="UNK6" low="6" high="9"/>
1793
<enum name="a6xx_fragcoord_sample_mode">
1794
<value value="0" name="FRAGCOORD_CENTER"/>
1795
<value value="3" name="FRAGCOORD_SAMPLE"/>
1798
<reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2">
1799
<bitfield name="SAMPLEID" pos="0" type="boolean"/>
1800
<bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/>
1803
<reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUF_INFO_0">
1804
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
1806
<reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress"/>
1807
<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
1808
<!-- TODO: fix the shr fields -->
1809
<bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
1810
<bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>
1814
The LRZ "fast clear" buffer is initialized to zero's by blob, and
1815
read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set. It appears
1816
to store 1b/block. It appears that '0' means block has original
1817
depth clear value, and '1' means that the corresponding block in
1818
LRZ has been modified. Ignoring alignment/padding, the size is
1819
given by the formula:
1821
// calculate LRZ size from depth size:
1822
if (nr_samples == 4) {
1825
} else if (nr_samples == 2) {
1829
lrz_width = div_round_up(width, 8);
1830
lrz_heigh = div_round_up(height, 8);
1832
// calculate # of blocks:
1833
nblocksx = div_round_up(lrz_width, 16);
1834
nblocksy = div_round_up(lrz_height, 4);
1836
// fast-clear buffer is 1bit/block:
1837
fc_sz = div_round_up(nblocksx * nblocksy, 8);
1839
In practice the blob seems to switch off FC_ENABLE once the size
1840
increases beyond 1 page. Not sure if that is an actual limit or
1843
<reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/>
1844
<!-- 0x8108 invalid -->
1845
<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
1846
<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
1848
<reg32 offset="0x810a" name="GRAS_UNKNOWN_810A">
1849
<bitfield name="UNK0" low="0" high="10" type="uint"/>
1850
<bitfield name="UNK16" low="16" high="26" type="uint"/>
1851
<bitfield name="UNK28" low="28" high="31" type="uint"/>
1854
<!-- 0x810b-0x810f invalid -->
1856
<reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1"/>
1858
<!-- 0x8111-0x83ff invalid -->
1860
<enum name="a6xx_rotation">
1861
<value value="0x0" name="ROTATE_0"/>
1862
<value value="0x1" name="ROTATE_90"/>
1863
<value value="0x2" name="ROTATE_180"/>
1864
<value value="0x3" name="ROTATE_270"/>
1865
<value value="0x4" name="ROTATE_HFLIP"/>
1866
<value value="0x5" name="ROTATE_VFLIP"/>
1869
<bitset name="a6xx_2d_blit_cntl" inline="yes">
1870
<bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
1871
<bitfield name="OVERWRITEEN" pos="3" type="boolean"/>
1872
<bitfield name="UNK4" low="4" high="6"/>
1873
<bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
1874
<bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
1875
<bitfield name="SCISSOR" pos="16" type="boolean"/>
1876
<bitfield name="UNK17" low="17" high="18"/>
1877
<!-- required when blitting D24S8/D24X8 -->
1878
<bitfield name="D24S8" pos="19" type="boolean"/>
1879
<!-- some sort of channel mask, disabled channels are set to zero ? -->
1880
<bitfield name="MASK" low="20" high="23"/>
1881
<bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
1882
<bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/>
1885
<reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
1886
<!-- note: the low 8 bits for src coords are valid, probably fixed point
1887
it would be a bit weird though, since we subtract 1 from BR coords
1888
apparently signed, gallium driver uses negative coords and it works?
1890
<reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int"/>
1891
<reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int"/>
1892
<reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int"/>
1893
<reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int"/>
1894
<reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy"/>
1895
<reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy"/>
1896
<reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
1897
<reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
1898
<reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
1899
<reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy"/>
1900
<reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy"/>
1901
<!-- 0x840c-0x85ff invalid -->
1903
<!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
1904
<reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL">
1905
<bitfield name="UNK7" pos="7" type="boolean"/>
1906
<bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/>
1908
<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
1909
<array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
1910
<array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
1911
<array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
1913
<!-- note 0x8620-0x87ff are not all invalid
1914
(in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
1917
<!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
1918
<reg32 offset="0x8800" name="RB_BIN_CONTROL">
1919
<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
1920
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
1921
<bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
1922
<bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
1923
<bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/>
1924
<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
1927
<reg32 offset="0x8801" name="RB_RENDER_CNTL">
1928
<bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/>
1929
<bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
1930
<!-- set during binning pass: -->
1931
<bitfield name="BINNING" pos="7" type="boolean"/>
1932
<bitfield name="UNK8" low="8" high="10"/>
1933
<bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
1934
<bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
1935
<bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
1936
<bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
1937
<!-- bit seems to be set whenever depth buffer enabled: -->
1938
<bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
1939
<!-- bitmask of MRTs using UBWC flag buffer: -->
1940
<bitfield name="FLAG_MRTS" low="16" high="23"/>
1942
<reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
1943
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1944
<bitfield name="UNK2" pos="2"/>
1945
<bitfield name="UNK3" pos="3"/>
1947
<reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
1948
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1949
<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1952
<reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
1953
<reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
1954
<reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
1955
<!-- 0x8807-0x8808 invalid -->
1957
note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
1958
name comes from kernel and is probably right)
1960
<reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
1961
<!-- see also GRAS_CNTL -->
1962
<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1963
<bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
1964
<bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
1965
<bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
1966
<bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
1967
<bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
1968
<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1969
<bitfield name="UNK10" pos="10" type="boolean"/>
1971
<reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
1972
<!-- enable bits for various FS sysvalue regs: -->
1973
<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
1974
<bitfield name="UNK1" pos="1" type="boolean"/>
1975
<bitfield name="FACENESS" pos="2" type="boolean"/>
1976
<bitfield name="SAMPLEID" pos="3" type="boolean"/>
1977
<bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>
1978
<bitfield name="SIZE" pos="6" type="boolean"/>
1979
<bitfield name="LINELENGTHEN" pos="7" type="boolean"/>
1980
<bitfield name="FOVEATION" pos="8" type="boolean"/>
1983
<reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
1984
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
1985
<bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
1986
<bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
1987
<bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>
1989
<reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
1990
<bitfield name="MRT" low="0" high="3" type="uint"/>
1992
<reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
1993
<bitfield name="RT0" low="0" high="3"/>
1994
<bitfield name="RT1" low="4" high="7"/>
1995
<bitfield name="RT2" low="8" high="11"/>
1996
<bitfield name="RT3" low="12" high="15"/>
1997
<bitfield name="RT4" low="16" high="19"/>
1998
<bitfield name="RT5" low="20" high="23"/>
1999
<bitfield name="RT6" low="24" high="27"/>
2000
<bitfield name="RT7" low="28" high="31"/>
2002
<reg32 offset="0x880e" name="RB_DITHER_CNTL">
2003
<bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/>
2004
<bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/>
2005
<bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/>
2006
<bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/>
2007
<bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/>
2008
<bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2009
<bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
2010
<bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2012
<reg32 offset="0x880f" name="RB_SRGB_CNTL">
2013
<!-- Same as SP_SRGB_CNTL -->
2014
<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2015
<bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2016
<bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2017
<bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2018
<bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2019
<bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2020
<bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2021
<bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2024
<reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2025
<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2027
<reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6"/>
2028
<!-- 0x8812-0x8817 invalid -->
2029
<!-- always 0x0 ? -->
2030
<reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6"/>
2031
<!-- 0x8819-0x881e all 32 bits -->
2032
<reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2033
<reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2034
<reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2035
<reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2036
<reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2037
<reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2038
<!-- 0x881f invalid -->
2039
<array offset="0x8820" name="RB_MRT" stride="8" length="8">
2040
<reg32 offset="0x0" name="CONTROL">
2041
<bitfield name="BLEND" pos="0" type="boolean"/>
2042
<bitfield name="BLEND2" pos="1" type="boolean"/>
2043
<bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2044
<bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2045
<bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2047
<reg32 offset="0x1" name="BLEND_CONTROL">
2048
<bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2049
<bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2050
<bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2051
<bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2052
<bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2053
<bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2055
<reg32 offset="0x2" name="BUF_INFO">
2056
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2057
<bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2058
<bitfield name="UNK10" pos="10"/>
2059
<bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2062
at least in gmem, things seem to be aligned to pitch of 64..
2063
maybe an artifact of tiled format used in gmem?
2065
<reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>
2066
<reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>
2068
Compared to a5xx and before, we configure both a GMEM base and
2069
external base. Not sure if this is to facilitate GMEM save/
2070
restore for context switch, or just to simplify state setup to
2071
not have to care about GMEM vs BYPASS mode.
2073
<!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
2074
<reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
2076
<reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
2079
<reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2080
<reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2081
<reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2082
<reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2083
<reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2084
<bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2085
<bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2086
<bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2088
<reg32 offset="0x8865" name="RB_BLEND_CNTL">
2089
<!-- per-mrt enable bit -->
2090
<bitfield name="ENABLE_BLEND" low="0" high="7"/>
2091
<bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2092
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
2093
<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2094
<bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
2095
<bitfield name="SAMPLE_MASK" low="16" high="31"/>
2097
<!-- 0x8866-0x886f invalid -->
2098
<reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2099
<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
2102
<reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2103
<bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
2104
<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2105
<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2106
<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
2108
Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
2109
also set when Z_BOUNDS_ENABLE is set
2111
<bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>
2112
<bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
2114
<!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2115
<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2116
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2117
<bitfield name="UNK3" low="3" high="4"/>
2119
<reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint"/>
2120
<reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint"/>
2121
<reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64"/>
2122
<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
2124
<reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float"/>
2125
<reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float"/>
2126
<!-- 0x887a-0x887f invalid -->
2127
<reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2128
<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2129
<bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2131
set for stencil operations that require read from stencil
2132
buffer, but not for example for stencil clear (which does
2133
not require read).. so guessing this is analogous to
2134
READ_DEST_ENABLE for color buffer..
2136
<bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2137
<bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2138
<bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2139
<bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2140
<bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2141
<bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2142
<bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2143
<bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2144
<bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2146
<reg32 offset="0x8881" name="RB_STENCIL_INFO">
2147
<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2148
<bitfield name="UNK1" pos="1" type="boolean"/>
2150
<reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint"/>
2151
<reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint"/>
2152
<reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64"/>
2153
<reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
2154
<reg32 offset="0x8887" name="RB_STENCILREF">
2155
<bitfield name="REF" low="0" high="7"/>
2156
<bitfield name="BFREF" low="8" high="15"/>
2158
<reg32 offset="0x8888" name="RB_STENCILMASK">
2159
<bitfield name="MASK" low="0" high="7"/>
2160
<bitfield name="BFMASK" low="8" high="15"/>
2162
<reg32 offset="0x8889" name="RB_STENCILWRMASK">
2163
<bitfield name="WRMASK" low="0" high="7"/>
2164
<bitfield name="BFWRMASK" low="8" high="15"/>
2166
<!-- 0x888a-0x888f invalid -->
2167
<reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy"/>
2168
<reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2169
<bitfield name="UNK0" pos="0" type="boolean"/>
2170
<bitfield name="COPY" pos="1" type="boolean"/>
2172
<!-- 0x8892-0x8897 invalid -->
2173
<reg32 offset="0x8898" name="RB_LRZ_CNTL">
2174
<bitfield name="ENABLE" pos="0" type="boolean"/>
2176
<!-- 0x8899-0x88bf invalid -->
2177
<!-- clamps depth value for depth test/write -->
2178
<reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
2179
<reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
2180
<!-- 0x88c2-0x88cf invalid-->
2181
<reg32 offset="0x88d0" name="RB_UNKNOWN_88D0">
2182
<bitfield name="UNK0" low="0" high="12"/>
2183
<bitfield name="UNK16" low="16" high="26"/>
2185
<reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy"/>
2186
<reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy"/>
2187
<!-- weird to duplicate other regs from same block?? -->
2188
<reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
2189
<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2190
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2192
<reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy"/>
2193
<reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2194
<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2196
<reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12"/>
2197
<!-- s/DST_FORMAT/DST_INFO/ probably: -->
2198
<reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2199
<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2200
<bitfield name="FLAGS" pos="2" type="boolean"/>
2201
<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2202
<bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2203
<bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
2204
<bitfield name="UNK15" pos="15" type="boolean"/>
2206
<reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64"/>
2207
<reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
2208
<!-- array-pitch is size of layer -->
2209
<reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
2210
<reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64"/>
2211
<reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2212
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2213
<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
2216
<reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2217
<reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2218
<reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2219
<reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2221
<!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2222
<reg32 offset="0x88e3" name="RB_BLIT_INFO">
2223
<bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? -->
2224
<bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2225
<bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
2226
<bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2228
For clearing depth/stencil
2232
For clearing color buffer:
2233
then probably a component mask, I always see 0xf
2235
<bitfield name="CLEAR_MASK" low="4" high="7"/>
2236
<bitfield name="UNK8" low="8" high="9"/>
2237
<bitfield name="UNK12" low="12" high="15"/>
2239
<!-- 0x88e4-0x88ef invalid -->
2240
<!-- always 0x0 ? -->
2241
<reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11"/>
2242
<!-- could be for separate stencil? (or may not be a flag buffer at all) -->
2243
<reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2244
<reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">
2245
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2246
<bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>
2248
<reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
2249
<!-- 0x88f5-0x88ff invalid -->
2250
<reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2251
<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2252
<bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
2253
<!-- TODO: actually part of array pitch -->
2254
<bitfield name="UNK8" low="8" high="10"/>
2255
<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
2257
<array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2258
<reg64 offset="0" name="ADDR" type="waddress" align="64"/>
2259
<reg32 offset="2" name="PITCH">
2260
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2261
<bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>
2264
<!-- 0x891b-0x8926 invalid -->
2265
<reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16"/>
2266
<!-- 0x8929-0x89ff invalid -->
2268
<!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
2271
These show up in a6xx gen3+ but so far haven't found an example of
2272
blob writing non-zero:
2274
<reg32 offset="0x8a00" name="RB_UNKNOWN_8A00"/>
2275
<reg32 offset="0x8a10" name="RB_UNKNOWN_8A10"/>
2276
<reg32 offset="0x8a20" name="RB_UNKNOWN_8A20"/>
2277
<reg32 offset="0x8a30" name="RB_UNKNOWN_8A30"/>
2279
<reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2280
<reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31"/>
2282
<bitset name="a6xx_2d_surf_info" inline="yes">
2283
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2284
<bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2285
<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2286
<bitfield name="FLAGS" pos="12" type="boolean"/>
2287
<bitfield name="SRGB" pos="13" type="boolean"/>
2288
<!-- the rest is only for src -->
2289
<bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2290
<bitfield name="FILTER" pos="16" type="boolean"/>
2291
<bitfield name="UNK17" pos="17" type="boolean"/>
2292
<bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2293
<bitfield name="UNK19" pos="19" type="boolean"/>
2294
<bitfield name="UNK20" pos="20" type="boolean"/>
2295
<bitfield name="UNK21" pos="21" type="boolean"/>
2296
<bitfield name="UNK22" pos="22" type="boolean"/>
2297
<bitfield name="UNK23" low="23" high="26"/>
2298
<bitfield name="UNK28" pos="28" type="boolean"/>
2301
<!-- 0x8c02-0x8c16 invalid -->
2302
<!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
2303
<reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
2304
<reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64"/>
2305
<reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
2306
<!-- this is a guess but seems likely (for NV12/IYUV): -->
2307
<reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64"/>
2308
<reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint"/>
2309
<reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64"/>
2311
<reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64"/>
2312
<reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/>
2313
<!-- this is a guess but seems likely (for NV12 with UBWC): -->
2314
<reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64"/>
2315
<reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint"/>
2317
<!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
2318
<!-- unlike a5xx, these are per channel values rather than packed -->
2319
<reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2320
<reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2321
<reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2322
<reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2323
<!-- 0x8c34-0x8dff invalid -->
2325
<!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
2326
<reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2327
<!-- 0x8e00-0x8e03 invalid -->
2328
<reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/> <!-- TODO: valid mask 0xfffffeff -->
2329
<reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2330
<!-- 0x8e06 invalid -->
2331
<reg32 offset="0x8e07" name="RB_CCU_CNTL">
2332
<!-- GMEM offset of CCU color cache
2333
for GMEM rendering, we set it to GMEM size minus the minimum
2334
CCU color cache size. CCU color cache will be needed in some
2335
resolve cases, and in those cases we need to reserve the end
2336
of GMEM for color cache.
2338
<bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
2339
<!-- GMEM offset of CCU depth cache -->
2340
<bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
2341
<bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
2342
<bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
2343
<!--TODO: valid mask 0xfffffc1f -->
2345
<reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">
2346
<bitfield name="MODE" pos="0" type="boolean"/>
2347
<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
2348
<bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
2349
<bitfield name="AMSBC" pos="4" type="boolean"/>
2350
<bitfield name="UPPER_BIT" pos="10" type="uint"/>
2351
<bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/>
2352
<bitfield name="UNK12" low="12" high="13"/>
2354
<!-- 0x8e09-0x8e0f invalid -->
2355
<array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>
2356
<array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>
2357
<!-- 0x8e1d-0x8e1f invalid -->
2358
<!-- 0x8e20-0x8e25 more perfcntr sel? -->
2359
<!-- 0x8e26-0x8e27 invalid -->
2360
<reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/>
2361
<!-- 0x8e29-0x8e2b invalid -->
2362
<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
2363
<reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
2364
<reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
2365
<!-- 0x8e3e-0x8e4f invalid -->
2366
<!-- GMEM save/restore for preemption: -->
2367
<reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/>
2368
<!-- address for GMEM save/restore? -->
2369
<reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/>
2370
<!-- 0x8e53-0x8e7f invalid -->
2371
<!-- 0x8e80-0x8e83 are valid -->
2372
<!-- 0x8e84-0x90ff invalid -->
2374
<!-- 0x9000-0x90ff invalid -->
2376
<reg32 offset="0x9100" name="VPC_GS_PARAM">
2377
<bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/>
2380
<bitset name="a6xx_vpc_xs_clip_cntl" inline="yes">
2381
<bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
2382
<!-- there can be up to 8 total clip/cull distance outputs,
2383
but apparenly VPC can only deal with vec4, so when there are
2384
more than 4 outputs a second location needs to be programmed
2386
<bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
2387
<bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
2389
<reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2390
<reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2391
<reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2393
<bitset name="a6xx_vpc_xs_layer_cntl" inline="yes">
2394
<bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
2395
<bitfield name="VIEWLOC" low="8" high="15" type="uint"/>
2398
<reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2399
<reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2400
<reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2402
<reg32 offset="0x9107" name="VPC_UNKNOWN_9107">
2403
<!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
2404
<bitfield name="RASTER_DISCARD" pos="0" type="boolean"/>
2405
<bitfield name="UNK2" pos="2" type="boolean"/>
2407
<reg32 offset="0x9108" name="VPC_POLYGON_MODE">
2408
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
2410
<!-- 0x9109-0x91ff invalid -->
2411
<array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2412
<reg32 offset="0x0" name="MODE"/>
2414
<array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2415
<reg32 offset="0x0" name="MODE"/>
2419
<reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31"/>
2420
<reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31"/>
2422
<array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2423
<!-- one bit per varying component: -->
2424
<reg32 offset="0" name="DISABLE"/>
2427
<reg32 offset="0x9216" name="VPC_SO_CNTL">
2429
Choose which DWORD to write to. There is an array of
2430
(4 * 64) DWORD's, dumped in the devcoredump at
2431
HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a
2432
(VPC location, stream) pair like so:
2434
location 0, stream 0
2435
location 2, stream 0
2437
location 126, stream 0
2438
location 0, stream 1
2439
location 2, stream 1
2441
location 126, stream 1
2442
location 0, stream 2
2445
When EmitStreamVertex(N) happens, the HW goes to DWORD
2446
64 * N and then "executes" the next 64 DWORD's.
2448
This field is auto-incremented when VPC_SO_PROG is
2451
<bitfield name="ADDR" low="0" high="7" type="hex"/>
2452
<!-- clear all A_EN and B_EN bits for all DWORD's -->
2453
<bitfield name="RESET" pos="16" type="boolean"/>
2455
<!-- special register, write multiple times to load SO program (not readable) -->
2456
<reg32 offset="0x9217" name="VPC_SO_PROG">
2457
<bitfield name="A_BUF" low="0" high="1" type="uint"/>
2458
<bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2459
<bitfield name="A_EN" pos="11" type="boolean"/>
2460
<bitfield name="B_BUF" low="12" high="13" type="uint"/>
2461
<bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2462
<bitfield name="B_EN" pos="23" type="boolean"/>
2465
<reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32"/>
2467
<array offset="0x921a" name="VPC_SO" stride="7" length="4">
2468
<reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
2469
<reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
2470
<reg32 offset="3" name="NCOMP" low="0" high="9"/> <!-- component count -->
2471
<reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
2472
<reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
2475
<reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT">
2476
<bitfield name="INVERT" pos="0" type="boolean"/>
2478
<!-- 0x9237-0x92ff invalid -->
2479
<!-- always 0x0 ? -->
2480
<reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2"/>
2482
<bitset name="a6xx_vpc_xs_pack" inline="yes">
2484
num of varyings plus four for gl_Position (plus one if gl_PointSize)
2485
plus # of transform-feedback (streamout) varyings if using the
2486
hw streamout (rather than stg instructions in shader)
2488
<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2489
<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2490
<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2491
<bitfield name="EXTRAPOS" low="24" high="27" type="uint">
2493
The number of extra copies of POSITION, i.e.
2494
number of views minus one when multi-position
2495
output is enabled, otherwise 0.
2499
<reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack"/>
2500
<reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack"/>
2501
<reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack"/>
2503
<reg32 offset="0x9304" name="VPC_CNTL_0">
2504
<bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2505
<!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
2506
<bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
2507
<bitfield name="VARYING" pos="16" type="boolean"/>
2508
<bitfield name="VIEWIDLOC" low="24" high="31" type="uint">
2510
This VPC location will be overwritten with
2511
ViewID when multiview is enabled. It's used when
2512
fragment shaders read ViewID. It's only
2513
strictly required for multi-position output,
2514
where the same VS invocation is used for all the
2515
views at once, but it can be used when multi-pos
2516
output is disabled too, to avoid having to pass
2517
ViewID through the VS.
2522
<reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL">
2524
It's offset by 1, and 0 means "disabled"
2526
<bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/>
2527
<bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/>
2528
<bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/>
2529
<bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/>
2530
<bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
2532
<reg32 offset="0x9306" name="VPC_SO_DISABLE">
2533
<bitfield name="DISABLE" pos="0" type="boolean"/>
2535
<!-- 0x9307-0x95ff invalid -->
2537
<!-- TODO: 0x9600-0x97ff range -->
2538
<reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
2539
<reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2540
<reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0"/> <!-- always 0x0 ? -->
2541
<reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
2542
<array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6"/>
2543
<!-- 0x960a-0x9623 invalid -->
2544
<!-- TODO: regs from 0x9624-0x963a -->
2545
<!-- 0x963b-0x97ff invalid -->
2547
<reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint"/>
2549
<!-- always 0x0 ? -->
2550
<reg32 offset="0x9801" name="PC_HS_INPUT_SIZE">
2551
<bitfield name="SIZE" low="0" high="10" type="uint"/>
2552
<bitfield name="UNK13" pos="13"/>
2555
<enum name="a6xx_tess_spacing">
2556
<value value="0x0" name="TESS_EQUAL"/>
2557
<value value="0x2" name="TESS_FRACTIONAL_ODD"/>
2558
<value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
2560
<enum name="a6xx_tess_output">
2561
<value value="0x0" name="TESS_POINTS"/>
2562
<value value="0x1" name="TESS_LINES"/>
2563
<value value="0x2" name="TESS_CW_TRIS"/>
2564
<value value="0x3" name="TESS_CCW_TRIS"/>
2566
<reg32 offset="0x9802" name="PC_TESS_CNTL">
2567
<bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
2568
<bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
2571
<reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint"/>
2572
<reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7"/>
2574
<reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2"/>
2576
<!-- probably a mirror of VFD_CONTROL_6 -->
2577
<reg32 offset="0x9806" name="PC_PRIMID_PASSTHRU" pos="0" type="boolean"/>
2579
<!-- New in a6xx gen3+ -->
2580
<reg32 offset="0x9808" name="PC_SO_STREAM_CNTL">
2581
<bitfield name="STREAM_ENABLE" pos="15" type="boolean"/>
2584
<reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL">
2585
<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
2587
<!-- 0x980b-0x983f invalid -->
2589
<!-- 0x9840 - 0x9842 are not readable -->
2590
<reg32 offset="0x9840" name="PC_DRAW_CMD">
2591
<bitfield name="STATE_ID" low="0" high="7"/>
2594
<reg32 offset="0x9841" name="PC_DISPATCH_CMD">
2595
<bitfield name="STATE_ID" low="0" high="7"/>
2598
<reg32 offset="0x9842" name="PC_EVENT_CMD">
2599
<!-- I think only the low bit is actually used? -->
2600
<bitfield name="STATE_ID" low="16" high="23"/>
2601
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
2605
0x9880 written in a lot of places by SQE, same value gets written
2606
to control reg 0x12a. Set by CP_SET_MARKER, so lets name it after
2609
<reg32 offset="0x9880" name="PC_MARKER"/>
2611
<!-- 0x9843-0x997f invalid -->
2613
<reg32 offset="0x9981" name="PC_POLYGON_MODE">
2614
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
2617
<reg32 offset="0x9980" name="PC_RASTER_CNTL">
2618
<!-- which stream to send to GRAS -->
2619
<bitfield name="STREAM" low="0" high="1" type="uint"/>
2620
<!-- discard primitives before rasterization -->
2621
<bitfield name="DISCARD" pos="2" type="boolean"/>
2624
<!-- 0x9982-0x9aff invalid -->
2626
<reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2627
<bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2628
<!-- maybe? b1 seems always set, so just assume it is for now: -->
2629
<bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
2630
<bitfield name="TESS_UPPER_LEFT_DOMAIN_ORIGIN" pos="2" type="boolean"/>
2631
<bitfield name="UNK3" pos="3" type="boolean"/>
2634
<bitset name="a6xx_xs_out_cntl" inline="yes">
2636
num of varyings plus four for gl_Position (plus one if gl_PointSize)
2637
plus # of transform-feedback (streamout) varyings if using the
2638
hw streamout (rather than stg instructions in shader)
2640
<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2641
<bitfield name="PSIZE" pos="8" type="boolean"/>
2642
<bitfield name="LAYER" pos="9" type="boolean"/>
2643
<bitfield name="VIEW" pos="10" type="boolean"/>
2644
<!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
2645
<bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
2646
<bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
2649
<reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2650
<reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2651
<!-- since HS can't output anything, only PRIMITIVE_ID is valid -->
2652
<reg32 offset="0x9b03" name="PC_HS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2653
<reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2655
<reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
2659
<!-- TODO: first 16 bits are valid so something is wrong or missing here -->
2660
<bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
2661
<bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
2662
<bitfield name="LINELENGTHEN" pos="15" type="boolean"/>
2663
<bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
2664
<bitfield name="UNK18" pos="18"/>
2667
<reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
2669
size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
2671
<bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
2674
<bitset name="a6xx_multiview_cntl" inline="yes">
2675
<bitfield name="ENABLE" pos="0" type="boolean"/>
2676
<bitfield name="DISABLEMULTIPOS" pos="1" type="boolean">
2678
Multi-position output lets the last geometry
2679
stage shader write multiple copies of
2680
gl_Position. If disabled then the VS is run once
2681
for each view, and ViewID is passed as a
2685
<bitfield name="VIEWS" low="2" high="6" type="uint"/>
2688
<reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl"/>
2689
<!-- mask of enabled views, doesn't exist on A630 -->
2690
<reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15"/>
2691
<!-- 0x9b09-0x9bff invalid -->
2692
<reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
2693
<!-- special register (but note first 8 bits can be written/read) -->
2694
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
2695
<bitfield name="STATE_ID" low="8" high="15"/>
2697
<!-- 0x9c01-0x9dff invalid -->
2698
<!-- TODO: 0x9e00-0xa000 range incomplete -->
2699
<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
2700
<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2701
<reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/>
2702
<reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/>
2703
<reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/>
2704
<reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
2706
<reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx">
2708
Possibly not really "initiating" the draw but the layout is similar
2709
to VGT_DRAW_INITIATOR on older gens
2712
<reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/>
2713
<reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/>
2715
<!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
2716
<reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
2717
<bitfield name="UNK0" low="0" high="15"/>
2718
<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
2719
<bitfield name="VSC_N" low="22" high="26" type="uint"/>
2721
<reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/>
2722
<reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/>
2724
<reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE">
2725
<doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc>
2726
<bitfield name="OVERRIDE" pos="0" type="boolean"/>
2729
<array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8"/>
2732
<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2734
<reg32 offset="0xa000" name="VFD_CONTROL_0">
2735
<bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
2736
<bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
2738
<reg32 offset="0xa001" name="VFD_CONTROL_1">
2739
<bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2740
<bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2741
<bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2742
<!-- only used for VS in non-multi-position-output case -->
2743
<bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/>
2745
<reg32 offset="0xa002" name="VFD_CONTROL_2">
2746
<bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid">
2748
This is the ID of the current patch within the
2749
subdraw, used to calculate the offset of the
2750
patch within the HS->DS buffers. When a draw is
2751
split into multiple subdraws then this differs
2752
from gl_PrimitiveID on the second, third, etc.
2756
<bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
2758
<reg32 offset="0xa003" name="VFD_CONTROL_3">
2759
<bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/>
2760
<bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/>
2761
<bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2762
<bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2764
<reg32 offset="0xa004" name="VFD_CONTROL_4">
2765
<bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
2767
<reg32 offset="0xa005" name="VFD_CONTROL_5">
2768
<bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
2769
<bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/>
2771
<reg32 offset="0xa006" name="VFD_CONTROL_6">
2773
True if gl_PrimitiveID is read via the FS and there is
2774
no matching write from the GS, and therefore it needs to
2775
be passed through via fixed-function logic.
2777
<bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
2780
<reg32 offset="0xa007" name="VFD_MODE_CNTL">
2781
<bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/>
2784
<reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl"/>
2785
<reg32 offset="0xa009" name="VFD_ADD_OFFSET">
2786
<!-- add VFD_INDEX_OFFSET to REGID4VTX -->
2787
<bitfield name="VERTEX" pos="0" type="boolean"/>
2788
<!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
2789
<bitfield name="INSTANCE" pos="1" type="boolean"/>
2792
<reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
2793
<reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
2794
<array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
2795
<reg64 offset="0x0" name="BASE" type="address" align="1"/>
2796
<reg32 offset="0x2" name="SIZE" type="uint"/>
2797
<reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/>
2799
<array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
2800
<reg32 offset="0x0" name="INSTR">
2801
<!-- IDX and byte OFFSET into VFD_FETCH -->
2802
<bitfield name="IDX" low="0" high="4" type="uint"/>
2803
<bitfield name="OFFSET" low="5" high="16"/>
2804
<bitfield name="INSTANCED" pos="17" type="boolean"/>
2805
<bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
2806
<bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2807
<bitfield name="UNK30" pos="30" type="boolean"/>
2808
<bitfield name="FLOAT" pos="31" type="boolean"/>
2810
<reg32 offset="0x1" name="STEP_RATE" type="uint"/>
2812
<array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
2813
<reg32 offset="0x0" name="INSTR">
2814
<bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2815
<bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2819
<reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2"/>
2822
Note: this seems to always be paired with another bit in another
2825
<enum name="a6xx_threadsize">
2826
<value value="0" name="THREAD64"/>
2827
<value value="1" name="THREAD128"/>
2829
<reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2830
<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8"/>
2832
<bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
2833
<!-- if set to SINGLE, only use 1 concurrent wave on each SP -->
2834
<bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
2836
When b31 set we just see FULLREGFOOTPRINT set. The pattern of
2837
used registers is a bit odd too:
2838
- used (half): 0-15 68-179 (cnt=128, max=179)
2839
- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
2840
whereas we usually see a (mostly) contiguous range of regs used. But if
2841
I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
2843
- used (merged): 0-191 (cnt=192, max=191)
2844
So I think if b31 is set, then the half precision registers overlap
2845
the full precision registers. (Which seems like a pretty sensible
2846
feature, actually I'm not sure when you *wouldn't* want to use that,
2847
since it gives register allocation more flexibility)
2849
<bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
2850
<bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
2851
<!-- could it be a low bit of branchstack? -->
2852
<bitfield name="UNK13" pos="13" type="boolean"/>
2853
<!-- seems to be nesting level for flow control:.. -->
2854
<bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
2857
<bitset name="a6xx_sp_xs_config" inline="yes">
2859
Each of these are set if the given resource type is used
2860
with the Vulkan/bindless binding model.
2862
<bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
2863
<bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
2864
<bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
2865
<bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
2867
<bitfield name="ENABLED" pos="8" type="boolean"/>
2869
number of textures and samplers.. these might be swapped, with GL I
2870
always see the same value for both.
2872
<bitfield name="NTEX" low="9" high="16" type="uint"/>
2873
<bitfield name="NSAMP" low="17" high="21" type="uint"/>
2874
<bitfield name="NIBO" low="22" high="28" type="uint"/>
2877
<bitset name="a6xx_sp_xs_prim_cntl" inline="yes">
2878
<!-- # of VS outputs including pos/psize -->
2879
<bitfield name="OUT" low="0" high="5" type="uint"/>
2880
<!-- FLAGS_REGID only for GS -->
2881
<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
2884
<reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
2886
This field actually controls all geometry stages. TCS, TES, and
2887
GS must have the same mergedregs setting as VS.
2889
<bitfield name="MERGEDREGS" pos="20" type="boolean"/>
2890
<!-- ??? (blob has it set) -->
2891
<bitfield name="UNK21" pos="21" type="boolean"/>
2893
<!-- bitmask of true/false conditions for VS brac.N instructions,
2894
bit N corresponds to brac.N -->
2895
<reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/>
2896
<!-- # of VS outputs including pos/psize -->
2897
<reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl"/>
2898
<array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
2899
<reg32 offset="0x0" name="REG">
2900
<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2901
<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2902
<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2903
<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2907
Starting with a5xx, position/psize outputs from shader end up in the
2908
SP_VS_OUT map, with highest OUTLOCn position. (Generally they are
2909
the last entries too, except when gl_PointCoord is used, blob inserts
2910
an extra varying after, but with a lower OUTLOC position. If present,
2911
psize is last, preceded by position.
2913
<array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
2914
<reg32 offset="0x0" name="REG">
2915
<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2916
<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2917
<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2918
<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2922
<bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes">
2923
<bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
2924
<doc>The size of memory that ldp/stp can address.</doc>
2926
<bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31">
2928
Seems to be the same as a3xx. The maximum stack
2929
size in units of 4 calls, so a call depth of 7
2930
would result in a value of 2.
2931
TODO: What's the actual size per call, i.e. the
2932
size of the PC? a3xx docs say it's 16 bits
2933
there, but the length register now takes 28 bits
2934
so it's probably been bumped to 32 bits.
2939
<bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes">
2940
<bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
2941
<bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean">
2943
There are four indices used to compute the
2944
private memory location for an access:
2948
- wavefront id (a swizzled version of what "getwid" returns)
2949
- SP ID (the same as what "getspid" returns)
2951
The stride for the SP ID is always set by
2952
TOTALPVTMEMSIZE. In the per-wave layout, the
2953
indices are used in this order:
2955
- offset % 4 (offset within dword)
2961
and the stride for the wavefront ID is
2962
MEMSIZEPERITEM, multiplied by 128 (fibers per
2963
wavefront). In the per-fiber layout, the indices
2964
are used in this order:
2972
and the stride for the fiber id/wavefront id
2973
combo is MEMSIZEPERITEM.
2975
Note: Accesses of more than 1 dword do not work
2976
with per-fiber layout. The blob will fall back
2977
to per-wave instead.
2982
<bitset name="a6xx_sp_xs_pvt_mem_hw_stack_offset" inline="yes">
2984
This seems to be be the equivalent of HWSTACKOFFSET in
2985
a3xx. The ldp/stp offset formula above isn't affected by
2986
HWSTACKSIZEPERTHREAD at all, so the HW return address
2987
stack seems to be after all the normal per-SP private
2990
<bitfield name="OFFSET" low="0" high="18" shr="11"/>
2993
<reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
2994
<reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32"/>
2995
<reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
2996
<reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32"/>
2997
<reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
2998
<reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint"/>
2999
<reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
3000
<reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint"/>
3001
<reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
3003
<reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
3005
There is no mergedregs bit, that comes from the VS.
3006
No idea what this bit does here.
3008
<bitfield name="UNK20" pos="20" type="boolean"/>
3011
Total size of local storage in dwords divided by the wave size.
3012
The maximum value is 64. With the wave size being always 64 for HS,
3013
the maximum size of local storage should be:
3014
64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k
3016
<reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint"/>
3017
<reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex"/>
3019
<!-- TODO: exact same layout as 0xa81b-0xa825 -->
3020
<reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
3021
<reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32"/>
3022
<reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
3023
<reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32"/>
3024
<reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
3025
<reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint"/>
3026
<reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
3027
<reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint"/>
3028
<reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
3030
<reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
3031
<!-- There is no mergedregs bit, that comes from the VS. -->
3032
<bitfield name="UNK20" pos="20" type="boolean"/> <!-- something preamble-related -->
3034
<reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/>
3036
<!-- TODO: exact same layout as 0xa802-0xa81a -->
3037
<reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl"/>
3038
<array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
3039
<reg32 offset="0x0" name="REG">
3040
<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
3041
<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
3042
<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
3043
<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
3046
<array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
3047
<reg32 offset="0x0" name="REG">
3048
<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
3049
<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
3050
<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
3051
<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
3055
<!-- TODO: exact same layout as 0xa81b-0xa825 -->
3056
<reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
3057
<reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32"/>
3058
<reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
3059
<reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32"/>
3060
<reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
3061
<reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint"/>
3062
<reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
3063
<reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint"/>
3064
<reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
3066
<reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
3068
There is no mergedregs bit, that comes from the VS.
3069
No idea what this bit does here.
3071
<bitfield name="UNK20" pos="20" type="boolean"/>
3073
<reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint">
3075
Normally the size of the output of the last stage in
3076
dwords. It should be programmed as follows:
3078
size less than 63 - size
3079
size of 63 (?) or 64 - 63
3080
size greater than 64 - 64
3082
What to program when the size is 61-63 is a guess, but
3083
both the blob and ir3 align the size to 4 dword's so it
3084
doesn't matter in practice.
3087
<reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex"/>
3089
<!-- TODO: exact same layout as 0xa802-0xa81a -->
3090
<reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl"/>
3091
<array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
3092
<reg32 offset="0x0" name="REG">
3093
<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
3094
<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
3095
<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
3096
<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
3100
<array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
3101
<reg32 offset="0x0" name="REG">
3102
<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
3103
<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
3104
<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
3105
<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
3109
<!-- TODO: exact same layout as 0xa81b-0xa825 -->
3110
<reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
3111
<reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32"/>
3112
<reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
3113
<reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32"/>
3114
<reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
3115
<reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint"/>
3116
<reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
3117
<reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint"/>
3118
<reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
3120
<reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16"/>
3121
<reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16"/>
3122
<reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16"/>
3123
<reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16"/>
3124
<reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64"/>
3125
<reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64"/>
3126
<reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64"/>
3127
<reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64"/>
3129
<!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->
3131
<reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
3132
<bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
3133
<bitfield name="UNK21" pos="21" type="boolean"/>
3134
<bitfield name="VARYING" pos="22" type="boolean"/>
3135
<bitfield name="DIFF_FINE" pos="23" type="boolean"/>
3136
<!-- note: vk blob uses bit24 -->
3137
<bitfield name="UNK24" pos="24" type="boolean"/>
3138
<bitfield name="UNK25" pos="25" type="boolean"/>
3139
<bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
3140
<bitfield name="UNK27" low="27" high="28"/>
3141
<bitfield name="MERGEDREGS" pos="31" type="boolean"/>
3143
<reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/>
3144
<reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
3145
<reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32"/>
3146
<reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
3147
<reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32"/>
3148
<reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
3150
<reg32 offset="0xa989" name="SP_BLEND_CNTL">
3151
<!-- per-mrt enable bit -->
3152
<bitfield name="ENABLE_BLEND" low="0" high="7"/>
3153
<bitfield name="UNK8" pos="8" type="boolean"/>
3154
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
3155
<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
3157
<reg32 offset="0xa98a" name="SP_SRGB_CNTL">
3158
<!-- Same as RB_SRGB_CNTL -->
3159
<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
3160
<bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
3161
<bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
3162
<bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
3163
<bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
3164
<bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
3165
<bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
3166
<bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
3168
<reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
3169
<bitfield name="RT0" low="0" high="3"/>
3170
<bitfield name="RT1" low="4" high="7"/>
3171
<bitfield name="RT2" low="8" high="11"/>
3172
<bitfield name="RT3" low="12" high="15"/>
3173
<bitfield name="RT4" low="16" high="19"/>
3174
<bitfield name="RT5" low="20" high="23"/>
3175
<bitfield name="RT6" low="24" high="27"/>
3176
<bitfield name="RT7" low="28" high="31"/>
3178
<reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
3179
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
3180
<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
3181
<bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
3182
<bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>
3184
<reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
3185
<bitfield name="MRT" low="0" high="3" type="uint"/>
3188
<array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
3190
<reg32 offset="0x0" name="REG">
3191
<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
3192
<bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
3196
<array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
3197
<reg32 offset="0" name="REG">
3198
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3199
<bitfield name="COLOR_SINT" pos="8" type="boolean"/>
3200
<bitfield name="COLOR_UINT" pos="9" type="boolean"/>
3201
<bitfield name="UNK10" pos="10" type="boolean"/>
3205
<reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
3206
<!-- unknown bits 0x7fc0 always set -->
3207
<bitfield name="COUNT" low="0" high="2" type="uint"/>
3208
<!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? -->
3209
<bitfield name="UNK3" pos="3" type="boolean"/>
3210
<bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/>
3211
<bitfield name="UNK12" low="12" high="14"/>
3213
<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
3214
<reg32 offset="0" name="CMD">
3215
<bitfield name="SRC" low="0" high="6" type="uint"/>
3216
<bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
3217
<bitfield name="TEX_ID" low="11" high="15" type="uint"/>
3218
<bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
3219
<bitfield name="WRMASK" low="22" high="25" type="hex"/>
3220
<bitfield name="HALF" pos="26" type="boolean"/>
3222
CMD seems always 0x4?? 3d, textureProj, textureLod seem to
3223
skip pre-fetch.. TODO test texelFetch
3224
CMD is 0x6 when the Vulkan mode is enabled, and
3225
TEX_ID/SAMP_ID refer to the descriptor sets while the
3226
indices come from SP_FS_BINDLESS_PREFETCH[n]
3228
<bitfield name="CMD" low="27" high="31"/>
3231
<array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4">
3232
<reg32 offset="0" name="CMD">
3233
<bitfield name="SAMP_ID" low="0" high="15" type="uint"/>
3234
<bitfield name="TEX_ID" low="16" high="31" type="uint"/>
3237
<reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint"/>
3238
<reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" /> <!-- always 0x0 ? -->
3239
<reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
3241
<!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
3246
<reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
3247
<bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
3248
<!-- seems to make SP use less concurrent threads when possible? -->
3249
<bitfield name="UNK21" pos="21" type="boolean"/>
3250
<!-- has a small impact on performance, not clear what it does -->
3251
<bitfield name="UNK22" pos="22" type="boolean"/>
3252
<!-- creates a separate prolog-only thread? -->
3253
<bitfield name="SEPARATEPROLOG" pos="23" type="boolean"/>
3254
<bitfield name="MERGEDREGS" pos="31" type="boolean"/>
3257
<!-- set for compute shaders -->
3258
<reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1">
3259
<bitfield name="SHARED_SIZE" low="0" high="4" type="uint">
3261
If 0 - all 32k of shared storage is enabled, otherwise
3262
(SHARED_SIZE + 1) * 1k is enabled.
3263
The ldl/stl offset seems to be rewritten to 0 when it is beyond
3264
this limit. This is different from ldlw/stlw, which wraps at
3265
64k (and has 36k of storage on A640 - reads between 36k-64k
3269
<bitfield name="UNK5" pos="5" type="boolean"/>
3271
<bitfield name="UNK6" pos="6" type="boolean"/>
3273
<reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex"/>
3274
<reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
3275
<reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32"/>
3276
<reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
3277
<reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32"/>
3278
<reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
3279
<reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint"/>
3280
<reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
3281
<reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint"/>
3282
<reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
3284
<!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 -->
3285
<reg32 offset="0xa9c2" name="SP_CS_CNTL_0">
3286
<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3287
<bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
3288
<bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
3289
<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3291
<!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 -->
3292
<reg32 offset="0xa9c3" name="SP_CS_CNTL_1">
3293
<!-- gl_LocalInvocationIndex -->
3294
<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
3295
<!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
3296
one of those 6 "SP cores" -->
3297
<bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
3298
<!-- Must match SP_CS_CTRL -->
3299
<bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
3300
<!-- 1 thread per wave (ignored if bit9 set) -->
3301
<bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
3304
<!-- TODO: two 64kb aligned addresses at a9d0/a9d2 -->
3306
<reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16"/>
3307
<reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16"/>
3308
<reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64"/>
3309
<reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64"/>
3311
<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
3312
<!-- TODO: probably align=64 with 6 flags bits in the low bits ? -->
3313
<reg64 offset="0" name="ADDR" type="address"/>
3317
IBO state for compute shader:
3319
<reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>
3320
<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>
3323
This enum is probably similar in purpose to SNORMMODE on a3xx,
3324
minus the snorm stuff, i.e. it controls what happens with an
3325
out-of-bounds isam/isamm. GL and Vulkan robustness require us to
3326
return 0 on out-of-bound textureFetch().
3328
<enum name="a6xx_isam_mode">
3329
<value value="0x2" name="ISAMMODE_GL"/>
3332
<reg32 offset="0xab00" name="SP_MODE_CONTROL">
3334
When set, half register loads from the constant file will
3335
load a 32-bit value (so hc0.y loads the same value as c0.y)
3336
and implicitly convert it to 16b (f2f16, or u2u16, based on
3337
operand type). When unset, half register loads from the
3338
constant file will load 16 bits from the packed constant
3339
file (so hc0.y loads the top 16 bits of the value of c0.x)
3341
<bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
3342
<bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/>
3343
<bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
3346
<reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
3347
<reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint"/>
3349
<array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
3350
<!-- TODO: probably align=64 with 6 flags bits in the low bits? -->
3351
<reg64 offset="0" name="ADDR" type="address"/>
3355
Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
3356
instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders.
3358
<reg64 offset="0xab1a" name="SP_IBO" type="address" align="16"/>
3359
<reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint"/>
3361
<reg32 offset="0xacc0" name="SP_2D_DST_FORMAT">
3362
<bitfield name="NORM" pos="0" type="boolean"/>
3363
<bitfield name="SINT" pos="1" type="boolean"/>
3364
<bitfield name="UINT" pos="2" type="boolean"/>
3365
<!-- looks like HW only cares about the base type of this format,
3366
which matches the ifmt? -->
3367
<bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
3368
<!-- set when ifmt is R2D_UNORM8_SRGB -->
3369
<bitfield name="SRGB" pos="11" type="boolean"/>
3370
<!-- some sort of channel mask, not sure what it is for -->
3371
<bitfield name="MASK" low="12" high="15"/>
3374
<reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
3375
<reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
3376
<reg32 offset="0xae02" name="SP_NC_MODE_CNTL">
3377
<!-- TODO: valid bits 0x3c3f, see kernel -->
3379
<reg32 offset="0xae03" name="SP_CHICKEN_BITS"/>
3380
<reg32 offset="0xae04" name="SP_FLOAT_CNTL">
3381
<bitfield name="F16_NO_INF" pos="3" type="boolean"/>
3384
<reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE">
3385
<!-- some perfcntrs are affected by a per-stage enable bit
3386
(PERF_SP_ALU_WORKING_CYCLES for example)
3387
TODO: verify position of HS/DS/GS bits -->
3388
<bitfield name="VS" pos="0" type="boolean"/>
3389
<bitfield name="HS" pos="1" type="boolean"/>
3390
<bitfield name="DS" pos="2" type="boolean"/>
3391
<bitfield name="GS" pos="3" type="boolean"/>
3392
<bitfield name="FS" pos="4" type="boolean"/>
3393
<bitfield name="CS" pos="5" type="boolean"/>
3395
<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
3396
<!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
3397
<!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
3398
<reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
3401
The downstream kernel calls the debug cluster of registers
3402
"a6xx_sp_ps_tp_cluster" but this actually specifies the border
3403
color base for compute shaders.
3405
<reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128"/>
3406
<reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2"/>
3407
<reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23"/>
3409
<reg32 offset="0xb190" name="SP_UNKNOWN_B190"/>
3410
<reg32 offset="0xb191" name="SP_UNKNOWN_B191"/>
3412
<!-- could be all the stuff below here is actually TPL1?? -->
3414
<reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
3415
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3416
<bitfield name="UNK2" low="2" high="3"/>
3418
<reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
3419
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3420
<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3423
<!-- looks to work in the same way as a5xx: -->
3424
<reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128"/>
3425
<reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
3426
<reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
3427
<reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
3428
<reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy"/>
3429
<reg32 offset="0xb309" name="SP_TP_MODE_CNTL">
3430
<bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>
3431
<bitfield name="UNK3" low="2" high="7"/>
3435
Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
3436
badly named or the functionality moved in a6xx. But downstream kernel
3437
calls this "a6xx_sp_ps_tp_2d_cluster"
3439
<reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
3440
<reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
3441
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
3442
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3444
<reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16"/>
3445
<reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
3446
<bitfield name="UNK0" low="0" high="8"/>
3447
<bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
3450
<!-- planes for NV12, etc. (TODO: not tested) -->
3451
<reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16"/>
3452
<reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint"/>
3453
<reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16"/>
3455
<reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16"/>
3456
<reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/>
3458
<reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31"/>
3459
<reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31"/>
3460
<reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30"/>
3461
<reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29"/>
3462
<reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy"/>
3464
<!-- always 0x100000 or 0x1000000? -->
3465
<reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25"/>
3466
<reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
3467
<reg32 offset="0xb602" name="TPL1_UNKNOWN_B602" low="0" high="7" type="uint"/>
3468
<reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL">
3469
<bitfield name="MODE" pos="0" type="boolean"/>
3470
<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
3471
<bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
3472
<bitfield name="UPPER_BIT" pos="4" type="uint"/>
3473
<bitfield name="UNK6" low="6" high="7"/>
3475
<reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint"/> <!-- always 0x0 or 0x44 ? -->
3476
<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29"/>
3477
<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29"/>
3478
<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29"/>
3479
<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29"/>
3480
<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29"/>
3481
<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12"/>
3483
<!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
3485
<bitset name="a6xx_hlsq_xs_cntl" inline="yes">
3486
<bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
3487
<bitfield name="ENABLED" pos="8" type="boolean"/>
3490
<reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3491
<reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3492
<reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3493
<reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3495
<reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>
3496
<reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/>
3497
<reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/>
3499
<reg32 offset="0xb980" name="HLSQ_FS_CNTL_0">
3500
<!-- must match SP_FS_CTRL -->
3501
<bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/>
3502
<bitfield name="VARYINGS" pos="1" type="boolean"/>
3503
<bitfield name="UNK2" low="2" high="11"/>
3505
<reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean"/> <!-- never used by blob -->
3507
<reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2">
3508
<!-- TODO: have test cases with either 0x3 or 0x7 -->
3510
<reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
3511
<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
3512
<!-- SAMPLEID is loaded into a half-precision register: -->
3513
<bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
3514
<bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
3516
SIZE is the "size" of the primitive, ie. what the i/j coords need
3517
to be divided by to scale to a single fragment. It is probably
3518
the longer of the two lines that form the tri (ie v0v1 and v0v2)?
3520
<bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
3522
<reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
3523
<!-- register loaded with position (bary.f) -->
3524
<bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
3525
<bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
3526
<bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
3527
<bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
3529
<reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
3530
<bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
3531
<bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
3532
<bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
3533
<bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
3535
<reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
3536
<bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>
3537
<bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/>
3539
<reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3541
<!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
3542
<reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
3543
<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
3544
<!-- localsize is value minus one: -->
3545
<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
3546
<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
3547
<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
3549
<reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
3550
<bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
3552
<reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
3553
<bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
3555
<reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
3556
<bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
3558
<reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
3559
<bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
3561
<reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
3562
<bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
3564
<reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
3565
<bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
3567
<reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
3568
<!-- these are all vec3. first 3 need to be high regs
3569
WGSIZECONSTID is the local size (from HLSQ_CS_NDRANGE_0)
3570
WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID
3572
<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3573
<bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
3574
<bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
3575
<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3577
<reg32 offset="0xb998" name="HLSQ_CS_CNTL_1">
3578
<!-- gl_LocalInvocationIndex -->
3579
<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
3580
<!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
3581
one of those 6 "SP cores" -->
3582
<bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
3583
<!-- Must match SP_CS_CTRL -->
3584
<bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
3585
<!-- 1 thread per wave (ignored if bit9 set) -->
3586
<bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
3588
<!--note: vulkan blob doesn't use these -->
3589
<reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
3590
<reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
3591
<reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
3593
<reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/>
3594
<reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/>
3595
<reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/>
3597
<!-- mirror of SP_CS_BINDLESS_BASE -->
3598
<array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
3599
<!-- 64 alignment, 2 low bits for unknown flags (always 0x3 when enabled?) -->
3600
<reg64 offset="0" name="ADDR" type="waddress"/>
3603
<!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? -->
3604
<reg32 offset="0xb9d0" name="HLSQ_CS_UNKNOWN_B9D0">
3605
<bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/>
3606
<bitfield name="UNK5" pos="5" type="boolean"/>
3608
<bitfield name="UNK6" pos="6" type="boolean"/>
3611
<reg32 offset="0xbb00" name="HLSQ_DRAW_CMD">
3612
<bitfield name="STATE_ID" low="0" high="7"/>
3615
<reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD">
3616
<bitfield name="STATE_ID" low="0" high="7"/>
3619
<reg32 offset="0xbb02" name="HLSQ_EVENT_CMD">
3620
<!-- I think only the low bit is actually used? -->
3621
<bitfield name="STATE_ID" low="16" high="23"/>
3622
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
3625
<reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD">
3627
This register clears pending loads queued up by
3628
CP_LOAD_STATE6. Each bit resets a particular kind(s) of
3632
<!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
3633
<bitfield name="VS_STATE" pos="0" type="boolean"/>
3634
<bitfield name="HS_STATE" pos="1" type="boolean"/>
3635
<bitfield name="DS_STATE" pos="2" type="boolean"/>
3636
<bitfield name="GS_STATE" pos="3" type="boolean"/>
3637
<bitfield name="FS_STATE" pos="4" type="boolean"/>
3638
<bitfield name="CS_STATE" pos="5" type="boolean"/>
3640
<bitfield name="CS_IBO" pos="6" type="boolean"/>
3641
<bitfield name="GFX_IBO" pos="7" type="boolean"/>
3643
<!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
3644
<bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/>
3645
<bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/>
3647
<!-- SS6_BINDLESS: one bit per bindless base -->
3648
<bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/>
3649
<bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/>
3652
<reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3654
<reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS">
3656
Shared constants are intended to be used for Vulkan push
3657
constants. When enabled, 8 vec4's are reserved in the FS
3658
const pool and 16 in the geometry const pool although
3659
only 8 are actually used (why?) and they are mapped to
3660
c504-c511 in each stage. Both VS and FS shared consts
3661
are written using ST6_CONSTANTS/SB6_IBO, so that both
3662
the geometry and FS shared consts can be written at once
3663
by using CP_LOAD_STATE6 rather than
3664
CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition
3665
DST_OFF and NUM_UNIT are in units of dwords instead of
3668
There is also a separate shared constant pool for CS,
3669
which is loaded through CP_LOAD_STATE6_FRAG with
3670
ST6_UBO/ST6_IBO. However the only real difference for CS
3673
<bitfield name="ENABLE" pos="0" type="boolean"/>
3676
<!-- mirror of SP_BINDLESS_BASE -->
3677
<array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
3678
<!-- align 64 with two LSB for unknown flags (always 0x3 enabled) -->
3679
<reg64 offset="0" name="ADDR" type="address"/>
3682
<reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD">
3683
<bitfield name="STATE_ID" low="8" high="15"/>
3684
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
3687
<reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/> <!-- all bits valid except bit 29 -->
3688
<reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6"/>
3689
<reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
3690
<reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
3691
<reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/>
3692
<array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
3694
<!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
3695
<reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
3698
These special registers signal the beginning/end of an event
3699
sequence. The sequence used internally for an event looks like:
3700
- write EVENT_CMD pipe register
3701
- write CP_EVENT_START
3702
- write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
3703
- write PC_EVENT_CMD with event or PC_DRAW_CMD
3704
- write HLSQ_EVENT_CMD(CONTEXT_DONE)
3705
- write PC_EVENT_CMD(CONTEXT_DONE)
3706
- write CP_EVENT_END
3707
Writing to CP_EVENT_END seems to actually trigger the context roll
3709
<reg32 offset="0xd600" name="CP_EVENT_START">
3710
<bitfield name="STATE_ID" low="0" high="7"/>
3712
<reg32 offset="0xd601" name="CP_EVENT_END">
3713
<bitfield name="STATE_ID" low="0" high="7"/>
3715
<reg32 offset="0xd700" name="CP_2D_EVENT_START">
3716
<bitfield name="STATE_ID" low="0" high="7"/>
3718
<reg32 offset="0xd701" name="CP_2D_EVENT_END">
3719
<bitfield name="STATE_ID" low="0" high="7"/>
3723
<!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3724
<domain name="A6XX_TEX_SAMP" width="32">
3725
<doc>Texture sampler dwords</doc>
3726
<enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3727
<value name="A6XX_TEX_NEAREST" value="0"/>
3728
<value name="A6XX_TEX_LINEAR" value="1"/>
3729
<value name="A6XX_TEX_ANISO" value="2"/>
3730
<value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
3732
<enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3733
<value name="A6XX_TEX_REPEAT" value="0"/>
3734
<value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
3735
<value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
3736
<value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
3737
<value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
3739
<enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3740
<value name="A6XX_TEX_ANISO_1" value="0"/>
3741
<value name="A6XX_TEX_ANISO_2" value="1"/>
3742
<value name="A6XX_TEX_ANISO_4" value="2"/>
3743
<value name="A6XX_TEX_ANISO_8" value="3"/>
3744
<value name="A6XX_TEX_ANISO_16" value="4"/>
3746
<enum name="a6xx_reduction_mode">
3747
<value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
3748
<value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
3749
<value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
3752
<reg32 offset="0" name="0">
3753
<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
3754
<bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
3755
<bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
3756
<bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
3757
<bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
3758
<bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
3759
<bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
3760
<bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3762
<reg32 offset="1" name="1">
3763
<bitfield name="CLAMPENABLE" pos="0" type="boolean">
3765
clamp result to [0, 1] if the format is unorm or
3766
[-1, 1] if the format is snorm, *after*
3767
filtering. Has no effect for other formats.
3770
<bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
3771
<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
3772
<bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
3773
<bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
3774
<bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
3775
<bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
3777
<reg32 offset="2" name="2">
3778
<bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
3779
<bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>
3780
<bitfield name="BCOLOR" low="7" high="31"/>
3782
<reg32 offset="3" name="3"/>
3785
<domain name="A6XX_TEX_CONST" width="32">
3786
<doc>Texture constant dwords</doc>
3787
<enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3788
<value name="A6XX_TEX_X" value="0"/>
3789
<value name="A6XX_TEX_Y" value="1"/>
3790
<value name="A6XX_TEX_Z" value="2"/>
3791
<value name="A6XX_TEX_W" value="3"/>
3792
<value name="A6XX_TEX_ZERO" value="4"/>
3793
<value name="A6XX_TEX_ONE" value="5"/>
3795
<enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3796
<value name="A6XX_TEX_1D" value="0"/>
3797
<value name="A6XX_TEX_2D" value="1"/>
3798
<value name="A6XX_TEX_CUBE" value="2"/>
3799
<value name="A6XX_TEX_3D" value="3"/>
3800
<value name="A6XX_TEX_BUFFER" value="4"/>
3802
<reg32 offset="0" name="0">
3803
<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3804
<bitfield name="SRGB" pos="2" type="boolean"/>
3805
<bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
3806
<bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
3807
<bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
3808
<bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
3809
<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
3810
<!-- overlaps with MIPLVLS -->
3811
<bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
3812
<bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
3813
<bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
3814
<bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3815
<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
3817
<reg32 offset="1" name="1">
3818
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
3819
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3821
<reg32 offset="2" name="2">
3823
b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3824
of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3826
b31 is probably the 'BUFFER' bit.. it is the one that changes
3827
behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
3829
<bitfield name="BUFFER" pos="4" type="boolean"/>
3830
<!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
3831
<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
3832
<doc>Pitch in bytes (so actually stride)</doc>
3833
<bitfield name="PITCH" low="7" high="28" type="uint"/>
3834
<bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>
3836
<reg32 offset="3" name="3">
3838
ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3839
for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3840
layer size at the point that it stops being reduced moving to
3841
higher (smaller) mipmap levels
3843
<bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3844
<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
3846
by default levels with w < 16 are linear
3847
TILE_ALL makes all levels have tiling
3848
seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
3850
<bitfield name="TILE_ALL" pos="27" type="boolean"/>
3851
<bitfield name="FLAG" pos="28" type="boolean"/>
3853
<!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
3854
the address of the non-flag base buffer is determined automatically,
3855
and must follow the flag buffer
3857
<reg32 offset="4" name="4">
3858
<bitfield name="BASE_LO" low="5" high="31" shr="5"/>
3860
<reg32 offset="5" name="5">
3861
<bitfield name="BASE_HI" low="0" high="16"/>
3862
<bitfield name="DEPTH" low="17" high="29" type="uint"/>
3864
<reg32 offset="6" name="6">
3865
<!-- pitch for plane 2 / plane 3 -->
3866
<bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
3868
<!-- 7/8 is plane 2 address for planar formats -->
3869
<reg32 offset="7" name="7">
3870
<bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
3872
<reg32 offset="8" name="8">
3873
<bitfield name="FLAG_HI" low="0" high="16"/>
3875
<!-- 9/10 is plane 3 address for planar formats -->
3876
<reg32 offset="9" name="9">
3877
<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3879
<reg32 offset="10" name="10">
3880
<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3881
<!-- log2 size of the first level, required for mipmapping -->
3882
<bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
3883
<bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
3885
<reg32 offset="11" name="11"/>
3886
<reg32 offset="12" name="12"/>
3887
<reg32 offset="13" name="13"/>
3888
<reg32 offset="14" name="14"/>
3889
<reg32 offset="15" name="15"/>
3892
<domain name="A6XX_UBO" width="32">
3893
<reg32 offset="0" name="0">
3894
<bitfield name="BASE_LO" low="0" high="31"/>
3896
<reg32 offset="1" name="1">
3897
<bitfield name="BASE_HI" low="0" high="16"/>
3898
<bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
3902
<domain name="A6XX_PDC" width="32">
3903
<reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3904
<reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3905
<reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3906
<reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3907
<reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3908
<reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3909
<reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3910
<reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3911
<reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3912
<reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3913
<reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3914
<reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3915
<reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3916
<reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3917
<reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3918
<reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3919
<reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3920
<reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3921
<reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3922
<reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3923
<reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3924
<reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3925
<reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3926
<reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3927
<reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3928
<reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3931
<domain name="A6XX_PDC_GPU_SEQ" width="32">
3932
<reg32 offset="0x0" name="MEM_0"/>
3935
<domain name="A6XX_CX_DBGC" width="32">
3936
<reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3937
<bitfield high="7" low="0" name="PING_INDEX"/>
3938
<bitfield high="15" low="8" name="PING_BLK_SEL"/>
3940
<reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3941
<reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3942
<reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3943
<reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3944
<bitfield high="5" low="0" name="TRACEEN"/>
3945
<bitfield high="14" low="12" name="GRANU"/>
3946
<bitfield high="31" low="28" name="SEGT"/>
3948
<reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
3949
<bitfield high="27" low="24" name="ENABLE"/>
3951
<reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
3952
<reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
3953
<reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
3954
<reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
3955
<reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
3956
<reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
3957
<reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
3958
<reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
3959
<reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
3960
<bitfield high="3" low="0" name="BYTEL0"/>
3961
<bitfield high="7" low="4" name="BYTEL1"/>
3962
<bitfield high="11" low="8" name="BYTEL2"/>
3963
<bitfield high="15" low="12" name="BYTEL3"/>
3964
<bitfield high="19" low="16" name="BYTEL4"/>
3965
<bitfield high="23" low="20" name="BYTEL5"/>
3966
<bitfield high="27" low="24" name="BYTEL6"/>
3967
<bitfield high="31" low="28" name="BYTEL7"/>
3969
<reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
3970
<bitfield high="3" low="0" name="BYTEL8"/>
3971
<bitfield high="7" low="4" name="BYTEL9"/>
3972
<bitfield high="11" low="8" name="BYTEL10"/>
3973
<bitfield high="15" low="12" name="BYTEL11"/>
3974
<bitfield high="19" low="16" name="BYTEL12"/>
3975
<bitfield high="23" low="20" name="BYTEL13"/>
3976
<bitfield high="27" low="24" name="BYTEL14"/>
3977
<bitfield high="31" low="28" name="BYTEL15"/>
3980
<reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
3981
<reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
3984
<domain name="A6XX_CX_MISC" width="32">
3985
<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
3986
<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
added
removed
src/freedreno/registers/adreno/a6xx.xml
