3
* Copyright © 2018 Intel Corporation
5
* Permission is hereby granted, free of charge, to any person obtaining a
6
* copy of this software and associated documentation files (the "Software"),
7
* to deal in the Software without restriction, including without limitation
8
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9
* and/or sell copies of the Software, and to permit persons to whom the
10
* Software is furnished to do so, subject to the following conditions:
12
* The above copyright notice and this permission notice (including the next
13
* paragraph) shall be included in all copies or substantial portions of the
16
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34
void yyerror (struct YYLTYPE *, char *);
36
void yyerror (char *);
41
#define YYLTYPE YYLTYPE
42
typedef struct YYLTYPE
58
message(enum message_level level, YYLTYPE *location,
61
static const char *level_str[] = { "warning", "error" };
65
fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
67
location->first_column, level_str[level]);
69
fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
72
vfprintf(stderr, fmt, args);
76
#define warn(flag, l, fmt, ...) \
78
if (warning_flags & WARN_ ## flag) \
79
message(WARN, l, fmt, ## __VA_ARGS__); \
82
#define error(l, fmt, ...) \
84
message(ERROR, l, fmt, ## __VA_ARGS__); \
88
isPowerofTwo(unsigned int x)
90
return x && (!(x & (x - 1)));
94
set_direct_src_operand(struct brw_reg *reg, int type)
96
return brw_reg(reg->file,
110
i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
111
struct brw_reg dest, struct brw_reg src0)
114
case BRW_OPCODE_BFREV:
115
brw_BFREV(p, dest, src0);
117
case BRW_OPCODE_CBIT:
118
brw_CBIT(p, dest, src0);
120
case BRW_OPCODE_F32TO16:
121
brw_F32TO16(p, dest, src0);
123
case BRW_OPCODE_F16TO32:
124
brw_F16TO32(p, dest, src0);
127
brw_MOV(p, dest, src0);
130
brw_FBL(p, dest, src0);
133
brw_FRC(p, dest, src0);
136
brw_FBH(p, dest, src0);
139
brw_NOT(p, dest, src0);
141
case BRW_OPCODE_RNDE:
142
brw_RNDE(p, dest, src0);
144
case BRW_OPCODE_RNDZ:
145
brw_RNDZ(p, dest, src0);
147
case BRW_OPCODE_RNDD:
148
brw_RNDD(p, dest, src0);
151
brw_LZD(p, dest, src0);
154
brw_DIM(p, dest, src0);
156
case BRW_OPCODE_RNDU:
157
fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
160
fprintf(stderr, "Unsupported unary opcode\n");
165
i965_asm_binary_instruction(int opcode,
166
struct brw_codegen *p,
172
case BRW_OPCODE_ADDC:
173
brw_ADDC(p, dest, src0, src1);
175
case BRW_OPCODE_BFI1:
176
brw_BFI1(p, dest, src0, src1);
179
brw_DP2(p, dest, src0, src1);
182
brw_DP3(p, dest, src0, src1);
185
brw_DP4(p, dest, src0, src1);
188
brw_DPH(p, dest, src0, src1);
190
case BRW_OPCODE_LINE:
191
brw_LINE(p, dest, src0, src1);
194
brw_MAC(p, dest, src0, src1);
196
case BRW_OPCODE_MACH:
197
brw_MACH(p, dest, src0, src1);
200
brw_PLN(p, dest, src0, src1);
203
brw_ROL(p, dest, src0, src1);
206
brw_ROR(p, dest, src0, src1);
208
case BRW_OPCODE_SAD2:
209
fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
211
case BRW_OPCODE_SADA2:
212
fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
214
case BRW_OPCODE_SUBB:
215
brw_SUBB(p, dest, src0, src1);
218
brw_ADD(p, dest, src0, src1);
221
/* Third parameter is conditional modifier
222
* which gets updated later
224
brw_CMP(p, dest, 0, src0, src1);
227
brw_AND(p, dest, src0, src1);
230
brw_ASR(p, dest, src0, src1);
233
brw_AVG(p, dest, src0, src1);
236
brw_OR(p, dest, src0, src1);
239
brw_SEL(p, dest, src0, src1);
242
brw_SHL(p, dest, src0, src1);
245
brw_SHR(p, dest, src0, src1);
248
brw_XOR(p, dest, src0, src1);
251
brw_MUL(p, dest, src0, src1);
254
fprintf(stderr, "Unsupported binary opcode\n");
259
i965_asm_ternary_instruction(int opcode,
260
struct brw_codegen *p,
268
brw_MAD(p, dest, src0, src1, src2);
270
case BRW_OPCODE_CSEL:
271
brw_CSEL(p, dest, src0, src1, src2);
274
brw_LRP(p, dest, src0, src1, src2);
277
brw_BFE(p, dest, src0, src1, src2);
279
case BRW_OPCODE_BFI2:
280
brw_BFI2(p, dest, src0, src1, src2);
283
fprintf(stderr, "Unsupported ternary opcode\n");
288
i965_asm_set_instruction_options(struct brw_codegen *p,
289
struct options options)
291
brw_inst_set_access_mode(p->devinfo, brw_last_inst,
292
options.access_mode);
293
brw_inst_set_mask_control(p->devinfo, brw_last_inst,
294
options.mask_control);
295
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
296
options.thread_control);
297
brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
298
options.no_dd_check);
299
brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
300
options.no_dd_clear);
301
brw_inst_set_debug_control(p->devinfo, brw_last_inst,
302
options.debug_control);
303
if (p->devinfo->ver >= 6)
304
brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
305
options.acc_wr_control);
306
brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
311
i965_asm_set_dst_nr(struct brw_codegen *p,
313
struct options options)
315
if (p->devinfo->ver <= 6) {
316
if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
317
options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
319
reg->nr |= BRW_MRF_COMPR4;
324
add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type type)
330
struct instr_label *label = rzalloc(p->mem_ctx, struct instr_label);
332
label->name = ralloc_strdup(p->mem_ctx, label_name);
333
label->offset = p->next_insn_offset;
336
list_addtail(&label->link, &instr_labels);
349
unsigned long long int llint;
351
enum brw_reg_type reg_type;
352
struct brw_codegen *program;
353
struct predicate predicate;
354
struct condition condition;
355
struct options options;
356
brw_inst *instruction;
366
%token LSQUARE RSQUARE
371
%token <integer> TYPE_B TYPE_UB
372
%token <integer> TYPE_W TYPE_UW
373
%token <integer> TYPE_D TYPE_UD
374
%token <integer> TYPE_Q TYPE_UQ
375
%token <integer> TYPE_V TYPE_UV
376
%token <integer> TYPE_F TYPE_HF
377
%token <integer> TYPE_DF TYPE_NF
378
%token <integer> TYPE_VF
381
%token <string> JUMP_LABEL
382
%token <string> JUMP_LABEL_TARGET
385
%token <integer> ADD ADD3 ADDC AND ASR AVG
386
%token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
387
%token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
388
%token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
389
%token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
390
%token <integer> GOTO
391
%token <integer> HALT
392
%token <integer> IF IFF ILLEGAL
393
%token <integer> JMPI JOIN
394
%token <integer> LINE LRP LZD
395
%token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
396
%token <integer> NENOP NOP NOT
398
%token <integer> PLN POP PUSH
399
%token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
400
%token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
401
%token <integer> WAIT WHILE
404
/* extended math functions */
405
%token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
406
%token <integer> RSQRTM SIN SINCOS SQRT
408
/* shared functions for send */
409
%token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
410
%token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
412
/* Conditional modifiers */
413
%token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
414
%token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
416
/* register Access Modes */
417
%token ALIGN1 ALIGN16
419
/* accumulator write control */
422
/* compaction control */
425
/* compression control */
426
%token COMPR COMPR4 SECHALF
428
/* mask control (WeCtrl) */
434
/* dependency control */
435
%token NODDCLR NODDCHK
443
/* predicate control */
444
%token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
445
%token <integer> ANY32H ALL32H
447
/* round instructions */
448
%token <integer> ROUND_INCREMENT
457
%token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
458
%token QTR_6N QTR_7N QTR_8N
461
%token <integer> X Y Z W
464
%token GENREGFILE MSGREGFILE
466
/* vertical stride in register region */
470
%token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
471
%token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
472
%token <integer> MASKREG
474
%token <integer> INTEGER
481
%nonassoc EMPTYEXECSIZE
484
%type <integer> execsize simple_int exp
487
/* predicate control */
488
%type <integer> predctrl predstate
489
%type <predicate> predicate
491
/* conditional modifier */
492
%type <condition> cond_mod
493
%type <integer> condModifiers
495
/* instruction options */
496
%type <options> instoptions instoption_list
497
%type <integer> instoption
500
%type <integer> writemask_x writemask_y writemask_z writemask_w
501
%type <integer> writemask
504
%type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
505
%type <integer> dstregion
507
%type <integer> saturate relativelocation rellocation
508
%type <reg> relativelocation2
511
%type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
512
%type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
513
%type <reg> indirectgenreg indirectregion
514
%type <reg> immreg src reg32 payload directgenreg_list addrparam region
515
%type <reg> region_wh directgenreg directmsgreg indirectmsgreg
516
%type <integer> swizzle
519
%type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
520
%type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
521
%type <integer> subregnum
524
%type <reg_type> reg_type imm_type
526
/* immediate values */
529
/* instruction opcodes */
530
%type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
531
%type <integer> sendop
532
%type <instruction> sendopcode
534
%type <integer> negate abs chansel math_function sharedfunction
536
%type <string> jumplabeltarget
537
%type <string> jumplabel
542
add_instruction_option(struct options *options, int option)
546
options->access_mode = BRW_ALIGN_1;
549
options->access_mode = BRW_ALIGN_16;
552
options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
555
options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
556
options->is_compr = true;
559
options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
562
options->thread_control |= BRW_THREAD_SWITCH;
565
options->thread_control |= BRW_THREAD_ATOMIC;
568
options->no_dd_check = true;
571
options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
574
options->mask_control |= BRW_MASK_DISABLE;
577
options->debug_control = BRW_DEBUG_BREAKPOINT;
580
options->mask_control |= BRW_WE_ALL;
583
options->compaction = true;
586
options->acc_wr_control = true;
589
options->end_of_thread = true;
591
/* TODO : Figure out how to set instruction group and get rid of
595
options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
598
options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
601
options->qtr_ctrl = 3;
604
options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
607
options->qtr_ctrl = BRW_COMPRESSION_NONE;
608
options->nib_ctrl = true;
611
options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
614
options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
615
options->nib_ctrl = true;
618
options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
621
options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
622
options->nib_ctrl = true;
625
options->qtr_ctrl = 3;
628
options->qtr_ctrl = 3;
629
options->nib_ctrl = true;
641
instrseq instruction SEMICOLON
642
| instrseq relocatableinstruction SEMICOLON
643
| instruction SEMICOLON
644
| relocatableinstruction SEMICOLON
645
| instrseq jumplabeltarget
649
/* Instruction Group */
653
| binaryaccinstruction
662
relocatableinstruction:
670
ILLEGAL execsize instoptions
672
brw_next_insn(p, $1);
673
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
674
i965_asm_set_instruction_options(p, $3);
678
/* Unary instruction */
680
predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
682
i965_asm_set_dst_nr(p, &$6, $8);
683
brw_set_default_access_mode(p, $8.access_mode);
684
i965_asm_unary_instruction($2, p, $6, $7);
685
brw_pop_insn_state(p);
686
i965_asm_set_instruction_options(p, $8);
687
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
690
if (p->devinfo->ver >= 7) {
691
if ($2 != BRW_OPCODE_DIM) {
692
brw_inst_set_flag_reg_nr(p->devinfo,
695
brw_inst_set_flag_subreg_nr(p->devinfo,
701
if ($7.file != BRW_IMMEDIATE_VALUE) {
702
brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
705
brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
706
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
707
// TODO: set instruction group instead of qtr and nib ctrl
708
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
711
if (p->devinfo->ver >= 7)
712
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
735
/* Binary instruction */
737
predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
739
i965_asm_set_dst_nr(p, &$6, $9);
740
brw_set_default_access_mode(p, $9.access_mode);
741
i965_asm_binary_instruction($2, p, $6, $7, $8);
742
i965_asm_set_instruction_options(p, $9);
743
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
746
if (p->devinfo->ver >= 7) {
747
brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
749
brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
753
brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
754
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
755
// TODO: set instruction group instead of qtr and nib ctrl
756
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
759
if (p->devinfo->ver >= 7)
760
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
763
brw_pop_insn_state(p);
786
/* Binary acc instruction */
787
binaryaccinstruction:
788
predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
790
i965_asm_set_dst_nr(p, &$6, $9);
791
brw_set_default_access_mode(p, $9.access_mode);
792
i965_asm_binary_instruction($2, p, $6, $7, $8);
793
brw_pop_insn_state(p);
794
i965_asm_set_instruction_options(p, $9);
795
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
798
if (p->devinfo->ver >= 7) {
799
if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
800
brw_inst_set_flag_reg_nr(p->devinfo,
803
brw_inst_set_flag_subreg_nr(p->devinfo,
809
brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
810
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
811
// TODO: set instruction group instead of qtr and nib ctrl
812
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
815
if (p->devinfo->ver >= 7)
816
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
835
/* Math instruction */
837
predicate MATH saturate math_function execsize dst src srcimm instoptions
839
brw_set_default_access_mode(p, $9.access_mode);
840
gfx6_math(p, $6, $4, $7, $8);
841
i965_asm_set_instruction_options(p, $9);
842
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
843
brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
844
// TODO: set instruction group instead
845
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
848
if (p->devinfo->ver >= 7)
849
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
852
brw_pop_insn_state(p);
874
/* NOP instruction */
882
/* Ternary operand instruction */
884
predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
886
brw_set_default_access_mode(p, $10.access_mode);
887
i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
888
brw_pop_insn_state(p);
889
i965_asm_set_instruction_options(p, $10);
890
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
893
if (p->devinfo->ver >= 7) {
894
brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
896
brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
900
brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
901
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
902
// TODO: set instruction group instead of qtr and nib ctrl
903
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
906
if (p->devinfo->ver >= 7)
907
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
920
/* Sync instruction */
922
WAIT execsize dst instoptions
924
brw_next_insn(p, $1);
925
i965_asm_set_instruction_options(p, $4);
926
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
927
brw_set_default_access_mode(p, $4.access_mode);
928
struct brw_reg dest = $3;
929
dest.swizzle = brw_swizzle_for_mask(dest.writemask);
930
if (dest.file != ARF || dest.nr != BRW_ARF_NOTIFICATION_COUNT)
931
error(&@1, "WAIT must use the notification register\n");
932
brw_set_dest(p, brw_last_inst, dest);
933
brw_set_src0(p, brw_last_inst, dest);
934
brw_set_src1(p, brw_last_inst, brw_null_reg());
935
brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
939
/* Send instruction */
941
predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
943
i965_asm_set_instruction_options(p, $8);
944
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
945
brw_set_dest(p, brw_last_inst, $4);
946
brw_set_src0(p, brw_last_inst, $5);
947
brw_inst_set_bits(brw_last_inst, 127, 96, $6);
948
brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
950
BRW_REGISTER_TYPE_UD);
951
brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
952
brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
953
// TODO: set instruction group instead of qtr and nib ctrl
954
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
957
if (p->devinfo->ver >= 7)
958
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
961
brw_pop_insn_state(p);
963
| predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
965
i965_asm_set_instruction_options(p, $9);
966
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
967
brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
968
brw_set_dest(p, brw_last_inst, $5);
969
brw_set_src0(p, brw_last_inst, $6);
970
brw_inst_set_bits(brw_last_inst, 127, 96, $7);
971
brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
973
BRW_REGISTER_TYPE_UD);
974
brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
975
brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
976
// TODO: set instruction group instead of qtr and nib ctrl
977
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
980
if (p->devinfo->ver >= 7)
981
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
984
brw_pop_insn_state(p);
986
| predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
988
i965_asm_set_instruction_options(p, $9);
989
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
990
brw_set_dest(p, brw_last_inst, $4);
991
brw_set_src0(p, brw_last_inst, $5);
992
brw_inst_set_bits(brw_last_inst, 127, 96, $7);
993
brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
994
brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
995
// TODO: set instruction group instead of qtr and nib ctrl
996
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
999
if (p->devinfo->ver >= 7)
1000
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1003
brw_pop_insn_state(p);
1005
| predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
1007
brw_next_insn(p, $2);
1008
i965_asm_set_instruction_options(p, $10);
1009
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1010
brw_set_dest(p, brw_last_inst, $4);
1011
brw_set_src0(p, brw_last_inst, $5);
1012
brw_set_src1(p, brw_last_inst, $6);
1014
if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
1015
brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
1017
brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1020
brw_inst_set_bits(brw_last_inst, 127, 96, $7);
1021
brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1022
brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1023
// TODO: set instruction group instead of qtr and nib ctrl
1024
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1027
if (p->devinfo->ver >= 7)
1028
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1031
brw_pop_insn_state(p);
1033
| predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
1035
brw_next_insn(p, $2);
1036
i965_asm_set_instruction_options(p, $10);
1037
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1038
brw_set_dest(p, brw_last_inst, $4);
1039
brw_set_src0(p, brw_last_inst, $5);
1040
brw_set_src1(p, brw_last_inst, $6);
1042
brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1043
brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1045
brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1046
brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1047
// TODO: set instruction group instead of qtr and nib ctrl
1048
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1051
if (p->devinfo->ver >= 7)
1052
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1055
brw_pop_insn_state(p);
1065
sendop { $$ = brw_next_insn(p, $1); }
1069
NULL_TOKEN { $$ = BRW_SFID_NULL; }
1070
| MATH { $$ = BRW_SFID_MATH; }
1071
| GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1072
| READ { $$ = BRW_SFID_DATAPORT_READ; }
1073
| WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1074
| URB { $$ = BRW_SFID_URB; }
1075
| THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1076
| VME { $$ = BRW_SFID_VME; }
1077
| RENDER { $$ = GFX6_SFID_DATAPORT_RENDER_CACHE; }
1078
| CONST { $$ = GFX6_SFID_DATAPORT_CONSTANT_CACHE; }
1079
| DATA { $$ = GFX7_SFID_DATAPORT_DATA_CACHE; }
1080
| PIXEL_INTERP { $$ = GFX7_SFID_PIXEL_INTERPOLATOR; }
1081
| DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1082
| CRE { $$ = HSW_SFID_CRE; }
1083
| SAMPLER { $$ = BRW_SFID_SAMPLER; }
1084
| DP_SAMPLER { $$ = GFX6_SFID_DATAPORT_SAMPLER_CACHE; }
1089
| MINUS LONG { $$ = -$2; }
1092
/* Jump instruction */
1094
predicate JMPI execsize relativelocation2 instoptions
1096
brw_next_insn(p, $2);
1097
i965_asm_set_instruction_options(p, $5);
1098
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1099
brw_set_dest(p, brw_last_inst, brw_ip_reg());
1100
brw_set_src0(p, brw_last_inst, brw_ip_reg());
1101
brw_set_src1(p, brw_last_inst, $4);
1102
brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1103
brw_inst_pred_control(p->devinfo,
1105
brw_pop_insn_state(p);
1109
/* branch instruction */
1111
predicate ENDIF execsize JUMP_LABEL instoptions
1113
add_label(p, $4, INSTR_LABEL_JIP);
1115
brw_next_insn(p, $2);
1116
i965_asm_set_instruction_options(p, $5);
1117
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1119
if (p->devinfo->ver == 6) {
1120
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1121
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1122
BRW_REGISTER_TYPE_D));
1123
brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1124
BRW_REGISTER_TYPE_D));
1125
} else if (p->devinfo->ver == 7) {
1126
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1127
BRW_REGISTER_TYPE_D));
1128
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1129
BRW_REGISTER_TYPE_D));
1130
brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1132
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1135
brw_pop_insn_state(p);
1137
| predicate ENDIF execsize relativelocation instoptions
1139
brw_next_insn(p, $2);
1140
i965_asm_set_instruction_options(p, $5);
1141
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1143
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1144
BRW_REGISTER_TYPE_D));
1145
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1146
BRW_REGISTER_TYPE_D));
1147
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1148
brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $4);
1150
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1153
brw_pop_insn_state(p);
1155
| ELSE execsize JUMP_LABEL jumplabel instoptions
1157
add_label(p, $3, INSTR_LABEL_JIP);
1158
add_label(p, $4, INSTR_LABEL_UIP);
1160
brw_next_insn(p, $1);
1161
i965_asm_set_instruction_options(p, $5);
1162
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1164
if (p->devinfo->ver == 6) {
1165
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1166
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1167
BRW_REGISTER_TYPE_D));
1168
brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1169
BRW_REGISTER_TYPE_D));
1170
} else if (p->devinfo->ver == 7) {
1171
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1172
BRW_REGISTER_TYPE_D));
1173
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1174
BRW_REGISTER_TYPE_D));
1175
brw_set_src1(p, brw_last_inst, brw_imm_w(0));
1177
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1178
BRW_REGISTER_TYPE_D));
1179
if (p->devinfo->ver < 12)
1180
brw_set_src0(p, brw_last_inst, brw_imm_d(0));
1183
| ELSE execsize relativelocation rellocation instoptions
1185
brw_next_insn(p, $1);
1186
i965_asm_set_instruction_options(p, $5);
1187
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1189
brw_set_dest(p, brw_last_inst, brw_ip_reg());
1190
brw_set_src0(p, brw_last_inst, brw_ip_reg());
1191
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1192
brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $3);
1193
brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $4);
1195
if (!p->single_program_flow)
1196
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1199
| predicate IF execsize JUMP_LABEL jumplabel instoptions
1201
add_label(p, $4, INSTR_LABEL_JIP);
1202
add_label(p, $5, INSTR_LABEL_UIP);
1204
brw_next_insn(p, $2);
1205
i965_asm_set_instruction_options(p, $6);
1206
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1208
if (p->devinfo->ver == 6) {
1209
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1210
brw_set_src0(p, brw_last_inst,
1211
vec1(retype(brw_null_reg(),
1212
BRW_REGISTER_TYPE_D)));
1213
brw_set_src1(p, brw_last_inst,
1214
vec1(retype(brw_null_reg(),
1215
BRW_REGISTER_TYPE_D)));
1216
} else if (p->devinfo->ver == 7) {
1217
brw_set_dest(p, brw_last_inst,
1218
vec1(retype(brw_null_reg(),
1219
BRW_REGISTER_TYPE_D)));
1220
brw_set_src0(p, brw_last_inst,
1221
vec1(retype(brw_null_reg(),
1222
BRW_REGISTER_TYPE_D)));
1223
brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1225
brw_set_dest(p, brw_last_inst,
1226
vec1(retype(brw_null_reg(),
1227
BRW_REGISTER_TYPE_D)));
1228
if (p->devinfo->ver < 12)
1229
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1232
brw_pop_insn_state(p);
1234
| predicate IF execsize relativelocation rellocation instoptions
1236
brw_next_insn(p, $2);
1237
i965_asm_set_instruction_options(p, $6);
1238
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1240
brw_set_dest(p, brw_last_inst, brw_ip_reg());
1241
brw_set_src0(p, brw_last_inst, brw_ip_reg());
1242
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1243
brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4);
1244
brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $5);
1246
if (!p->single_program_flow)
1247
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1250
brw_pop_insn_state(p);
1252
| predicate IFF execsize JUMP_LABEL instoptions
1254
add_label(p, $4, INSTR_LABEL_JIP);
1256
brw_next_insn(p, $2);
1257
i965_asm_set_instruction_options(p, $5);
1258
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1260
if (p->devinfo->ver == 6) {
1261
brw_set_src0(p, brw_last_inst,
1262
vec1(retype(brw_null_reg(),
1263
BRW_REGISTER_TYPE_D)));
1264
brw_set_src1(p, brw_last_inst,
1265
vec1(retype(brw_null_reg(),
1266
BRW_REGISTER_TYPE_D)));
1267
} else if (p->devinfo->ver == 7) {
1268
brw_set_dest(p, brw_last_inst,
1269
vec1(retype(brw_null_reg(),
1270
BRW_REGISTER_TYPE_D)));
1271
brw_set_src0(p, brw_last_inst,
1272
vec1(retype(brw_null_reg(),
1273
BRW_REGISTER_TYPE_D)));
1274
brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1276
brw_set_dest(p, brw_last_inst,
1277
vec1(retype(brw_null_reg(),
1278
BRW_REGISTER_TYPE_D)));
1279
if (p->devinfo->ver < 12)
1280
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1283
brw_pop_insn_state(p);
1285
| predicate IFF execsize relativelocation instoptions
1287
brw_next_insn(p, $2);
1288
i965_asm_set_instruction_options(p, $5);
1289
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1291
brw_set_dest(p, brw_last_inst, brw_ip_reg());
1292
brw_set_src0(p, brw_last_inst, brw_ip_reg());
1293
brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4);
1294
brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1296
if (!p->single_program_flow)
1297
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1300
brw_pop_insn_state(p);
1304
/* break instruction */
1306
predicate BREAK execsize JUMP_LABEL JUMP_LABEL instoptions
1308
add_label(p, $4, INSTR_LABEL_JIP);
1309
add_label(p, $5, INSTR_LABEL_UIP);
1311
brw_next_insn(p, $2);
1312
i965_asm_set_instruction_options(p, $6);
1313
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1315
if (p->devinfo->ver >= 8) {
1316
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1317
BRW_REGISTER_TYPE_D));
1318
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1320
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1321
BRW_REGISTER_TYPE_D));
1322
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1323
BRW_REGISTER_TYPE_D));
1324
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1327
brw_pop_insn_state(p);
1329
| predicate BREAK execsize relativelocation relativelocation instoptions
1331
brw_next_insn(p, $2);
1332
i965_asm_set_instruction_options(p, $6);
1333
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1335
brw_set_dest(p, brw_last_inst, brw_ip_reg());
1336
brw_set_src0(p, brw_last_inst, brw_ip_reg());
1337
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1338
brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4);
1339
brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $5);
1341
brw_pop_insn_state(p);
1343
| predicate HALT execsize JUMP_LABEL JUMP_LABEL instoptions
1345
add_label(p, $4, INSTR_LABEL_JIP);
1346
add_label(p, $5, INSTR_LABEL_UIP);
1348
brw_next_insn(p, $2);
1349
i965_asm_set_instruction_options(p, $6);
1350
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1352
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1353
BRW_REGISTER_TYPE_D));
1355
if (p->devinfo->ver >= 8) {
1356
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1358
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1359
BRW_REGISTER_TYPE_D));
1360
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1363
brw_pop_insn_state(p);
1365
| predicate CONT execsize JUMP_LABEL JUMP_LABEL instoptions
1367
add_label(p, $4, INSTR_LABEL_JIP);
1368
add_label(p, $5, INSTR_LABEL_UIP);
1370
brw_next_insn(p, $2);
1371
i965_asm_set_instruction_options(p, $6);
1372
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1373
brw_set_dest(p, brw_last_inst, brw_ip_reg());
1375
if (p->devinfo->ver >= 8) {
1376
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1378
brw_set_src0(p, brw_last_inst, brw_ip_reg());
1379
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1382
brw_pop_insn_state(p);
1384
| predicate CONT execsize relativelocation relativelocation instoptions
1386
brw_next_insn(p, $2);
1387
i965_asm_set_instruction_options(p, $6);
1388
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1389
brw_set_dest(p, brw_last_inst, brw_ip_reg());
1391
brw_set_src0(p, brw_last_inst, brw_ip_reg());
1392
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1394
brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4);
1395
brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $5);
1397
brw_pop_insn_state(p);
1401
/* loop instruction */
1403
predicate WHILE execsize JUMP_LABEL instoptions
1405
add_label(p, $4, INSTR_LABEL_JIP);
1407
brw_next_insn(p, $2);
1408
i965_asm_set_instruction_options(p, $5);
1409
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1411
if (p->devinfo->ver >= 8) {
1412
brw_set_dest(p, brw_last_inst,
1413
retype(brw_null_reg(),
1414
BRW_REGISTER_TYPE_D));
1415
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1416
} else if (p->devinfo->ver == 7) {
1417
brw_set_dest(p, brw_last_inst,
1418
retype(brw_null_reg(),
1419
BRW_REGISTER_TYPE_D));
1420
brw_set_src0(p, brw_last_inst,
1421
retype(brw_null_reg(),
1422
BRW_REGISTER_TYPE_D));
1423
brw_set_src1(p, brw_last_inst,
1426
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1427
brw_set_src0(p, brw_last_inst,
1428
retype(brw_null_reg(),
1429
BRW_REGISTER_TYPE_D));
1430
brw_set_src1(p, brw_last_inst,
1431
retype(brw_null_reg(),
1432
BRW_REGISTER_TYPE_D));
1435
brw_pop_insn_state(p);
1437
| predicate WHILE execsize relativelocation instoptions
1439
brw_next_insn(p, $2);
1440
i965_asm_set_instruction_options(p, $5);
1441
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1443
brw_set_dest(p, brw_last_inst, brw_ip_reg());
1444
brw_set_src0(p, brw_last_inst, brw_ip_reg());
1445
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1446
brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4);
1447
brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, 0);
1449
brw_pop_insn_state(p);
1451
| DO execsize instoptions
1453
brw_next_insn(p, $1);
1454
if (p->devinfo->ver < 6) {
1455
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1456
i965_asm_set_instruction_options(p, $3);
1457
brw_set_dest(p, brw_last_inst, brw_null_reg());
1458
brw_set_src0(p, brw_last_inst, brw_null_reg());
1459
brw_set_src1(p, brw_last_inst, brw_null_reg());
1461
brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1466
/* Relative location */
1473
INTEGER { $$ = $1; }
1474
| MINUS INTEGER { $$ = -$2; }
1476
| MINUS LONG { $$ = -$2; }
1481
| /* empty */ { $$ = 0; }
1492
JUMP_LABEL { $$ = $1; }
1493
| /* empty */ { $$ = NULL; }
1499
struct target_label *label = rzalloc(p->mem_ctx, struct target_label);
1501
label->name = ralloc_strdup(p->mem_ctx, $1);
1502
label->offset = p->next_insn_offset;
1504
list_addtail(&label->link, &target_labels);
1508
/* Destination register */
1515
dstreg dstregion writemask reg_type
1518
$$.vstride = BRW_VERTICAL_STRIDE_1;
1519
$$.width = BRW_WIDTH_1;
1523
$$.swizzle = BRW_SWIZZLE_NOOP;
1524
$$.subnr = $$.subnr * brw_reg_type_to_size($4);
1529
dstoperandex_typed dstregion writemask reg_type
1535
$$.subnr = $$.subnr * brw_reg_type_to_size($4);
1537
/* BSpec says "When the conditional modifier is present, updates
1538
* to the selected flag register also occur. In this case, the
1539
* register region fields of the ‘null’ operand are valid."
1541
| nullreg dstregion writemask reg_type
1544
$$.vstride = BRW_VERTICAL_STRIDE_1;
1545
$$.width = BRW_WIDTH_1;
1554
$$.type = BRW_REGISTER_TYPE_UW;
1575
$$.address_mode = BRW_ADDRESS_DIRECT;
1580
$$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1585
$$.address_mode = BRW_ADDRESS_DIRECT;
1590
$$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1594
/* Source register */
1604
case BRW_REGISTER_TYPE_UD:
1605
$$ = brw_imm_ud($1);
1607
case BRW_REGISTER_TYPE_D:
1610
case BRW_REGISTER_TYPE_UW:
1611
$$ = brw_imm_uw($1 | ($1 << 16));
1613
case BRW_REGISTER_TYPE_W:
1616
case BRW_REGISTER_TYPE_F:
1617
$$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1618
/* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
1621
case BRW_REGISTER_TYPE_V:
1624
case BRW_REGISTER_TYPE_UV:
1625
$$ = brw_imm_uv($1);
1627
case BRW_REGISTER_TYPE_VF:
1628
$$ = brw_imm_vf($1);
1630
case BRW_REGISTER_TYPE_Q:
1633
case BRW_REGISTER_TYPE_UQ:
1634
$$ = brw_imm_uq($1);
1636
case BRW_REGISTER_TYPE_DF:
1637
$$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1641
error(&@2, "Unknown immediate type %s\n",
1642
brw_reg_type_to_letters($2));
1648
directgenreg region reg_type
1650
$$ = set_direct_src_operand(&$1, $3);
1651
$$ = stride($$, $2.vstride, $2.width, $2.hstride);
1661
| indirectsrcoperand
1666
| indirectsrcoperand
1671
| indirectsrcoperand
1675
directsrcaccoperand:
1677
| accreg region reg_type
1679
$$ = set_direct_src_operand(&$1, $3);
1680
$$.vstride = $2.vstride;
1681
$$.width = $2.width;
1682
$$.hstride = $2.hstride;
1687
srcarcoperandex_typed region reg_type
1689
$$ = brw_reg($1.file,
1701
| nullreg region reg_type
1703
$$ = set_direct_src_operand(&$1, $3);
1704
$$.vstride = $2.vstride;
1705
$$.width = $2.width;
1706
$$.hstride = $2.hstride;
1710
$$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1714
srcarcoperandex_typed:
1724
negate abs indirectgenreg indirectregion swizzle reg_type
1726
$$ = brw_reg($3.file,
1738
$$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1739
// brw_reg set indirect_offset to 0 so set it to valid value
1740
$$.indirect_offset = $3.indirect_offset;
1753
negate abs directgenreg_list region swizzle reg_type
1755
$$ = brw_reg($3.file,
1770
/* Address register */
1774
memset(&$$, '\0', sizeof($$));
1775
$$.subnr = $1.subnr;
1776
$$.indirect_offset = $2;
1781
/* Register files and register numbers */
1783
INTEGER { $$ = $1; }
1788
DOT exp { $$ = $2; }
1789
| /* empty */ %prec SUBREGNUM { $$ = 0; }
1795
memset(&$$, '\0', sizeof($$));
1796
$$.file = BRW_GENERAL_REGISTER_FILE;
1803
GENREGFILE LSQUARE addrparam RSQUARE
1805
memset(&$$, '\0', sizeof($$));
1806
$$.file = BRW_GENERAL_REGISTER_FILE;
1807
$$.subnr = $3.subnr;
1808
$$.indirect_offset = $3.indirect_offset;
1815
$$.file = BRW_MESSAGE_REGISTER_FILE;
1822
MSGREGFILE LSQUARE addrparam RSQUARE
1824
memset(&$$, '\0', sizeof($$));
1825
$$.file = BRW_MESSAGE_REGISTER_FILE;
1826
$$.subnr = $3.subnr;
1827
$$.indirect_offset = $3.indirect_offset;
1834
int subnr = (p->devinfo->ver >= 8) ? 16 : 8;
1837
error(&@2, "Address sub register number %d"
1838
"out of range\n", $2);
1840
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1841
$$.nr = BRW_ARF_ADDRESS;
1850
if (p->devinfo->ver < 8)
1856
error(&@1, "Accumulator register number %d"
1857
" out of range\n", $1);
1859
memset(&$$, '\0', sizeof($$));
1860
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1861
$$.nr = BRW_ARF_ACCUMULATOR;
1869
// SNB = 1 flag reg and IVB+ = 2 flag reg
1870
int nr_reg = (p->devinfo->ver >= 7) ? 2 : 1;
1874
error(&@1, "Flag register number %d"
1875
" out of range \n", $1);
1877
error(&@2, "Flag subregister number %d"
1878
" out of range\n", $2);
1880
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1881
$$.nr = BRW_ARF_FLAG | $1;
1890
error(&@1, "Mask register number %d"
1891
" out of range\n", $1);
1893
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1894
$$.nr = BRW_ARF_MASK;
1902
int subnr = (p->devinfo->ver >= 11) ? 2 : 3;
1904
error(&@2, "Notification sub register number %d"
1905
" out of range\n", $2);
1907
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1908
$$.nr = BRW_ARF_NOTIFICATION_COUNT;
1917
error(&@1, "State register number %d"
1918
" out of range\n", $1);
1921
error(&@2, "State sub register number %d"
1922
" out of range\n", $2);
1924
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1925
$$.nr = BRW_ARF_STATE;
1931
CONTROLREG subregnum
1934
error(&@2, "control sub register number %d"
1935
" out of range\n", $2);
1937
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1938
$$.nr = BRW_ARF_CONTROL;
1944
IPREG { $$ = brw_ip_reg(); }
1948
NULL_TOKEN { $$ = brw_null_reg(); }
1955
error(&@2, "Thread control sub register number %d"
1956
" out of range\n", $2);
1958
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1959
$$.nr = BRW_ARF_TDR;
1965
PERFORMANCEREG subregnum
1968
if (p->devinfo->ver >= 10)
1970
else if (p->devinfo->ver <= 8)
1976
error(&@2, "Performance sub register number %d"
1977
" out of range\n", $2);
1979
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1980
$$.nr = BRW_ARF_TIMESTAMP;
1986
CHANNELENABLEREG subregnum
1989
error(&@1, "Channel enable register number %d"
1990
" out of range\n", $1);
1992
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1993
$$.nr = BRW_ARF_MASK;
1998
/* Immediate values */
2004
| LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
2006
$$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
2014
$$ = BRW_HORIZONTAL_STRIDE_1;
2018
if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
2019
error(&@2, "Invalid Horizontal stride %d\n", $2);
2033
$$ = stride($$, 0, 1, 0);
2037
if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2038
error(&@2, "Invalid VertStride %d\n", $2);
2040
$$ = stride($$, $2, 1, 0);
2042
| LANGLE exp COMMA exp COMMA exp RANGLE
2045
if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2046
error(&@2, "Invalid VertStride %d\n", $2);
2048
if ($4 > 16 || !isPowerofTwo($4))
2049
error(&@4, "Invalid width %d\n", $4);
2051
if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2052
error(&@6, "Invalid Horizontal stride in"
2053
" region_wh %d\n", $6);
2055
$$ = stride($$, $2, $4, $6);
2057
| LANGLE exp SEMICOLON exp COMMA exp RANGLE
2059
if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2060
error(&@2, "Invalid VertStride %d\n", $2);
2062
if ($4 > 16 || !isPowerofTwo($4))
2063
error(&@4, "Invalid width %d\n", $4);
2065
if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2066
error(&@6, "Invalid Horizontal stride in"
2067
" region_wh %d\n", $6);
2069
$$ = stride($$, $2, $4, $6);
2071
| LANGLE VxH COMMA exp COMMA exp RANGLE
2073
if ($4 > 16 || !isPowerofTwo($4))
2074
error(&@4, "Invalid width %d\n", $4);
2076
if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2077
error(&@6, "Invalid Horizontal stride in"
2078
" region_wh %d\n", $6);
2080
$$ = brw_VxH_indirect(0, 0);
2085
LANGLE exp COMMA exp RANGLE
2087
if ($2 > 16 || !isPowerofTwo($2))
2088
error(&@2, "Invalid width %d\n", $2);
2090
if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2091
error(&@4, "Invalid Horizontal stride in"
2092
" region_wh %d\n", $4);
2094
$$ = stride($$, 0, $2, $4);
2095
$$.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL;
2100
TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
2101
| TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
2102
| TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
2103
| TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
2104
| TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
2105
| TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
2106
| TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
2107
| TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; }
2108
| TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
2109
| TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
2110
| TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
2111
| TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; }
2115
reg_type { $$ = $1; }
2116
| TYPE_V { $$ = BRW_REGISTER_TYPE_V; }
2117
| TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; }
2118
| TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; }
2124
$$ = WRITEMASK_XYZW;
2126
| DOT writemask_x writemask_y writemask_z writemask_w
2128
$$ = $2 | $3 | $4 | $5;
2133
/* empty */ { $$ = 0; }
2134
| X { $$ = 1 << BRW_CHANNEL_X; }
2138
/* empty */ { $$ = 0; }
2139
| Y { $$ = 1 << BRW_CHANNEL_Y; }
2143
/* empty */ { $$ = 0; }
2144
| Z { $$ = 1 << BRW_CHANNEL_Z; }
2148
/* empty */ { $$ = 0; }
2149
| W { $$ = 1 << BRW_CHANNEL_W; }
2155
$$ = BRW_SWIZZLE_NOOP;
2159
$$ = BRW_SWIZZLE4($2, $2, $2, $2);
2161
| DOT chansel chansel chansel chansel
2163
$$ = BRW_SWIZZLE4($2, $3, $4, $5);
2174
/* Instruction prediction and modifiers */
2178
brw_push_insn_state(p);
2179
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2180
brw_set_default_flag_reg(p, 0, 0);
2181
brw_set_default_predicate_inverse(p, false);
2183
| LPAREN predstate flagreg predctrl RPAREN
2185
brw_push_insn_state(p);
2186
brw_set_default_predicate_inverse(p, $2);
2187
brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2188
brw_set_default_predicate_control(p, $4);
2193
/* empty */ { $$ = 0; }
2199
/* empty */ { $$ = BRW_PREDICATE_NORMAL; }
2200
| DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2201
| DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2202
| DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2203
| DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2218
/* Source Modification */
2220
/* empty */ { $$ = 0; }
2225
/* empty */ { $$ = 0; }
2229
/* Flag (Conditional) Modifier */
2233
$$.cond_modifier = $1;
2235
$$.flag_subreg_nr = 0;
2237
| condModifiers DOT flagreg
2239
$$.cond_modifier = $1;
2240
$$.flag_reg_nr = $3.nr;
2241
$$.flag_subreg_nr = $3.subnr;
2246
/* empty */ { $$ = BRW_CONDITIONAL_NONE; }
2261
/* empty */ { $$ = BRW_INSTRUCTION_NORMAL; }
2262
| SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2265
/* Execution size */
2267
/* empty */ %prec EMPTYEXECSIZE
2271
| LPAREN exp2 RPAREN
2273
if ($2 > 32 || !isPowerofTwo($2))
2274
error(&@2, "Invalid execution size %llu\n", $2);
2280
/* Instruction options */
2284
memset(&$$, 0, sizeof($$));
2286
| LCURLY instoption_list RCURLY
2288
memset(&$$, 0, sizeof($$));
2294
instoption_list COMMA instoption
2296
memset(&$$, 0, sizeof($$));
2298
add_instruction_option(&$$, $3);
2300
| instoption_list instoption
2302
memset(&$$, 0, sizeof($$));
2304
add_instruction_option(&$$, $2);
2308
memset(&$$, 0, sizeof($$));
2313
ALIGN1 { $$ = ALIGN1;}
2314
| ALIGN16 { $$ = ALIGN16; }
2315
| ACCWREN { $$ = ACCWREN; }
2316
| SECHALF { $$ = SECHALF; }
2317
| COMPR { $$ = COMPR; }
2318
| COMPR4 { $$ = COMPR4; }
2319
| BREAKPOINT { $$ = BREAKPOINT; }
2320
| NODDCLR { $$ = NODDCLR; }
2321
| NODDCHK { $$ = NODDCHK; }
2322
| MASK_DISABLE { $$ = MASK_DISABLE; }
2324
| SWITCH { $$ = SWITCH; }
2325
| ATOMIC { $$ = ATOMIC; }
2326
| CMPTCTRL { $$ = CMPTCTRL; }
2327
| WECTRL { $$ = WECTRL; }
2328
| QTR_2Q { $$ = QTR_2Q; }
2329
| QTR_3Q { $$ = QTR_3Q; }
2330
| QTR_4Q { $$ = QTR_4Q; }
2331
| QTR_2H { $$ = QTR_2H; }
2332
| QTR_2N { $$ = QTR_2N; }
2333
| QTR_3N { $$ = QTR_3N; }
2334
| QTR_4N { $$ = QTR_4N; }
2335
| QTR_5N { $$ = QTR_5N; }
2336
| QTR_6N { $$ = QTR_6N; }
2337
| QTR_7N { $$ = QTR_7N; }
2338
| QTR_8N { $$ = QTR_8N; }
2343
extern int yylineno;
2347
yyerror(YYLTYPE *ltype, char *msg)
2353
fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2354
input_filename, yylineno, msg, lex_text());
added
removed
src/intel/tools/i965_gram.y
