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* Copyright © 2020 Valve Corporation
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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BEGIN_TEST(validate.sdwa.allow)
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for (unsigned i = GFX8; i <= GFX10; i++) {
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//>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
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if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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//>> Validation results:
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SDWA_instruction *sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa();
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sdwa->neg[0] = sdwa->neg[1] = sdwa->abs[0] = sdwa->abs[1] = true;
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sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1b), inputs[0], inputs[1]).instr->sdwa();
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sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa();
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sdwa->sel[0] = SubdwordSel::sbyte2;
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sdwa->sel[1] = SubdwordSel::uword1;
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finish_validator_test();
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BEGIN_TEST(validate.sdwa.support)
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for (unsigned i = GFX7; i <= GFX10; i++) {
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//>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
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if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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//>> Validation results:
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//~gfx7! SDWA is GFX8+ only: v1: %t0 = v_mul_f32 %a, %b dst_sel:dword src0_sel:dword src1_sel:dword
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//~gfx7! Validation failed
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//~gfx([89]|10)! Validation passed
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bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
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finish_validator_test();
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BEGIN_TEST(validate.sdwa.operands)
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for (unsigned i = GFX8; i <= GFX10; i++) {
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//>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm
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if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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//>> Validation results:
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//~gfx8! Wrong source position for SGPR argument: v1: %_ = v_mul_f32 %sgpr0, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword
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//~gfx8! Wrong source position for SGPR argument: v1: %_ = v_mul_f32 %vgpr0, %sgpr1 dst_sel:dword src0_sel:dword src1_sel:dword
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bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], inputs[1]);
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bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[3]);
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//~gfx8! Wrong source position for constant argument: v1: %_ = v_mul_f32 4, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword
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//~gfx8! Wrong source position for constant argument: v1: %_ = v_mul_f32 %vgpr0, 4 dst_sel:dword src0_sel:dword src1_sel:dword
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bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(4u), inputs[1]);
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bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(4u));
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//! Literal applied on wrong instruction format: v1: %_ = v_mul_f32 0x1234, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword
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//! Literal applied on wrong instruction format: v1: %_ = v_mul_f32 %vgpr0, 0x1234 dst_sel:dword src0_sel:dword src1_sel:dword
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//! Wrong source position for Literal argument: v1: %_ = v_mul_f32 %vgpr0, 0x1234 dst_sel:dword src0_sel:dword src1_sel:dword
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bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x1234u), inputs[1]);
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bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(0x1234u));
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finish_validator_test();
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BEGIN_TEST(validate.sdwa.vopc)
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for (unsigned i = GFX8; i <= GFX10; i++) {
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//>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm
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if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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//>> Validation results:
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bld.vopc_sdwa(aco_opcode::v_cmp_gt_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]);
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//~gfx8! SDWA+VOPC definition must be fixed to vcc on GFX8: s2: %_ = v_cmp_lt_f32 %vgpr0, %vgpr1 src0_sel:dword src1_sel:dword
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bld.vopc_sdwa(aco_opcode::v_cmp_lt_f32, bld.def(bld.lm), inputs[0], inputs[1]);
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//~gfx(9|10)! SDWA VOPC clamp only supported on GFX8: s2: %_:vcc = v_cmp_eq_f32 %vgpr0, %vgpr1 clamp src0_sel:dword src1_sel:dword
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bld.vopc_sdwa(aco_opcode::v_cmp_eq_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]).instr->sdwa().clamp = true;
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//! Validation failed
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finish_validator_test();
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BEGIN_TEST(validate.sdwa.omod)
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for (unsigned i = GFX8; i <= GFX10; i++) {
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//>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm
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if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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//>> Validation results:
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//~gfx8! SDWA omod only supported on GFX9+: v1: %_ = v_mul_f32 %vgpr0, %vgpr1 *2 dst_sel:dword src0_sel:dword src1_sel:dword
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//~gfx8! Validation failed
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//~gfx(9|10)! Validation passed
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bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa().omod = 1;
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finish_validator_test();
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BEGIN_TEST(validate.sdwa.vcc)
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for (unsigned i = GFX8; i <= GFX10; i++) {
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//>> v1: %vgpr0, v1: %vgpr1, s2: %sgpr0 = p_startpgm
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if (!setup_cs("v1 v1 s2", (chip_class)i))
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//>> Validation results:
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//! 3rd operand must be fixed to vcc with SDWA: v1: %_ = v_cndmask_b32 %vgpr0, %vgpr1, %_ dst_sel:dword src0_sel:dword src1_sel:dword
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bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], inputs[2]);
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bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], bld.vcc(inputs[2]));
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//! 2nd definition must be fixed to vcc with SDWA: v1: %_, s2: %_ = v_add_co_u32 %vgpr0, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword
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bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm), inputs[0], inputs[1]);
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bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm, vcc), inputs[0], inputs[1]);
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//! Validation failed
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finish_validator_test();
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BEGIN_TEST(optimize.sdwa.extract)
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for (unsigned i = GFX7; i <= GFX10; i++) {
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for (unsigned is_signed = 0; is_signed <= 1; is_signed++) {
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//>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
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if (!setup_cs("v1 v1 s1 s1", (chip_class)i, CHIP_UNKNOWN, is_signed ? "_signed" : "_unsigned"))
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//; def standard_test(index, sel):
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//; res = 'v1: %%res%s = v_mul_f32 %%a, %%b dst_sel:dword src0_sel:dword src1_sel:%c%s\n' % (index, 's' if variant.endswith('_signed') else 'u', sel)
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//; res += 'p_unit_test %s, %%res%s' % (index, index)
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//; funcs['standard_test'] = lambda a: standard_test(*(v for v in a.split(',')))
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aco_opcode ext = aco_opcode::p_extract;
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aco_opcode ins = aco_opcode::p_insert;
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//~gfx[^7].*! @standard_test(0,byte0)
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Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u),
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Operand::c32(is_signed));
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writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte0_b));
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//~gfx[^7].*! @standard_test(1,byte1)
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Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u),
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Operand::c32(is_signed));
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writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte1_b));
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//~gfx[^7].*! @standard_test(2,byte2)
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Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), Operand::c32(8u),
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Operand::c32(is_signed));
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writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte2_b));
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//~gfx[^7].*! @standard_test(3,byte3)
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Temp bfe_byte3_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(3u), Operand::c32(8u),
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Operand::c32(is_signed));
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writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte3_b));
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//~gfx[^7].*! @standard_test(4,word0)
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Temp bfe_word0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u),
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Operand::c32(is_signed));
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writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_word0_b));
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//~gfx[^7].*! @standard_test(5,word1)
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Temp bfe_word1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u),
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Operand::c32(16u), Operand::c32(is_signed));
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writeout(5, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_word1_b));
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//~gfx[^7]_unsigned! @standard_test(6,byte0)
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Temp bfi_byte0_b = bld.pseudo(ins, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u));
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writeout(6, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_byte0_b));
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//~gfx[^7]_unsigned! @standard_test(7,word0)
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bld.pseudo(ins, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u));
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writeout(7, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_word0_b));
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//! v1: %tmp8 = p_insert %b, 1, 8
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//! v1: %res8 = v_mul_f32 %a, %tmp8
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//! p_unit_test 8, %res8
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bld.pseudo(ins, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u));
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writeout(8, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_byte1_b));
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/* v_cvt_f32_ubyte[0-3] can be used instead of v_cvt_f32_u32+sdwa */
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//~gfx7_signed! v1: %bfe_byte0_b = p_extract %b, 0, 8, 1
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//~gfx7_signed! v1: %res9 = v_cvt_f32_u32 %bfe_byte0_b
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//~gfx[^7]+_signed! v1: %res9 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte0
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//~gfx\d+_unsigned! v1: %res9 = v_cvt_f32_ubyte0 %b
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//! p_unit_test 9, %res9
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Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u),
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Operand::c32(is_signed));
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writeout(9, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte0_b));
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//~gfx7_signed! v1: %bfe_byte1_b = p_extract %b, 1, 8, 1
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//~gfx7_signed! v1: %res10 = v_cvt_f32_u32 %bfe_byte1_b
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//~gfx[^7]+_signed! v1: %res10 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte1
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//~gfx\d+_unsigned! v1: %res10 = v_cvt_f32_ubyte1 %b
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//! p_unit_test 10, %res10
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Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u),
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Operand::c32(is_signed));
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writeout(10, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte1_b));
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//~gfx7_signed! v1: %bfe_byte2_b = p_extract %b, 2, 8, 1
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//~gfx7_signed! v1: %res11 = v_cvt_f32_u32 %bfe_byte2_b
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//~gfx[^7]+_signed! v1: %res11 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte2
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//~gfx\d+_unsigned! v1: %res11 = v_cvt_f32_ubyte2 %b
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//! p_unit_test 11, %res11
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Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), Operand::c32(8u),
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Operand::c32(is_signed));
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writeout(11, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte2_b));
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//~gfx7_signed! v1: %bfe_byte3_b = p_extract %b, 3, 8, 1
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//~gfx7_signed! v1: %res12 = v_cvt_f32_u32 %bfe_byte3_b
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//~gfx[^7]+_signed! v1: %res12 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte3
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//~gfx\d+_unsigned! v1: %res12 = v_cvt_f32_ubyte3 %b
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//! p_unit_test 12, %res12
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Temp bfe_byte3_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(3u), Operand::c32(8u),
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Operand::c32(is_signed));
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writeout(12, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte3_b));
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/* VOP3-only instructions can't use SDWA but they can use opsel on GFX9+ instead */
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//~gfx(9|10).*! v1: %res13 = v_add_i16 %a, %b
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//~gfx(9|10).*! p_unit_test 13, %res13
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Temp bfe_word0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u),
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Operand::c32(is_signed));
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writeout(13, bld.vop3(aco_opcode::v_add_i16, bld.def(v1), inputs[0], bfe_word0_b));
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//~gfx(9|10).*! v1: %res14 = v_add_i16 %a, hi(%b)
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//~gfx(9|10).*! p_unit_test 14, %res14
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Temp bfe_word1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u),
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Operand::c32(16u), Operand::c32(is_signed));
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writeout(14, bld.vop3(aco_opcode::v_add_i16, bld.def(v1), inputs[0], bfe_word1_b));
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BEGIN_TEST(optimize.sdwa.extract_modifiers)
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for (unsigned i = GFX8; i <= GFX10; i++) {
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//>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
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if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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aco_opcode ext = aco_opcode::p_extract;
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//! v1: %res0 = v_mul_f32 %a, -%b dst_sel:dword src0_sel:dword src1_sel:ubyte0
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//! p_unit_test 0, %res0
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Temp byte0 = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u),
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Temp neg_byte0 = fneg(byte0);
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writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_byte0));
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//~gfx8! v1: %neg = v_mul_f32 -1.0, %b
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//~gfx8! v1: %res1 = v_mul_f32 %a, %neg dst_sel:dword src0_sel:dword src1_sel:ubyte0
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//~gfx(9|10)! v1: %neg_byte0 = v_mul_f32 -1.0, %b dst_sel:ubyte0 src0_sel:dword src1_sel:dword
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//~gfx(9|10)! v1: %res1 = v_mul_f32 %a, %neg_byte0
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//! p_unit_test 1, %res1
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Temp neg = fneg(inputs[1]);
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bld.pseudo(ext, bld.def(v1), neg, Operand::zero(), Operand::c32(8u), Operand::zero());
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writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_neg));
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//! v1: %res2 = v_mul_f32 %a, |%b| dst_sel:dword src0_sel:dword src1_sel:ubyte0
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//! p_unit_test 2, %res2
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Temp abs_byte0 = fabs(byte0);
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writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], abs_byte0));
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//! v1: %abs = v_mul_f32 1.0, |%b|
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//! v1: %res3 = v_mul_f32 %a, %abs dst_sel:dword src0_sel:dword src1_sel:ubyte0
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//! p_unit_test 3, %res3
310
Temp abs = fabs(inputs[1]);
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bld.pseudo(ext, bld.def(v1), abs, Operand::zero(), Operand::c32(8u), Operand::zero());
313
writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_abs));
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//! v1: %res4 = v_mul_f32 %1, -|%2| dst_sel:dword src0_sel:dword src1_sel:ubyte0
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//! p_unit_test 4, %res4
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Temp neg_abs_byte0 = fneg(abs_byte0);
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writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_abs_byte0));
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//~gfx8! v1: %neg_abs = v_mul_f32 -1.0, %abs
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//~gfx8! v1: %res5 = v_mul_f32 %a, %neg_abs dst_sel:dword src0_sel:dword src1_sel:ubyte0
322
//~gfx(9|10)! v1: %neg_abs_byte0 = v_mul_f32 -1.0, %abs dst_sel:ubyte0 src0_sel:dword src1_sel:dword
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//~gfx(9|10)! v1: %res5 = v_mul_f32 %a, %neg_abs_byte0
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//! p_unit_test 5, %res5
325
Temp neg_abs = fneg(abs);
327
bld.pseudo(ext, bld.def(v1), neg_abs, Operand::zero(), Operand::c32(8u), Operand::zero());
328
writeout(5, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_neg_abs));
334
BEGIN_TEST(optimize.sdwa.extract.sgpr)
335
for (unsigned i = GFX8; i <= GFX10; i++) {
336
//>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
337
if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
340
aco_opcode ext = aco_opcode::p_extract;
342
//~gfx8! v1: %byte0_b = p_extract %b, 0, 8, 0
343
//~gfx8! v1: %res1 = v_mul_f32 %c, %byte0_b
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//~gfx(9|10)! v1: %res1 = v_mul_f32 %c, %b dst_sel:dword src0_sel:dword src1_sel:ubyte0
345
//! p_unit_test 1, %res1
346
Temp byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u),
348
writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], byte0_b));
350
//~gfx8! v1: %byte0_c = p_extract %c, 0, 8, 0
351
//~gfx8! v1: %res2 = v_mul_f32 %a, %byte0_c
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//~gfx(9|10)! v1: %res2 = v_mul_f32 %a, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0
353
//! p_unit_test 2, %res2
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Temp byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u),
356
writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_c));
358
//~gfx8! v1: %byte0_c_2 = p_extract %c, 0, 8, 0
359
//~gfx8! v1: %res3 = v_mul_f32 %c, %byte0_c_2
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//~gfx(9|10)! v1: %res3 = v_mul_f32 %c, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0
361
//! p_unit_test 3, %res3
362
byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u),
364
writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], byte0_c));
366
//~gfx(8|9)! v1: %byte0_c_3 = p_extract %c, 0, 8, 0
367
//~gfx(8|9)! v1: %res4 = v_mul_f32 %d, %byte0_c_3
368
//~gfx10! v1: %res4 = v_mul_f32 %d, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0
369
//! p_unit_test 4, %res4
370
byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u),
372
writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[3], byte0_c));
378
BEGIN_TEST(optimize.sdwa.from_vop3)
379
for (unsigned i = GFX8; i <= GFX10; i++) {
380
//>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
381
if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
384
//! v1: %res0 = v_mul_f32 -|%a|, %b dst_sel:dword src0_sel:dword src1_sel:ubyte0
385
//! p_unit_test 0, %res0
386
Temp byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(),
387
Operand::c32(8u), Operand::zero());
388
VOP3_instruction *mul = &bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_b).instr->vop3();
391
writeout(0, mul->definitions[0].getTemp());
393
//~gfx8! v1: %byte0_b_0 = p_extract %b, 0, 8, 0
394
//~gfx8! v1: %res1 = v_mul_f32 %a, %byte0_b_0 *4
395
//~gfx(9|10)! v1: %res1 = v_mul_f32 %a, %b *4 dst_sel:dword src0_sel:dword src1_sel:ubyte0
396
//! p_unit_test 1, %res1
397
byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(),
398
Operand::c32(8u), Operand::zero());
399
mul = &bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_b).instr->vop3();
401
writeout(1, mul->definitions[0].getTemp());
403
//~gfx8! v1: %byte0_b_1 = p_extract %b, 0, 8, 0
404
//~gfx8! v1: %res2 = v_mul_f32 %byte0_b_1, %c
405
//~gfx(9|10)! v1: %res2 = v_mul_f32 %b, %c dst_sel:dword src0_sel:ubyte0 src1_sel:dword
406
//! p_unit_test 2, %res2
407
byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(),
408
Operand::c32(8u), Operand::zero());
409
writeout(2, bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), byte0_b, inputs[2]));
412
//~gfx10! v1: %byte0_b_2 = p_extract %b, 0, 8, 0
413
//~gfx10! v1: %res3 = v_mul_f32 %byte0_b_2, 0x1234
414
//~gfx10! p_unit_test 3, %res3
415
byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(),
416
Operand::c32(8u), Operand::zero());
418
bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), byte0_b, Operand::c32(0x1234u)));
425
BEGIN_TEST(optimize.sdwa.insert)
426
for (unsigned i = GFX7; i <= GFX10; i++) {
427
//>> v1: %a, v1: %b = p_startpgm
428
if (!setup_cs("v1 v1", (chip_class)i))
431
aco_opcode ext = aco_opcode::p_extract;
432
aco_opcode ins = aco_opcode::p_insert;
434
//~gfx[^7]! v1: %res0 = v_mul_f32 %a, %b dst_sel:ubyte0 src0_sel:dword src1_sel:dword
435
//~gfx[^7]! p_unit_test 0, %res0
436
Temp val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
437
writeout(0, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)));
439
//~gfx[^7]! v1: %res1 = v_mul_f32 %a, %b dst_sel:ubyte1 src0_sel:dword src1_sel:dword
440
//~gfx[^7]! p_unit_test 1, %res1
441
val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
442
writeout(1, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(8u)));
444
//~gfx[^7]! v1: %res2 = v_mul_f32 %a, %b dst_sel:ubyte2 src0_sel:dword src1_sel:dword
445
//~gfx[^7]! p_unit_test 2, %res2
446
val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
447
writeout(2, bld.pseudo(ins, bld.def(v1), val, Operand::c32(2u), Operand::c32(8u)));
449
//~gfx[^7]! v1: %res3 = v_mul_f32 %a, %b dst_sel:ubyte3 src0_sel:dword src1_sel:dword
450
//~gfx[^7]! p_unit_test 3, %res3
451
val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
452
writeout(3, bld.pseudo(ins, bld.def(v1), val, Operand::c32(3u), Operand::c32(8u)));
454
//~gfx[^7]! v1: %res4 = v_mul_f32 %a, %b dst_sel:uword0 src0_sel:dword src1_sel:dword
455
//~gfx[^7]! p_unit_test 4, %res4
456
val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
457
writeout(4, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(16u)));
459
//~gfx[^7]! v1: %res5 = v_mul_f32 %a, %b dst_sel:uword1 src0_sel:dword src1_sel:dword
460
//~gfx[^7]! p_unit_test 5, %res5
461
val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
462
writeout(5, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u)));
464
//~gfx[^7]! v1: %res6 = v_mul_f32 %a, %b dst_sel:ubyte0 src0_sel:dword src1_sel:dword
465
//~gfx[^7]! p_unit_test 6, %res6
466
val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
468
6, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(8u), Operand::zero()));
470
//~gfx[^7]! v1: %res7 = v_mul_f32 %a, %b dst_sel:uword0 src0_sel:dword src1_sel:dword
471
//~gfx[^7]! p_unit_test 7, %res7
472
val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
474
7, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(16u), Operand::zero()));
476
//~gfx[^7]! v1: %tmp8 = v_mul_f32 %a, %b
477
//~gfx[^7]! v1: %res8 = p_extract %tmp8, 2, 8, 0
478
//~gfx[^7]! p_unit_test 8, %res8
479
val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
481
8, bld.pseudo(ext, bld.def(v1), val, Operand::c32(2u), Operand::c32(8u), Operand::zero()));
483
//~gfx[^7]! v1: %tmp9 = v_mul_f32 %a, %b
484
//~gfx[^7]! v1: %res9 = p_extract %tmp9, 0, 8, 1
485
//~gfx[^7]! p_unit_test 9, %res9
486
val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
488
9, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(8u), Operand::c32(1u)));
493
//! v1: %res10 = v_mul_f32 %a, %b
494
//! p_unit_test 10, %res10
495
val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
496
bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u));
499
//~gfx8! v1: %tmp11 = v_sub_i16 %a, %b
500
//~gfx8! v1: %res11 = p_insert %tmp11, 0, 16
501
//~gfx(9|10)! v1: %res11 = v_sub_i16 %a, %b
502
//~gfx(8|9|10)! p_unit_test 11, %res11
503
val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]);
504
writeout(11, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(16u)));
506
//~gfx8! v1: %tmp12 = v_sub_i16 %a, %b
507
//~gfx8! v1: %res12 = p_insert %tmp12, 1, 16
508
//~gfx(9|10)! v1: %res12 = v_sub_i16 %a, %b opsel_hi
509
//~gfx(8|9|10)! p_unit_test 12, %res12
510
val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]);
511
writeout(12, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u)));
513
//~gfx[^7]! v1: %tmp13 = v_sub_i16 %a, %b
514
//~gfx[^7]! v1: %res13 = p_insert %tmp13, 0, 8
515
//~gfx[^7]! p_unit_test 13, %res13
516
val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]);
517
writeout(13, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)));
523
BEGIN_TEST(optimize.sdwa.insert_modifiers)
524
for (unsigned i = GFX8; i <= GFX9; i++) {
525
//>> v1: %a = p_startpgm
526
if (!setup_cs("v1", (chip_class)i))
529
aco_opcode ins = aco_opcode::p_insert;
531
//~gfx8! v1: %tmp0 = v_rcp_f32 %a *2
532
//~gfx8! v1: %res0 = p_insert %tmp0, 0, 8
533
//~gfx9! v1: %res0 = v_rcp_f32 %a *2 dst_sel:ubyte0 src0_sel:dword
534
//! p_unit_test 0, %res0
535
Temp val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
536
val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u));
537
writeout(0, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)));
539
//! v1: %res1 = v_rcp_f32 %a clamp dst_sel:ubyte0 src0_sel:dword
540
//! p_unit_test 1, %res1
541
val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
542
val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(),
543
Operand::c32(0x3f800000u));
544
writeout(1, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)));
546
//! v1: %tmp2 = v_rcp_f32 %a dst_sel:ubyte0 src0_sel:dword
547
//! v1: %res2 = v_mul_f32 %tmp2, 2.0
548
//! p_unit_test 2, %res2
549
val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
550
val = bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u));
551
val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u));
554
//! v1: %tmp3 = v_rcp_f32 %a dst_sel:ubyte0 src0_sel:dword
555
//! v1: %res3 = v_med3_f32 %tmp3, 0, 1.0
556
//! p_unit_test 3, %res3
557
val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
558
val = bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u));
559
val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(),
560
Operand::c32(0x3f800000u));
563
//~gfx8! v1: %tmp4 = v_rcp_f32 %a *2 clamp
564
//~gfx8! v1: %res4 = p_insert %tmp4, 0, 8
565
//~gfx9! v1: %res4 = v_rcp_f32 %a *2 clamp dst_sel:ubyte0 src0_sel:dword
566
//! p_unit_test 4, %res4
567
val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
568
val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u));
569
val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(),
570
Operand::c32(0x3f800000u));
571
writeout(4, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)));