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* Copyright © 2020 Valve Corporation
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* based on amdgpu winsys.
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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#include "radv_null_winsys_public.h"
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#include "util/u_string.h"
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#include "radv_null_bo.h"
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#include "radv_null_cs.h"
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#include "vk_sync_dummy.h"
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/* Hardcode some GPU info that are needed for the driver or for some tools. */
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uint32_t num_render_backends;
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bool has_dedicated_vram;
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[CHIP_TAHITI] = {0x6780, 8, true},
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[CHIP_PITCAIRN] = {0x6800, 8, true},
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[CHIP_VERDE] = {0x6820, 4, true},
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[CHIP_OLAND] = {0x6060, 2, true},
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[CHIP_HAINAN] = {0x6660, 2, true},
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[CHIP_BONAIRE] = {0x6640, 4, true},
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[CHIP_KAVERI] = {0x1304, 2, false},
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[CHIP_KABINI] = {0x9830, 2, false},
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[CHIP_HAWAII] = {0x67A0, 16, true},
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[CHIP_TONGA] = {0x6920, 8, true},
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[CHIP_ICELAND] = {0x6900, 2, true},
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[CHIP_CARRIZO] = {0x9870, 2, false},
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[CHIP_FIJI] = {0x7300, 16, true},
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[CHIP_STONEY] = {0x98E4, 2, false},
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[CHIP_POLARIS10] = {0x67C0, 8, true},
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[CHIP_POLARIS11] = {0x67E0, 4, true},
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[CHIP_POLARIS12] = {0x6980, 4, true},
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[CHIP_VEGAM] = {0x694C, 4, true},
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[CHIP_VEGA10] = {0x6860, 16, true},
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[CHIP_VEGA12] = {0x69A0, 8, true},
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[CHIP_VEGA20] = {0x66A0, 16, true},
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[CHIP_RAVEN] = {0x15DD, 2, false},
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[CHIP_RENOIR] = {0x1636, 2, false},
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[CHIP_ARCTURUS] = {0x738C, 2, true},
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[CHIP_NAVI10] = {0x7310, 16, true},
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[CHIP_NAVI12] = {0x7360, 8, true},
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[CHIP_NAVI14] = {0x7340, 8, true},
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[CHIP_SIENNA_CICHLID] = {0x73A0, 16, true},
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[CHIP_VANGOGH] = {0x163F, 8, false},
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[CHIP_NAVY_FLOUNDER] = {0x73C0, 8, true},
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[CHIP_DIMGREY_CAVEFISH] = {0x73E0, 8, true},
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radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
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const char *family = getenv("RADV_FORCE_FAMILY");
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info->chip_class = CLASS_UNKNOWN;
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info->family = CHIP_UNKNOWN;
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for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
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if (!strcasecmp(family, ac_get_family_name(i))) {
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/* Override family and chip_class. */
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info->name = ac_get_family_name(i);
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if (i >= CHIP_SIENNA_CICHLID)
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info->chip_class = GFX10_3;
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else if (i >= CHIP_NAVI10)
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info->chip_class = GFX10;
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else if (i >= CHIP_VEGA10)
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info->chip_class = GFX9;
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else if (i >= CHIP_TONGA)
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info->chip_class = GFX8;
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else if (i >= CHIP_BONAIRE)
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info->chip_class = GFX7;
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info->chip_class = GFX6;
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if (info->family == CHIP_UNKNOWN) {
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fprintf(stderr, "radv: Unknown family: %s\n", family);
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info->pci_id = gpu_info[info->family].pci_id;
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if (info->chip_class >= GFX10_3)
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info->max_wave64_per_simd = 16;
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else if (info->chip_class >= GFX10)
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info->max_wave64_per_simd = 20;
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else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
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info->max_wave64_per_simd = 8;
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info->max_wave64_per_simd = 10;
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if (info->chip_class >= GFX10)
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info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2;
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else if (info->chip_class >= GFX8)
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info->num_physical_sgprs_per_simd = 800;
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info->num_physical_sgprs_per_simd = 512;
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info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
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info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
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info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024;
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info->lds_encode_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4;
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info->lds_alloc_granularity =
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info->chip_class >= GFX10_3 ? 256 * 4 : info->lds_encode_granularity;
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info->max_render_backends = gpu_info[info->family].num_render_backends;
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info->has_dedicated_vram = gpu_info[info->family].has_dedicated_vram;
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info->has_packed_math_16bit = info->chip_class >= GFX9;
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info->has_image_load_dcc_bug =
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info->family == CHIP_DIMGREY_CAVEFISH || info->family == CHIP_VANGOGH;
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info->has_accelerated_dot_product =
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info->family == CHIP_ARCTURUS || info->family == CHIP_ALDEBARAN ||
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info->family == CHIP_VEGA20 || info->family >= CHIP_NAVI12;
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info->address32_hi = info->chip_class >= GFX9 ? 0xffff8000u : 0x0;
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info->has_rbplus = info->family == CHIP_STONEY || info->chip_class >= GFX9;
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info->rbplus_allowed =
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(info->family == CHIP_STONEY || info->family == CHIP_VEGA12 || info->family == CHIP_RAVEN ||
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info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->chip_class >= GFX10_3);
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radv_null_winsys_destroy(struct radeon_winsys *rws)
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radv_null_winsys_get_fd(struct radeon_winsys *rws)
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static const struct vk_sync_type *const *
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radv_null_winsys_get_sync_types(struct radeon_winsys *rws)
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return radv_null_winsys(rws)->sync_types;
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struct radeon_winsys *
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radv_null_winsys_create()
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struct radv_null_winsys *ws;
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ws = calloc(1, sizeof(struct radv_null_winsys));
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ws->base.destroy = radv_null_winsys_destroy;
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ws->base.query_info = radv_null_winsys_query_info;
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ws->base.get_fd = radv_null_winsys_get_fd;
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ws->base.get_sync_types = radv_null_winsys_get_sync_types;
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radv_null_bo_init_functions(ws);
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radv_null_cs_init_functions(ws);
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ws->sync_types[0] = &vk_sync_dummy_type;
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ws->sync_types[1] = NULL;