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/**********************************************************
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* Copyright 2008-2009 VMware, Inc. All rights reserved.
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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**********************************************************/
26
#include "git_sha1.h" /* For MESA_GIT_SHA1 */
27
#include "util/format/u_format.h"
28
#include "util/u_memory.h"
29
#include "util/u_inlines.h"
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#include "util/u_screen.h"
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#include "util/u_string.h"
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#include "util/u_math.h"
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#include "os/os_process.h"
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#include "svga_winsys.h"
37
#include "svga_public.h"
38
#include "svga_context.h"
39
#include "svga_format.h"
40
#include "svga_screen.h"
41
#include "svga_tgsi.h"
42
#include "svga_resource_texture.h"
43
#include "svga_resource.h"
44
#include "svga_debug.h"
46
#include "svga3d_shaderdefs.h"
47
#include "VGPU10ShaderTokens.h"
49
/* NOTE: this constant may get moved into a svga3d*.h header file */
50
#define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
53
#define MESA_GIT_SHA1 "(unknown git revision)"
59
static const struct debug_named_value svga_debug_flags[] = {
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{ "dma", DEBUG_DMA, NULL },
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{ "tgsi", DEBUG_TGSI, NULL },
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{ "pipe", DEBUG_PIPE, NULL },
63
{ "state", DEBUG_STATE, NULL },
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{ "screen", DEBUG_SCREEN, NULL },
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{ "tex", DEBUG_TEX, NULL },
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{ "swtnl", DEBUG_SWTNL, NULL },
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{ "const", DEBUG_CONSTS, NULL },
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{ "viewport", DEBUG_VIEWPORT, NULL },
69
{ "views", DEBUG_VIEWS, NULL },
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{ "perf", DEBUG_PERF, NULL },
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{ "flush", DEBUG_FLUSH, NULL },
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{ "sync", DEBUG_SYNC, NULL },
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{ "cache", DEBUG_CACHE, NULL },
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{ "streamout", DEBUG_STREAMOUT, NULL },
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{ "query", DEBUG_QUERY, NULL },
76
{ "samplers", DEBUG_SAMPLERS, NULL },
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{ "image", DEBUG_IMAGE, NULL },
78
{ "uav", DEBUG_UAV, NULL },
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{ "retry", DEBUG_RETRY, NULL },
85
svga_get_vendor( struct pipe_screen *pscreen )
87
return "VMware, Inc.";
92
svga_get_name( struct pipe_screen *pscreen )
94
const char *build = "", *llvm = "", *mutex = "";
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static char name[100];
97
/* Only return internal details in the DEBUG version:
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build = "build: DEBUG;";
100
mutex = "mutex: " PIPE_ATOMIC ";";
102
build = "build: RELEASE;";
104
#ifdef DRAW_LLVM_AVAILABLE
108
snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
113
/** Helper for querying float-valued device cap */
115
get_float_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
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SVGA3dDevCapResult result;
119
if (sws->get_cap(sws, cap, &result))
126
/** Helper for querying uint-valued device cap */
128
get_uint_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
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SVGA3dDevCapResult result;
132
if (sws->get_cap(sws, cap, &result))
139
/** Helper for querying boolean-valued device cap */
141
get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
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SVGA3dDevCapResult result;
145
if (sws->get_cap(sws, cap, &result))
153
svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
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struct svga_screen *svgascreen = svga_screen(screen);
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struct svga_winsys_screen *sws = svgascreen->sws;
159
case PIPE_CAPF_MIN_LINE_WIDTH:
160
case PIPE_CAPF_MIN_LINE_WIDTH_AA:
161
case PIPE_CAPF_MIN_POINT_SIZE:
162
case PIPE_CAPF_MIN_POINT_SIZE_AA:
164
case PIPE_CAPF_POINT_SIZE_GRANULARITY:
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case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
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case PIPE_CAPF_MAX_LINE_WIDTH:
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return svgascreen->maxLineWidth;
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case PIPE_CAPF_MAX_LINE_WIDTH_AA:
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return svgascreen->maxLineWidthAA;
172
case PIPE_CAPF_MAX_POINT_SIZE:
174
case PIPE_CAPF_MAX_POINT_SIZE_AA:
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return svgascreen->maxPointSize;
177
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
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return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
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case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
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case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
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case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
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case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
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debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
198
svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
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struct svga_screen *svgascreen = svga_screen(screen);
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struct svga_winsys_screen *sws = svgascreen->sws;
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SVGA3dDevCapResult result;
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
207
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
209
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
211
* "In virtually every OpenGL implementation and hardware,
212
* GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
213
* http://www.opengl.org/wiki/Blending
215
return sws->have_vgpu10 ? 1 : 0;
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case PIPE_CAP_ANISOTROPIC_FILTER:
218
case PIPE_CAP_POINT_SPRITE:
220
case PIPE_CAP_MAX_RENDER_TARGETS:
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return svgascreen->max_color_buffers;
222
case PIPE_CAP_OCCLUSION_QUERY:
224
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
225
return sws->have_vgpu10;
226
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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return sws->have_vgpu10 ? 16 : 0;
229
case PIPE_CAP_TEXTURE_SWIZZLE:
231
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
234
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
236
unsigned size = 1 << (SVGA_MAX_TEXTURE_LEVELS - 1);
237
if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
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size = MIN2(result.u, size);
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if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
242
size = MIN2(result.u, size);
248
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
250
return 8; /* max 128x128x128 */
251
return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
253
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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* No mechanism to query the host, and at least limited to 2048x2048 on
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return MIN2(util_last_bit(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_SIZE)),
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case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
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return sws->have_sm5 ? SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE :
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(sws->have_vgpu10 ? SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE : 0);
265
case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
268
case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
270
case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
271
return sws->have_vgpu10;
272
case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
273
return !sws->have_vgpu10;
275
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
276
return 1; /* The color outputs of vertex shaders are not clamped */
277
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
278
return sws->have_vgpu10;
280
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
281
return 1; /* expected for GL_ARB_framebuffer_object */
283
case PIPE_CAP_GLSL_FEATURE_LEVEL:
284
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
285
if (sws->have_gl43) {
287
} else if (sws->have_sm5) {
289
} else if (sws->have_vgpu10) {
295
case PIPE_CAP_TEXTURE_TRANSFER_MODES:
298
case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
299
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
300
case PIPE_CAP_VERTEX_SHADER_SATURATE:
303
case PIPE_CAP_DEPTH_CLIP_DISABLE:
304
case PIPE_CAP_INDEP_BLEND_ENABLE:
305
case PIPE_CAP_CONDITIONAL_RENDER:
306
case PIPE_CAP_QUERY_TIMESTAMP:
307
case PIPE_CAP_VS_INSTANCEID:
308
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
309
case PIPE_CAP_SEAMLESS_CUBE_MAP:
310
case PIPE_CAP_FAKE_SW_MSAA:
311
return sws->have_vgpu10;
313
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
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return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
315
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
316
return sws->have_vgpu10 ? 4 : 0;
317
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
318
return sws->have_sm5 ? SVGA3D_MAX_STREAMOUT_DECLS :
319
(sws->have_vgpu10 ? SVGA3D_MAX_DX10_STREAMOUT_DECLS : 0);
320
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
321
return sws->have_sm5;
322
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
323
return sws->have_sm5;
324
case PIPE_CAP_TEXTURE_MULTISAMPLE:
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return svgascreen->ms_samples ? 1 : 0;
327
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
328
/* convert bytes to texels for the case of the largest texel
331
return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
333
case PIPE_CAP_MIN_TEXEL_OFFSET:
334
return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
335
case PIPE_CAP_MAX_TEXEL_OFFSET:
336
return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
338
case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
339
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
342
case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
343
return sws->have_vgpu10 ? 256 : 0;
344
case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
345
return sws->have_vgpu10 ? 1024 : 0;
347
case PIPE_CAP_PRIMITIVE_RESTART:
348
case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
349
return 1; /* may be a sw fallback, depending on restart index */
351
case PIPE_CAP_GENERATE_MIPMAP:
352
return sws->have_generate_mipmap_cmd;
354
case PIPE_CAP_NATIVE_FENCE_FD:
355
return sws->have_fence_fd;
357
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
360
case PIPE_CAP_CUBE_MAP_ARRAY:
361
case PIPE_CAP_INDEP_BLEND_FUNC:
362
case PIPE_CAP_SAMPLE_SHADING:
363
case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
364
case PIPE_CAP_TEXTURE_QUERY_LOD:
365
return sws->have_sm4_1;
367
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
368
/* SM4_1 supports only single-channel textures where as SM5 supports
369
* all four channel textures */
370
return sws->have_sm5 ? 4 :
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(sws->have_sm4_1 ? 1 : 0);
372
case PIPE_CAP_DRAW_INDIRECT:
373
return sws->have_sm5;
374
case PIPE_CAP_MAX_VERTEX_STREAMS:
375
return sws->have_sm5 ? 4 : 0;
376
case PIPE_CAP_COMPUTE:
377
return sws->have_gl43;
378
case PIPE_CAP_MAX_VARYINGS:
379
/* According to the spec, max varyings does not include the components
380
* for position, so remove one count from the max for position.
382
return sws->have_vgpu10 ? VGPU10_MAX_FS_INPUTS-1 : 10;
383
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
384
return sws->have_coherent;
386
case PIPE_CAP_START_INSTANCE:
387
return sws->have_sm5;
388
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
389
return sws->have_sm5;
391
case PIPE_CAP_SAMPLER_VIEW_TARGET:
392
return sws->have_gl43;
394
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
395
return sws->have_gl43;
397
case PIPE_CAP_CLIP_HALFZ:
398
return sws->have_gl43;
399
case PIPE_CAP_SHAREABLE_SHADERS:
402
case PIPE_CAP_PCI_GROUP:
403
case PIPE_CAP_PCI_BUS:
404
case PIPE_CAP_PCI_DEVICE:
405
case PIPE_CAP_PCI_FUNCTION:
407
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
408
return sws->have_gl43 ? 16 : 0;
410
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
411
case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
412
return sws->have_gl43 ? SVGA_MAX_SHADER_BUFFERS : 0;
413
case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
414
case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
415
return sws->have_gl43 ? SVGA_MAX_ATOMIC_BUFFERS : 0;
416
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
418
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
419
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
420
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
421
return 1; /* need 4-byte alignment for all offsets and strides */
422
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
424
case PIPE_CAP_MAX_VIEWPORTS:
425
assert((!sws->have_vgpu10 && svgascreen->max_viewports == 1) ||
427
svgascreen->max_viewports == SVGA3D_DX_MAX_VIEWPORTS));
428
return svgascreen->max_viewports;
429
case PIPE_CAP_ENDIANNESS:
430
return PIPE_ENDIAN_LITTLE;
432
case PIPE_CAP_VENDOR_ID:
433
return 0x15ad; /* VMware Inc. */
434
case PIPE_CAP_DEVICE_ID:
435
if (sws->device_id) {
436
return sws->device_id;
438
return 0x0405; /* assume SVGA II */
440
case PIPE_CAP_ACCELERATED:
442
case PIPE_CAP_VIDEO_MEMORY:
443
/* XXX: Query the host ? */
445
case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
446
return sws->have_vgpu10;
447
case PIPE_CAP_CLEAR_TEXTURE:
448
return sws->have_vgpu10;
449
case PIPE_CAP_DOUBLES:
450
return sws->have_sm5;
452
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
453
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
455
case PIPE_CAP_TGSI_DIV:
457
case PIPE_CAP_MAX_GS_INVOCATIONS:
459
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
461
/* Verify this once protocol is finalized. Setting it to minimum value. */
462
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
463
return sws->have_sm5 ? 30 : 0;
464
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
466
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
468
case PIPE_CAP_IMAGE_STORE_FORMATTED:
469
return sws->have_gl43;
471
return u_pipe_screen_get_param_defaults(screen, param);
477
vgpu9_get_shader_param(struct pipe_screen *screen,
478
enum pipe_shader_type shader,
479
enum pipe_shader_cap param)
481
struct svga_screen *svgascreen = svga_screen(screen);
482
struct svga_winsys_screen *sws = svgascreen->sws;
485
assert(!sws->have_vgpu10);
489
case PIPE_SHADER_FRAGMENT:
492
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
493
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
494
return get_uint_cap(sws,
495
SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
497
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
498
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
500
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
501
return SVGA3D_MAX_NESTING_LEVEL;
502
case PIPE_SHADER_CAP_MAX_INPUTS:
504
case PIPE_SHADER_CAP_MAX_OUTPUTS:
505
return svgascreen->max_color_buffers;
506
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
507
return 224 * sizeof(float[4]);
508
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
510
case PIPE_SHADER_CAP_MAX_TEMPS:
511
val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
512
return MIN2(val, SVGA3D_TEMPREG_MAX);
513
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
515
* Although PS 3.0 has some addressing abilities it can only represent
516
* loops that can be statically determined and unrolled. Given we can
517
* only handle a subset of the cases that the gallium frontend already
518
* does it is better to defer loop unrolling to the gallium frontend.
521
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
523
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
525
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
526
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
527
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
529
case PIPE_SHADER_CAP_SUBROUTINES:
531
case PIPE_SHADER_CAP_INT64_ATOMICS:
532
case PIPE_SHADER_CAP_INTEGERS:
534
case PIPE_SHADER_CAP_FP16:
535
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
536
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
537
case PIPE_SHADER_CAP_INT16:
538
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
540
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
541
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
543
case PIPE_SHADER_CAP_PREFERRED_IR:
544
return PIPE_SHADER_IR_TGSI;
545
case PIPE_SHADER_CAP_SUPPORTED_IRS:
546
return 1 << PIPE_SHADER_IR_TGSI;
547
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
548
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
549
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
550
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
551
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
552
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
553
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
554
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
555
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
556
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
557
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
559
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
562
/* If we get here, we failed to handle a cap above */
563
debug_printf("Unexpected fragment shader query %u\n", param);
565
case PIPE_SHADER_VERTEX:
568
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
569
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
570
return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
572
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
573
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
574
/* XXX: until we have vertex texture support */
576
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
577
return SVGA3D_MAX_NESTING_LEVEL;
578
case PIPE_SHADER_CAP_MAX_INPUTS:
580
case PIPE_SHADER_CAP_MAX_OUTPUTS:
582
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
583
return 256 * sizeof(float[4]);
584
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
586
case PIPE_SHADER_CAP_MAX_TEMPS:
587
val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
588
return MIN2(val, SVGA3D_TEMPREG_MAX);
589
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
591
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
593
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
594
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
596
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
598
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
600
case PIPE_SHADER_CAP_SUBROUTINES:
602
case PIPE_SHADER_CAP_INT64_ATOMICS:
603
case PIPE_SHADER_CAP_INTEGERS:
605
case PIPE_SHADER_CAP_FP16:
606
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
607
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
608
case PIPE_SHADER_CAP_INT16:
609
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
611
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
612
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
614
case PIPE_SHADER_CAP_PREFERRED_IR:
615
return PIPE_SHADER_IR_TGSI;
616
case PIPE_SHADER_CAP_SUPPORTED_IRS:
617
return 1 << PIPE_SHADER_IR_TGSI;
618
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
619
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
620
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
621
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
622
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
623
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
624
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
625
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
626
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
627
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
628
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
630
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
633
/* If we get here, we failed to handle a cap above */
634
debug_printf("Unexpected vertex shader query %u\n", param);
636
case PIPE_SHADER_GEOMETRY:
637
case PIPE_SHADER_COMPUTE:
638
case PIPE_SHADER_TESS_CTRL:
639
case PIPE_SHADER_TESS_EVAL:
640
/* no support for geometry, tess or compute shaders at this time */
643
debug_printf("Unexpected shader type (%u) query\n", shader);
651
vgpu10_get_shader_param(struct pipe_screen *screen,
652
enum pipe_shader_type shader,
653
enum pipe_shader_cap param)
655
struct svga_screen *svgascreen = svga_screen(screen);
656
struct svga_winsys_screen *sws = svgascreen->sws;
658
assert(sws->have_vgpu10);
659
(void) sws; /* silence unused var warnings in non-debug builds */
661
if ((!sws->have_sm5) &&
662
(shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL))
665
if ((!sws->have_gl43) && (shader == PIPE_SHADER_COMPUTE))
668
/* NOTE: we do not query the device for any caps/limits at this time */
670
/* Generally the same limits for vertex, geometry and fragment shaders */
672
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
673
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
674
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
675
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
677
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
679
case PIPE_SHADER_CAP_MAX_INPUTS:
680
if (shader == PIPE_SHADER_FRAGMENT)
681
return VGPU10_MAX_FS_INPUTS;
682
else if (shader == PIPE_SHADER_GEOMETRY)
683
return svgascreen->max_gs_inputs;
684
else if (shader == PIPE_SHADER_TESS_CTRL)
685
return VGPU11_MAX_HS_INPUT_CONTROL_POINTS;
686
else if (shader == PIPE_SHADER_TESS_EVAL)
687
return VGPU11_MAX_DS_INPUT_CONTROL_POINTS;
689
return svgascreen->max_vs_inputs;
690
case PIPE_SHADER_CAP_MAX_OUTPUTS:
691
if (shader == PIPE_SHADER_FRAGMENT)
692
return VGPU10_MAX_FS_OUTPUTS;
693
else if (shader == PIPE_SHADER_GEOMETRY)
694
return VGPU10_MAX_GS_OUTPUTS;
695
else if (shader == PIPE_SHADER_TESS_CTRL)
696
return VGPU11_MAX_HS_OUTPUTS;
697
else if (shader == PIPE_SHADER_TESS_EVAL)
698
return VGPU11_MAX_DS_OUTPUTS;
700
return svgascreen->max_vs_outputs;
702
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
703
return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
704
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
705
return svgascreen->max_const_buffers;
706
case PIPE_SHADER_CAP_MAX_TEMPS:
707
return VGPU10_MAX_TEMPS;
708
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
709
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
710
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
711
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
712
return TRUE; /* XXX verify */
713
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
714
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
715
case PIPE_SHADER_CAP_SUBROUTINES:
716
case PIPE_SHADER_CAP_INTEGERS:
718
case PIPE_SHADER_CAP_FP16:
719
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
720
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
721
case PIPE_SHADER_CAP_INT16:
722
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
724
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
725
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
726
return sws->have_gl43 ? PIPE_MAX_SAMPLERS : SVGA3D_DX_MAX_SAMPLERS;
727
case PIPE_SHADER_CAP_PREFERRED_IR:
728
return PIPE_SHADER_IR_TGSI;
729
case PIPE_SHADER_CAP_SUPPORTED_IRS:
731
return 1 << PIPE_SHADER_IR_TGSI;
734
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
735
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
736
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
737
/* For the above cases, we rely on the GLSL compiler to translate/lower
738
* the TGIS instruction into other instructions we do support.
741
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
742
return sws->have_sm5;
744
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
745
return sws->have_gl43 ? SVGA_MAX_IMAGES : 0;
747
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
748
return sws->have_gl43 ? SVGA_MAX_SHADER_BUFFERS : 0;
750
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
751
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
752
return sws->have_gl43 ? SVGA_MAX_ATOMIC_BUFFERS : 0;
754
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
755
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
756
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
757
case PIPE_SHADER_CAP_INT64_ATOMICS:
759
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
762
debug_printf("Unexpected vgpu10 shader query %u\n", param);
770
svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
771
enum pipe_shader_cap param)
773
struct svga_screen *svgascreen = svga_screen(screen);
774
struct svga_winsys_screen *sws = svgascreen->sws;
775
if (sws->have_vgpu10) {
776
return vgpu10_get_shader_param(screen, shader, param);
779
return vgpu9_get_shader_param(screen, shader, param);
785
svga_sm5_get_compute_param(struct pipe_screen *screen,
786
enum pipe_shader_ir ir_type,
787
enum pipe_compute_cap param,
790
ASSERTED struct svga_screen *svgascreen = svga_screen(screen);
791
ASSERTED struct svga_winsys_screen *sws = svgascreen->sws;
792
uint64_t *iret = (uint64_t *)ret;
794
assert(sws->have_gl43);
795
assert(ir_type == PIPE_SHADER_IR_TGSI);
798
case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
802
return 3 * sizeof(uint64_t);
803
case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
807
return 3 * sizeof(uint64_t);
808
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
810
return sizeof(uint64_t);
811
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
813
return sizeof(uint64_t);
814
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
816
return sizeof(uint64_t);
818
debug_printf("Unexpected compute param %u\n", param);
824
svga_fence_reference(struct pipe_screen *screen,
825
struct pipe_fence_handle **ptr,
826
struct pipe_fence_handle *fence)
828
struct svga_winsys_screen *sws = svga_screen(screen)->sws;
829
sws->fence_reference(sws, ptr, fence);
834
svga_fence_finish(struct pipe_screen *screen,
835
struct pipe_context *ctx,
836
struct pipe_fence_handle *fence,
839
struct svga_winsys_screen *sws = svga_screen(screen)->sws;
842
SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
845
retVal = sws->fence_signalled(sws, fence, 0) == 0;
848
SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
849
__FUNCTION__, fence);
851
retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
854
SVGA_STATS_TIME_POP(sws);
861
svga_fence_get_fd(struct pipe_screen *screen,
862
struct pipe_fence_handle *fence)
864
struct svga_winsys_screen *sws = svga_screen(screen)->sws;
866
return sws->fence_get_fd(sws, fence, TRUE);
871
svga_get_driver_query_info(struct pipe_screen *screen,
873
struct pipe_driver_query_info *info)
875
#define QUERY(NAME, ENUM, UNITS) \
876
{NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
878
static const struct pipe_driver_query_info queries[] = {
879
/* per-frame counters */
880
QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
881
PIPE_DRIVER_QUERY_TYPE_UINT64),
882
QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
883
PIPE_DRIVER_QUERY_TYPE_UINT64),
884
QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
885
PIPE_DRIVER_QUERY_TYPE_UINT64),
886
QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
887
PIPE_DRIVER_QUERY_TYPE_UINT64),
888
QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
889
PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
890
QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
891
PIPE_DRIVER_QUERY_TYPE_UINT64),
892
QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
893
PIPE_DRIVER_QUERY_TYPE_UINT64),
894
QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
895
PIPE_DRIVER_QUERY_TYPE_BYTES),
896
QUERY("num-command-buffers", SVGA_QUERY_NUM_COMMAND_BUFFERS,
897
PIPE_DRIVER_QUERY_TYPE_UINT64),
898
QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
899
PIPE_DRIVER_QUERY_TYPE_BYTES),
900
QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
901
PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
902
QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
903
PIPE_DRIVER_QUERY_TYPE_UINT64),
904
QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
905
PIPE_DRIVER_QUERY_TYPE_UINT64),
906
QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
907
PIPE_DRIVER_QUERY_TYPE_UINT64),
908
QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
909
PIPE_DRIVER_QUERY_TYPE_UINT64),
910
QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
911
PIPE_DRIVER_QUERY_TYPE_UINT64),
912
QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
913
PIPE_DRIVER_QUERY_TYPE_UINT64),
914
QUERY("num-shader-relocations", SVGA_QUERY_NUM_SHADER_RELOCATIONS,
915
PIPE_DRIVER_QUERY_TYPE_UINT64),
916
QUERY("num-surface-relocations", SVGA_QUERY_NUM_SURFACE_RELOCATIONS,
917
PIPE_DRIVER_QUERY_TYPE_UINT64),
919
/* running total counters */
920
QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
921
PIPE_DRIVER_QUERY_TYPE_BYTES),
922
QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
923
PIPE_DRIVER_QUERY_TYPE_UINT64),
924
QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
925
PIPE_DRIVER_QUERY_TYPE_UINT64),
926
QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
927
PIPE_DRIVER_QUERY_TYPE_UINT64),
928
QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
929
PIPE_DRIVER_QUERY_TYPE_UINT64),
930
QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
931
PIPE_DRIVER_QUERY_TYPE_UINT64),
932
QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
933
PIPE_DRIVER_QUERY_TYPE_UINT64),
934
QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW,
935
PIPE_DRIVER_QUERY_TYPE_FLOAT),
936
QUERY("shader-mem-used", SVGA_QUERY_SHADER_MEM_USED,
937
PIPE_DRIVER_QUERY_TYPE_UINT64),
942
return ARRAY_SIZE(queries);
944
if (index >= ARRAY_SIZE(queries))
947
*info = queries[index];
953
init_logging(struct pipe_screen *screen)
955
struct svga_screen *svgascreen = svga_screen(screen);
956
static const char *log_prefix = "Mesa: ";
959
/* Log Version to Host */
960
snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
961
"%s%s\n", log_prefix, svga_get_name(screen));
962
svgascreen->sws->host_log(svgascreen->sws, host_log);
964
snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
965
"%s" PACKAGE_VERSION MESA_GIT_SHA1, log_prefix);
966
svgascreen->sws->host_log(svgascreen->sws, host_log);
968
/* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
969
* line (program name and arguments).
971
if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
973
if (os_get_command_line(cmdline, sizeof(cmdline))) {
974
snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
975
"%s%s\n", log_prefix, cmdline);
976
svgascreen->sws->host_log(svgascreen->sws, host_log);
983
* no-op logging function to use when SVGA_NO_LOGGING is set.
986
nop_host_log(struct svga_winsys_screen *sws, const char *message)
993
svga_destroy_screen( struct pipe_screen *screen )
995
struct svga_screen *svgascreen = svga_screen(screen);
997
svga_screen_cache_cleanup(svgascreen);
999
mtx_destroy(&svgascreen->swc_mutex);
1000
mtx_destroy(&svgascreen->tex_mutex);
1002
svgascreen->sws->destroy(svgascreen->sws);
1009
* Create a new svga_screen object
1011
struct pipe_screen *
1012
svga_screen_create(struct svga_winsys_screen *sws)
1014
struct svga_screen *svgascreen;
1015
struct pipe_screen *screen;
1018
SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
1021
svgascreen = CALLOC_STRUCT(svga_screen);
1025
svgascreen->debug.force_level_surface_view =
1026
debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
1027
svgascreen->debug.force_surface_view =
1028
debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
1029
svgascreen->debug.force_sampler_view =
1030
debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
1031
svgascreen->debug.no_surface_view =
1032
debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
1033
svgascreen->debug.no_sampler_view =
1034
debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
1035
svgascreen->debug.no_cache_index_buffers =
1036
debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
1038
screen = &svgascreen->screen;
1040
screen->destroy = svga_destroy_screen;
1041
screen->get_name = svga_get_name;
1042
screen->get_vendor = svga_get_vendor;
1043
screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
1044
screen->get_param = svga_get_param;
1045
screen->get_shader_param = svga_get_shader_param;
1046
screen->get_paramf = svga_get_paramf;
1047
screen->get_timestamp = NULL;
1048
screen->is_format_supported = svga_is_format_supported;
1049
screen->context_create = svga_context_create;
1050
screen->fence_reference = svga_fence_reference;
1051
screen->fence_finish = svga_fence_finish;
1052
screen->fence_get_fd = svga_fence_get_fd;
1054
screen->get_driver_query_info = svga_get_driver_query_info;
1056
screen->get_compute_param = svga_sm5_get_compute_param;
1058
svgascreen->sws = sws;
1060
svga_init_screen_resource_functions(svgascreen);
1062
if (sws->get_hw_version) {
1063
svgascreen->hw_version = sws->get_hw_version(sws);
1065
svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
1068
if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
1069
/* too old for 3D acceleration */
1070
debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1071
svgascreen->hw_version);
1075
if (sws->have_gl43) {
1076
svgascreen->forcedSampleCount =
1077
get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FORCED_SAMPLE_COUNT, 0);
1079
sws->have_gl43 = sws->have_gl43 && (svgascreen->forcedSampleCount >= 4);
1081
/* Allow a temporary environment variable to enable/disable GL43 support.
1084
debug_get_bool_option("SVGA_GL43", sws->have_gl43);
1086
svgascreen->debug.sampler_state_mapping =
1087
debug_get_bool_option("SVGA_SAMPLER_STATE_MAPPING", FALSE);
1090
/* sampler state mapping code is only enabled with GL43
1091
* due to the limitation in SW Renderer. (VMware bug 2825014)
1093
svgascreen->debug.sampler_state_mapping = FALSE;
1096
debug_printf("%s enabled\n",
1097
sws->have_gl43 ? "SM5+" :
1098
sws->have_sm5 ? "SM5" :
1099
sws->have_sm4_1 ? "SM4_1" :
1100
sws->have_vgpu10 ? "VGPU10" : "VGPU9");
1102
debug_printf("Mesa: %s %s (%s)\n", svga_get_name(screen),
1103
PACKAGE_VERSION, MESA_GIT_SHA1);
1106
* The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1107
* when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
1108
* we prefer the later when available.
1110
* This mimics hardware vendors extensions for D3D depth sampling. See also
1111
* http://aras-p.info/texts/D3D9GPUHacks.html
1115
boolean has_df16, has_df24, has_d24s8_int;
1116
SVGA3dSurfaceFormatCaps caps;
1117
SVGA3dSurfaceFormatCaps mask;
1122
svgascreen->depth.z16 = SVGA3D_Z_D16;
1123
svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1124
svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1126
svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1127
has_df16 = (caps.value & mask.value) == mask.value;
1129
svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1130
has_df24 = (caps.value & mask.value) == mask.value;
1132
svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1133
has_d24s8_int = (caps.value & mask.value) == mask.value;
1135
/* XXX: We might want some other logic here.
1136
* Like if we only have d24s8_int we should
1137
* emulate the other formats with that.
1140
svgascreen->depth.z16 = SVGA3D_Z_DF16;
1143
svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1145
if (has_d24s8_int) {
1146
svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1150
/* Query device caps
1152
if (sws->have_vgpu10) {
1153
svgascreen->haveProvokingVertex
1154
= get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1155
svgascreen->haveLineSmooth = TRUE;
1156
svgascreen->maxPointSize = 80.0F;
1157
svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1159
/* Multisample samples per pixel */
1160
if (sws->have_sm4_1 && debug_get_bool_option("SVGA_MSAA", TRUE)) {
1161
if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_2X, FALSE))
1162
svgascreen->ms_samples |= 1 << 1;
1163
if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_4X, FALSE))
1164
svgascreen->ms_samples |= 1 << 3;
1167
if (sws->have_sm5 && debug_get_bool_option("SVGA_MSAA", TRUE)) {
1168
if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_8X, FALSE))
1169
svgascreen->ms_samples |= 1 << 7;
1172
/* Maximum number of constant buffers */
1173
if (sws->have_gl43) {
1174
svgascreen->max_const_buffers = SVGA_MAX_CONST_BUFS;
1177
svgascreen->max_const_buffers =
1178
get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1179
svgascreen->max_const_buffers = MIN2(svgascreen->max_const_buffers,
1180
SVGA_MAX_CONST_BUFS);
1183
svgascreen->haveBlendLogicops =
1184
get_bool_cap(sws, SVGA3D_DEVCAP_LOGIC_BLENDOPS, FALSE);
1186
screen->is_format_supported = svga_is_dx_format_supported;
1188
svgascreen->max_viewports = SVGA3D_DX_MAX_VIEWPORTS;
1191
if (sws->have_sm4_1) {
1192
svgascreen->max_vs_inputs = VGPU10_1_MAX_VS_INPUTS;
1193
svgascreen->max_vs_outputs = VGPU10_1_MAX_VS_OUTPUTS;
1194
svgascreen->max_gs_inputs = VGPU10_1_MAX_GS_INPUTS;
1197
svgascreen->max_vs_inputs = VGPU10_MAX_VS_INPUTS;
1198
svgascreen->max_vs_outputs = VGPU10_MAX_VS_OUTPUTS;
1199
svgascreen->max_gs_inputs = VGPU10_MAX_GS_INPUTS;
1204
unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1205
SVGA3DVSVERSION_NONE);
1206
unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1207
SVGA3DPSVERSION_NONE);
1209
/* we require Shader model 3.0 or later */
1210
if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1214
svgascreen->haveProvokingVertex = FALSE;
1216
svgascreen->haveLineSmooth =
1217
get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1219
svgascreen->maxPointSize =
1220
get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1221
/* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1222
svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1224
/* The SVGA3D device always supports 4 targets at this time, regardless
1225
* of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1227
svgascreen->max_color_buffers = 4;
1229
/* Only support one constant buffer
1231
svgascreen->max_const_buffers = 1;
1233
/* No multisampling */
1234
svgascreen->ms_samples = 0;
1236
/* Only one viewport */
1237
svgascreen->max_viewports = 1;
1240
svgascreen->max_vs_inputs = 16;
1241
svgascreen->max_vs_outputs = 10;
1242
svgascreen->max_gs_inputs = 0;
1245
/* common VGPU9 / VGPU10 caps */
1246
svgascreen->haveLineStipple =
1247
get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1249
svgascreen->maxLineWidth =
1250
MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1252
svgascreen->maxLineWidthAA =
1253
MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1256
debug_printf("svga: haveProvokingVertex %u\n",
1257
svgascreen->haveProvokingVertex);
1258
debug_printf("svga: haveLineStip %u "
1259
"haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1260
svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1261
svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1262
debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1263
debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1266
(void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1267
(void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1269
svga_screen_cache_init(svgascreen);
1271
if (debug_get_bool_option("SVGA_NO_LOGGING", FALSE) == TRUE) {
1272
svgascreen->sws->host_log = nop_host_log;
1274
init_logging(screen);
1285
struct svga_winsys_screen *
1286
svga_winsys_screen(struct pipe_screen *screen)
1288
return svga_screen(screen)->sws;
1293
struct svga_screen *
1294
svga_screen(struct pipe_screen *screen)
1297
assert(screen->destroy == svga_destroy_screen);
1298
return (struct svga_screen *)screen;
added
removed
src/gallium/drivers/svga/svga_screen.c
