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* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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#include "r600_pipe.h"
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#include "r600_public.h"
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#include "evergreen_compute.h"
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#include "sb/sb_public.h"
32
#include "pipe/p_shader_tokens.h"
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#include "util/u_debug.h"
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#include "util/u_memory.h"
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#include "util/u_screen.h"
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#include "util/u_simple_shaders.h"
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#include "util/u_upload_mgr.h"
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#include "util/u_math.h"
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#include "vl/vl_decoder.h"
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#include "vl/vl_video_buffer.h"
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#include "radeon_video.h"
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#include "radeon_uvd.h"
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#include "util/os_time.h"
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static const struct debug_named_value r600_debug_options[] = {
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{ "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
50
{ "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
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{ "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
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{ "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
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{ "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
54
{ "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
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{ "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
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{ "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
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{ "nirsb", DBG_NIR_SB, "Enable NIR with SB optimizer"},
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DEBUG_NAMED_VALUE_END /* must be last */
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static void r600_destroy_context(struct pipe_context *context)
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struct r600_context *rctx = (struct r600_context *)context;
71
r600_isa_destroy(rctx->isa);
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r600_sb_context_destroy(rctx->sb_context);
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for (sh = 0; sh < (rctx->b.chip_class < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) {
76
r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL);
78
r600_resource_reference(&rctx->dummy_cmask, NULL);
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r600_resource_reference(&rctx->dummy_fmask, NULL);
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if (rctx->append_fence)
82
pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
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for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
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rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, false, NULL);
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free(rctx->driver_consts[sh].constants);
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if (rctx->fixed_func_tcs_shader)
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rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
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if (rctx->dummy_pixel_shader) {
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rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
94
if (rctx->custom_dsa_flush) {
95
rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
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if (rctx->custom_blend_resolve) {
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rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
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if (rctx->custom_blend_decompress) {
101
rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
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if (rctx->custom_blend_fastclear) {
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rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
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util_unreference_framebuffer_state(&rctx->framebuffer.state);
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if (rctx->gs_rings.gsvs_ring.buffer)
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pipe_resource_reference(&rctx->gs_rings.gsvs_ring.buffer, NULL);
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if (rctx->gs_rings.esgs_ring.buffer)
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pipe_resource_reference(&rctx->gs_rings.esgs_ring.buffer, NULL);
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for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh)
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for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i)
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rctx->b.b.set_constant_buffer(context, sh, i, false, NULL);
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util_blitter_destroy(rctx->blitter);
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u_suballocator_destroy(&rctx->allocator_fetch_shader);
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r600_release_command_buffer(&rctx->start_cs_cmd);
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FREE(rctx->start_compute_cs_cmd.buf);
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r600_common_context_cleanup(&rctx->b);
129
r600_resource_reference(&rctx->trace_buf, NULL);
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r600_resource_reference(&rctx->last_trace_buf, NULL);
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radeon_clear_saved_cs(&rctx->last_gfx);
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static struct pipe_context *r600_create_context(struct pipe_screen *screen,
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void *priv, unsigned flags)
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struct r600_context *rctx = CALLOC_STRUCT(r600_context);
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struct r600_screen* rscreen = (struct r600_screen *)screen;
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struct radeon_winsys *ws = rscreen->b.ws;
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rctx->b.b.screen = screen;
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rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
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rctx->b.b.destroy = r600_destroy_context;
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rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
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if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
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rctx->screen = rscreen;
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list_inithead(&rctx->texture_buffers);
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r600_init_blit_functions(rctx);
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if (rscreen->b.info.has_video_hw.uvd_decode) {
161
rctx->b.b.create_video_codec = r600_uvd_create_decoder;
162
rctx->b.b.create_video_buffer = r600_video_buffer_create;
164
rctx->b.b.create_video_codec = vl_create_decoder;
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rctx->b.b.create_video_buffer = vl_video_buffer_create;
168
if (getenv("R600_TRACE"))
169
rctx->is_debug = true;
170
r600_init_common_state_functions(rctx);
172
switch (rctx->b.chip_class) {
175
r600_init_state_functions(rctx);
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r600_init_atom_start_cs(rctx);
177
rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
178
rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
179
: r600_create_resolve_blend(rctx);
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rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
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rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
182
rctx->b.family == CHIP_RV620 ||
183
rctx->b.family == CHIP_RS780 ||
184
rctx->b.family == CHIP_RS880 ||
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rctx->b.family == CHIP_RV710);
189
evergreen_init_state_functions(rctx);
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evergreen_init_atom_start_cs(rctx);
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evergreen_init_atom_start_compute_cs(rctx);
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rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
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rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
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rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
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rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
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rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
197
rctx->b.family == CHIP_PALM ||
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rctx->b.family == CHIP_SUMO ||
199
rctx->b.family == CHIP_SUMO2 ||
200
rctx->b.family == CHIP_CAICOS ||
201
rctx->b.family == CHIP_CAYMAN ||
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rctx->b.family == CHIP_ARUBA);
204
rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
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PIPE_USAGE_DEFAULT, 32);
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R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
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ws->cs_create(&rctx->b.gfx.cs, rctx->b.ctx, RING_GFX,
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r600_context_gfx_flush, rctx, false);
214
rctx->b.gfx.flush = r600_context_gfx_flush;
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u_suballocator_init(&rctx->allocator_fetch_shader, &rctx->b.b, 64 * 1024,
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0, PIPE_USAGE_DEFAULT, 0, FALSE);
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rctx->isa = calloc(1, sizeof(struct r600_isa));
220
if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
223
if (rscreen->b.debug_flags & DBG_FORCE_DMA)
224
rctx->b.b.resource_copy_region = rctx->b.dma_copy;
226
rctx->blitter = util_blitter_create(&rctx->b.b);
227
if (rctx->blitter == NULL)
229
util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
230
rctx->blitter->draw_rectangle = r600_draw_rectangle;
232
r600_begin_new_cs(rctx);
234
rctx->dummy_pixel_shader =
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util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
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TGSI_SEMANTIC_GENERIC,
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TGSI_INTERPOLATE_CONSTANT);
238
rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
243
r600_destroy_context(&rctx->b.b);
247
static bool is_nir_enabled(struct r600_common_screen *screen) {
248
return ((screen->debug_flags & DBG_NIR_PREFERRED) &&
249
screen->family >= CHIP_CEDAR);
256
static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
258
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
259
enum radeon_family family = rscreen->b.family;
262
/* Supported features (boolean caps). */
263
case PIPE_CAP_NPOT_TEXTURES:
264
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
265
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
266
case PIPE_CAP_ANISOTROPIC_FILTER:
267
case PIPE_CAP_POINT_SPRITE:
268
case PIPE_CAP_OCCLUSION_QUERY:
269
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
270
case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
271
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
272
case PIPE_CAP_TEXTURE_SWIZZLE:
273
case PIPE_CAP_DEPTH_CLIP_DISABLE:
274
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
275
case PIPE_CAP_SHADER_STENCIL_EXPORT:
276
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
277
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
278
case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
279
case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
280
case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
281
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
282
case PIPE_CAP_VERTEX_SHADER_SATURATE:
283
case PIPE_CAP_SEAMLESS_CUBE_MAP:
284
case PIPE_CAP_PRIMITIVE_RESTART:
285
case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
286
case PIPE_CAP_CONDITIONAL_RENDER:
287
case PIPE_CAP_TEXTURE_BARRIER:
288
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
289
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
290
case PIPE_CAP_VS_INSTANCEID:
291
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
292
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
294
case PIPE_CAP_START_INSTANCE:
295
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
296
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
297
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
298
case PIPE_CAP_TEXTURE_MULTISAMPLE:
299
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
300
case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
301
case PIPE_CAP_VS_LAYER_VIEWPORT:
302
case PIPE_CAP_SAMPLE_SHADING:
303
case PIPE_CAP_CLIP_HALFZ:
304
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
305
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
306
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
307
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
308
case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
309
case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
310
case PIPE_CAP_INVALIDATE_BUFFER:
311
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
312
case PIPE_CAP_QUERY_MEMORY_INFO:
313
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
314
case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
315
case PIPE_CAP_CLEAR_TEXTURE:
316
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
317
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
318
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
319
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
320
case PIPE_CAP_NIR_ATOMICS_AS_DEREF:
323
case PIPE_CAP_TEXTURE_TRANSFER_MODES:
324
return PIPE_TEXTURE_TRANSFER_BLIT;
326
case PIPE_CAP_SHAREABLE_SHADERS:
329
case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
330
/* Optimal number for good TexSubImage performance on Polaris10. */
331
return 64 * 1024 * 1024;
333
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
334
return rscreen->b.info.drm_minor >= 43;
336
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
337
return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
339
case PIPE_CAP_COMPUTE:
340
return rscreen->b.chip_class > R700;
342
case PIPE_CAP_TGSI_TEXCOORD:
345
case PIPE_CAP_NIR_IMAGES_AS_DEREF:
346
case PIPE_CAP_FAKE_SW_MSAA:
349
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
350
return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
352
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
353
return R600_MAP_BUFFER_ALIGNMENT;
355
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
358
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
361
case PIPE_CAP_GLSL_FEATURE_LEVEL:
362
if (family >= CHIP_CEDAR)
363
return is_nir_enabled(&rscreen->b) ? 450 : 430;
364
/* pre-evergreen geom shaders need newer kernel */
365
if (rscreen->b.info.drm_minor >= 37)
369
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
372
/* Supported except the original R600. */
373
case PIPE_CAP_INDEP_BLEND_ENABLE:
374
case PIPE_CAP_INDEP_BLEND_FUNC:
375
/* R600 doesn't support per-MRT blends */
376
return family == CHIP_R600 ? 0 : 1;
378
/* Supported on Evergreen. */
379
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
380
case PIPE_CAP_CUBE_MAP_ARRAY:
381
case PIPE_CAP_TEXTURE_GATHER_SM5:
382
case PIPE_CAP_TEXTURE_QUERY_LOD:
383
case PIPE_CAP_FS_FINE_DERIVATIVE:
384
case PIPE_CAP_SAMPLER_VIEW_TARGET:
385
case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
386
case PIPE_CAP_SHADER_CLOCK:
387
case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
388
case PIPE_CAP_QUERY_BUFFER_OBJECT:
389
case PIPE_CAP_IMAGE_STORE_FORMATTED:
390
return family >= CHIP_CEDAR ? 1 : 0;
391
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
392
return family >= CHIP_CEDAR ? 4 : 0;
393
case PIPE_CAP_DRAW_INDIRECT:
394
/* kernel command checker support is also required */
395
return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
397
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
398
return family >= CHIP_CEDAR ? 0 : 1;
400
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
403
case PIPE_CAP_MAX_GS_INVOCATIONS:
406
/* shader buffer objects */
407
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
409
case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
412
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
416
case PIPE_CAP_DOUBLES:
417
if (rscreen->b.family == CHIP_ARUBA ||
418
rscreen->b.family == CHIP_CAYMAN ||
419
rscreen->b.family == CHIP_CYPRESS ||
420
rscreen->b.family == CHIP_HEMLOCK)
422
if (is_nir_enabled(&rscreen->b))
425
case PIPE_CAP_INT64_DIVMOD:
426
/* it is actually not supported, but the nir lowering hdanles this corectly wheras
427
* the glsl lowering path seems to not initialize the buildins correctly.
429
return is_nir_enabled(&rscreen->b);
430
case PIPE_CAP_CULL_DISTANCE:
433
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
434
if (family >= CHIP_CEDAR)
438
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
439
if (family >= CHIP_CEDAR)
444
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
445
return rscreen->b.has_streamout ? 4 : 0;
446
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
447
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
448
return rscreen->b.has_streamout ? 1 : 0;
449
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
450
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
453
/* Geometry shader output. */
454
case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
456
case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
458
case PIPE_CAP_MAX_VERTEX_STREAMS:
459
return family >= CHIP_CEDAR ? 4 : 1;
461
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
462
/* Should be 2047, but 2048 is a requirement for GL 4.4 */
466
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
467
if (family >= CHIP_CEDAR)
471
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
472
if (family >= CHIP_CEDAR)
476
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
477
/* textures support 8192, but layered rendering supports 2048 */
479
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
480
/* textures support 8192, but layered rendering supports 2048 */
483
/* Render targets. */
484
case PIPE_CAP_MAX_RENDER_TARGETS:
485
/* XXX some r6xx are buggy and can only do 4 */
488
case PIPE_CAP_MAX_VIEWPORTS:
489
return R600_MAX_VIEWPORTS;
490
case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
491
case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
494
/* Timer queries, present when the clock frequency is non zero. */
495
case PIPE_CAP_QUERY_TIME_ELAPSED:
496
return rscreen->b.info.clock_crystal_freq != 0;
497
case PIPE_CAP_QUERY_TIMESTAMP:
498
return rscreen->b.info.drm_minor >= 20 &&
499
rscreen->b.info.clock_crystal_freq != 0;
501
case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
502
case PIPE_CAP_MIN_TEXEL_OFFSET:
505
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
506
case PIPE_CAP_MAX_TEXEL_OFFSET:
509
case PIPE_CAP_MAX_VARYINGS:
512
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
513
return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
514
case PIPE_CAP_ENDIANNESS:
515
return PIPE_ENDIAN_LITTLE;
517
case PIPE_CAP_VENDOR_ID:
518
return ATI_VENDOR_ID;
519
case PIPE_CAP_DEVICE_ID:
520
return rscreen->b.info.pci_id;
521
case PIPE_CAP_ACCELERATED:
523
case PIPE_CAP_VIDEO_MEMORY:
524
return rscreen->b.info.vram_size >> 20;
527
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
528
return rscreen->b.chip_class >= R700;
529
case PIPE_CAP_PCI_GROUP:
530
return rscreen->b.info.pci_domain;
531
case PIPE_CAP_PCI_BUS:
532
return rscreen->b.info.pci_bus;
533
case PIPE_CAP_PCI_DEVICE:
534
return rscreen->b.info.pci_dev;
535
case PIPE_CAP_PCI_FUNCTION:
536
return rscreen->b.info.pci_func;
538
case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
539
if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
542
case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
543
if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
544
return EG_MAX_ATOMIC_BUFFERS;
548
return u_pipe_screen_get_param_defaults(pscreen, param);
552
static int r600_get_shader_param(struct pipe_screen* pscreen,
553
enum pipe_shader_type shader,
554
enum pipe_shader_cap param)
556
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
560
case PIPE_SHADER_FRAGMENT:
561
case PIPE_SHADER_VERTEX:
563
case PIPE_SHADER_GEOMETRY:
564
if (rscreen->b.family >= CHIP_CEDAR)
566
/* pre-evergreen geom shaders need newer kernel */
567
if (rscreen->b.info.drm_minor >= 37)
570
case PIPE_SHADER_TESS_CTRL:
571
case PIPE_SHADER_TESS_EVAL:
572
case PIPE_SHADER_COMPUTE:
573
if (rscreen->b.family >= CHIP_CEDAR)
581
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
582
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
583
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
584
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
586
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
588
case PIPE_SHADER_CAP_MAX_INPUTS:
589
return shader == PIPE_SHADER_VERTEX ? 16 : 32;
590
case PIPE_SHADER_CAP_MAX_OUTPUTS:
591
return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
592
case PIPE_SHADER_CAP_MAX_TEMPS:
593
return 256; /* Max native temporaries. */
594
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
595
if (shader == PIPE_SHADER_COMPUTE) {
596
uint64_t max_const_buffer_size;
597
enum pipe_shader_ir ir_type = is_nir_enabled(&rscreen->b) ?
598
PIPE_SHADER_IR_NIR: PIPE_SHADER_IR_TGSI;
599
pscreen->get_compute_param(pscreen, ir_type,
600
PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
601
&max_const_buffer_size);
602
return MIN2(max_const_buffer_size, INT_MAX);
605
return R600_MAX_CONST_BUFFER_SIZE;
607
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
608
return R600_MAX_USER_CONST_BUFFERS;
609
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
611
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
613
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
614
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
615
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
616
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
618
case PIPE_SHADER_CAP_SUBROUTINES:
619
case PIPE_SHADER_CAP_INT64_ATOMICS:
620
case PIPE_SHADER_CAP_FP16:
621
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
622
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
623
case PIPE_SHADER_CAP_INT16:
624
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
626
case PIPE_SHADER_CAP_INTEGERS:
627
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
629
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
630
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
632
case PIPE_SHADER_CAP_PREFERRED_IR:
633
if (is_nir_enabled(&rscreen->b))
634
return PIPE_SHADER_IR_NIR;
635
return PIPE_SHADER_IR_TGSI;
636
case PIPE_SHADER_CAP_SUPPORTED_IRS: {
638
if (shader == PIPE_SHADER_COMPUTE)
639
ir = 1 << PIPE_SHADER_IR_NATIVE;
640
if (rscreen->b.family >= CHIP_CEDAR) {
641
ir |= 1 << PIPE_SHADER_IR_TGSI;
642
if (is_nir_enabled(&rscreen->b))
643
ir |= 1 << PIPE_SHADER_IR_NIR;
647
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
648
if (rscreen->b.family == CHIP_ARUBA ||
649
rscreen->b.family == CHIP_CAYMAN ||
650
rscreen->b.family == CHIP_CYPRESS ||
651
rscreen->b.family == CHIP_HEMLOCK)
654
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
655
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
656
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
657
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
658
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
660
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
661
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
662
if (rscreen->b.family >= CHIP_CEDAR &&
663
(shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
666
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
667
if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
670
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
671
/* having to allocate the atomics out amongst shaders stages is messy,
672
so give compute 8 buffers and all the others one */
673
if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
674
return EG_MAX_ATOMIC_BUFFERS;
677
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
678
/* due to a bug in the shader compiler, some loops hang
679
* if they are not unrolled, see:
680
* https://bugs.freedesktop.org/show_bug.cgi?id=86720
687
static void r600_destroy_screen(struct pipe_screen* pscreen)
689
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
694
if (!rscreen->b.ws->unref(rscreen->b.ws))
697
if (rscreen->global_pool) {
698
compute_memory_pool_delete(rscreen->global_pool);
701
r600_destroy_common_screen(&rscreen->b);
704
static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
705
const struct pipe_resource *templ)
707
if (templ->target == PIPE_BUFFER &&
708
(templ->bind & PIPE_BIND_GLOBAL))
709
return r600_compute_global_buffer_create(screen, templ);
711
return r600_resource_create_common(screen, templ);
714
struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
715
const struct pipe_screen_config *config)
717
struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
723
/* Set functions first. */
724
rscreen->b.b.context_create = r600_create_context;
725
rscreen->b.b.destroy = r600_destroy_screen;
726
rscreen->b.b.get_param = r600_get_param;
727
rscreen->b.b.get_shader_param = r600_get_shader_param;
728
rscreen->b.b.resource_create = r600_resource_create;
730
if (!r600_common_screen_init(&rscreen->b, ws)) {
735
if (rscreen->b.info.chip_class >= EVERGREEN) {
736
rscreen->b.b.is_format_supported = evergreen_is_format_supported;
738
rscreen->b.b.is_format_supported = r600_is_format_supported;
741
rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
742
if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
743
rscreen->b.debug_flags |= DBG_COMPUTE;
744
if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
745
rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
746
if (!debug_get_bool_option("R600_HYPERZ", TRUE))
747
rscreen->b.debug_flags |= DBG_NO_HYPERZ;
749
if (rscreen->b.family == CHIP_UNKNOWN) {
750
fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
755
/* Figure out streamout kernel support. */
756
switch (rscreen->b.chip_class) {
758
if (rscreen->b.family < CHIP_RS780) {
759
rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
761
rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
765
rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
769
rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
772
rscreen->b.has_streamout = FALSE;
777
switch (rscreen->b.chip_class) {
780
rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
781
rscreen->has_compressed_msaa_texturing = false;
784
rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
785
rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
788
rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
789
rscreen->has_compressed_msaa_texturing = true;
792
rscreen->has_msaa = FALSE;
793
rscreen->has_compressed_msaa_texturing = false;
796
rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
797
!(rscreen->b.debug_flags & DBG_NO_CP_DMA);
799
rscreen->b.barrier_flags.cp_to_L2 =
800
R600_CONTEXT_INV_VERTEX_CACHE |
801
R600_CONTEXT_INV_TEX_CACHE |
802
R600_CONTEXT_INV_CONST_CACHE;
803
rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV;
805
rscreen->global_pool = compute_memory_pool_new(rscreen);
807
/* Create the auxiliary context. This must be done last. */
808
rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
810
rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
811
#if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
812
struct pipe_resource templ = {};
815
templ.height0 = 2048;
817
templ.array_size = 1;
818
templ.target = PIPE_TEXTURE_2D;
819
templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
820
templ.usage = PIPE_USAGE_DEFAULT;
822
struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
823
unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_MAP_WRITE);
827
r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
828
r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
829
r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
830
r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
831
r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
833
ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
836
for (i = 0; i < 256; i++) {
837
printf("%02X", map[i]);
843
if (rscreen->b.debug_flags & DBG_TEST_DMA)
844
r600_test_dma(&rscreen->b);
846
r600_query_fix_enabled_rb_mask(&rscreen->b);
847
return &rscreen->b.b;
added
removed
src/gallium/drivers/r600/r600_pipe.c
