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* Copyright © 2010 Intel Corporation
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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/** @file brw_fs_visitor.cpp
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* This file supports generating the FS LIR from the GLSL IR. The LIR
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* makes it easier to do backend-specific optimizations than doing so
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* in the GLSL IR or in the native code.
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#include "compiler/glsl_types.h"
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/* Sample from the MCS surface attached to this multisample texture. */
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fs_visitor::emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
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const fs_reg &texture,
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const fs_reg &texture_handle)
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const fs_reg dest = vgrf(glsl_type::uvec4_type);
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fs_reg srcs[TEX_LOGICAL_NUM_SRCS];
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srcs[TEX_LOGICAL_SRC_COORDINATE] = coordinate;
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srcs[TEX_LOGICAL_SRC_SURFACE] = texture;
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srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_ud(0);
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srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE] = texture_handle;
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srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(components);
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srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(0);
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fs_inst *inst = bld.emit(SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs,
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/* We only care about one or two regs of response, but the sampler always
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inst->size_written = 4 * dest.component_size(inst->exec_size);
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/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
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fs_visitor::emit_dummy_fs()
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int reg_width = dispatch_width / 8;
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/* Everyone's favorite color. */
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const float color[4] = { 1.0, 0.0, 1.0, 0.0 };
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for (int i = 0; i < 4; i++) {
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bld.MOV(fs_reg(MRF, 2 + i * reg_width, BRW_REGISTER_TYPE_F),
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write = bld.emit(FS_OPCODE_FB_WRITE);
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write->last_rt = true;
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if (devinfo->ver >= 6) {
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write->mlen = 4 * reg_width;
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write->header_size = 2;
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write->mlen = 2 + 4 * reg_width;
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/* Tell the SF we don't have any inputs. Gfx4-5 require at least one
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* varying to avoid GPU hangs, so set that.
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struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data);
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wm_prog_data->num_varying_inputs = devinfo->ver < 6 ? 1 : 0;
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memset(wm_prog_data->urb_setup, -1,
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sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
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brw_compute_urb_setup_index(wm_prog_data);
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/* We don't have any uniforms. */
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stage_prog_data->nr_params = 0;
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stage_prog_data->curb_read_length = 0;
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stage_prog_data->dispatch_grf_start_reg = 2;
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wm_prog_data->dispatch_grf_start_reg_16 = 2;
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wm_prog_data->dispatch_grf_start_reg_32 = 2;
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grf_used = 1; /* Gfx4-5 don't allow zero GRF blocks */
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/* Input data is organized with first the per-primitive values, followed
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* by per-vertex values. The per-vertex will have interpolation information
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* associated, so use 4 components for each value.
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/* The register location here is relative to the start of the URB
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* data. It will get adjusted to be a real location before
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* generate_code() time.
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fs_visitor::interp_reg(int location, int channel)
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assert(stage == MESA_SHADER_FRAGMENT);
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assert(BITFIELD64_BIT(location) & ~nir->info.per_primitive_inputs);
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const struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
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assert(prog_data->urb_setup[location] >= 0);
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unsigned nr = prog_data->urb_setup[location];
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/* Adjust so we start counting from the first per_vertex input. */
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assert(nr >= prog_data->num_per_primitive_inputs);
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nr -= prog_data->num_per_primitive_inputs;
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const unsigned per_vertex_start = prog_data->num_per_primitive_inputs;
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const unsigned regnr = per_vertex_start + (nr * 4) + channel;
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return fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F);
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/* The register location here is relative to the start of the URB
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* data. It will get adjusted to be a real location before
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* generate_code() time.
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fs_visitor::per_primitive_reg(int location)
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assert(stage == MESA_SHADER_FRAGMENT);
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assert(BITFIELD64_BIT(location) & nir->info.per_primitive_inputs);
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const struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
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assert(prog_data->urb_setup[location] >= 0);
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const unsigned regnr = prog_data->urb_setup[location];
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assert(regnr < prog_data->num_per_primitive_inputs);
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return fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F);
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/** Emits the interpolation for the varying inputs. */
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fs_visitor::emit_interpolation_setup_gfx4()
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struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
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fs_builder abld = bld.annotate("compute pixel centers");
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this->pixel_x = vgrf(glsl_type::uint_type);
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this->pixel_y = vgrf(glsl_type::uint_type);
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this->pixel_x.type = BRW_REGISTER_TYPE_UW;
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this->pixel_y.type = BRW_REGISTER_TYPE_UW;
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abld.ADD(this->pixel_x,
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fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
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fs_reg(brw_imm_v(0x10101010)));
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abld.ADD(this->pixel_y,
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fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
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fs_reg(brw_imm_v(0x11001100)));
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abld = bld.annotate("compute pixel deltas from v0");
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this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL] =
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vgrf(glsl_type::vec2_type);
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const fs_reg &delta_xy = this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL];
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const fs_reg xstart(negate(brw_vec1_grf(1, 0)));
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const fs_reg ystart(negate(brw_vec1_grf(1, 1)));
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if (devinfo->has_pln) {
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for (unsigned i = 0; i < dispatch_width / 8; i++) {
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abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 0), i),
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quarter(this->pixel_x, i), xstart);
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abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 1), i),
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quarter(this->pixel_y, i), ystart);
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abld.ADD(offset(delta_xy, abld, 0), this->pixel_x, xstart);
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abld.ADD(offset(delta_xy, abld, 1), this->pixel_y, ystart);
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this->pixel_z = fetch_payload_reg(bld, payload.source_depth_reg);
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/* The SF program automatically handles doing the perspective correction or
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* not based on wm_prog_data::interp_mode[] so we can use the same pixel
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* offsets for both perspective and non-perspective.
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this->delta_xy[BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL] =
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this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL];
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abld = bld.annotate("compute pos.w and 1/pos.w");
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/* Compute wpos.w. It's always in our setup, since it's needed to
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* interpolate the other attributes.
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this->wpos_w = vgrf(glsl_type::float_type);
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abld.emit(FS_OPCODE_LINTERP, wpos_w, delta_xy,
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component(interp_reg(VARYING_SLOT_POS, 3), 0));
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/* Compute the pixel 1/W value from wpos.w. */
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this->pixel_w = vgrf(glsl_type::float_type);
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abld.emit(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
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brw_rnd_mode_from_nir(unsigned mode, unsigned *mask)
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unsigned brw_mode = 0;
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if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 |
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FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 |
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FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64) &
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brw_mode |= BRW_RND_MODE_RTZ << BRW_CR0_RND_MODE_SHIFT;
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*mask |= BRW_CR0_RND_MODE_MASK;
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if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 |
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FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 |
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FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64) &
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brw_mode |= BRW_RND_MODE_RTNE << BRW_CR0_RND_MODE_SHIFT;
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*mask |= BRW_CR0_RND_MODE_MASK;
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if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP16) {
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brw_mode |= BRW_CR0_FP16_DENORM_PRESERVE;
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*mask |= BRW_CR0_FP16_DENORM_PRESERVE;
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if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP32) {
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brw_mode |= BRW_CR0_FP32_DENORM_PRESERVE;
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*mask |= BRW_CR0_FP32_DENORM_PRESERVE;
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if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP64) {
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brw_mode |= BRW_CR0_FP64_DENORM_PRESERVE;
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*mask |= BRW_CR0_FP64_DENORM_PRESERVE;
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if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16)
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*mask |= BRW_CR0_FP16_DENORM_PRESERVE;
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if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32)
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*mask |= BRW_CR0_FP32_DENORM_PRESERVE;
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if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64)
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*mask |= BRW_CR0_FP64_DENORM_PRESERVE;
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if (mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE)
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*mask |= BRW_CR0_FP_MODE_MASK;
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assert((*mask & brw_mode) == brw_mode);
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fs_visitor::emit_shader_float_controls_execution_mode()
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unsigned execution_mode = this->nir->info.float_controls_execution_mode;
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if (execution_mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE)
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fs_builder abld = bld.annotate("shader floats control execution mode");
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unsigned mask, mode = brw_rnd_mode_from_nir(execution_mode, &mask);
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abld.emit(SHADER_OPCODE_FLOAT_CONTROL_MODE, bld.null_reg_ud(),
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brw_imm_d(mode), brw_imm_d(mask));
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/** Emits the interpolation for the varying inputs. */
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fs_visitor::emit_interpolation_setup_gfx6()
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fs_builder abld = bld.annotate("compute pixel centers");
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this->pixel_x = vgrf(glsl_type::float_type);
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this->pixel_y = vgrf(glsl_type::float_type);
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struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(prog_data);
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fs_reg int_pixel_offset_x, int_pixel_offset_y; /* Used on Gen12HP+ */
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fs_reg int_pixel_offset_xy; /* Used on Gen8+ */
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fs_reg half_int_pixel_offset_x, half_int_pixel_offset_y;
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if (!wm_prog_data->per_coarse_pixel_dispatch) {
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/* The thread payload only delivers subspan locations (ss0, ss1,
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* ss2, ...). Since subspans covers 2x2 pixels blocks, we need to
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* generate 4 pixel coordinates out of each subspan location. We do this
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* by replicating a subspan coordinate 4 times and adding an offset of 1
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* in each direction from the initial top left (tl) location to generate
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* top right (tr = +1 in x), bottom left (bl = +1 in y) and bottom right
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* (br = +1 in x, +1 in y).
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* The locations we build look like this in SIMD8 :
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* ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
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* The value 0x11001010 is a vector of 8 half byte vector. It adds
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* following to generate the 4 pixels coordinates out of the subspan0:
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* 1 : ss0.y + 1 -> ss0.br.y
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* 1 : ss0.y + 1 -> ss0.bl.y
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* 0 : ss0.y + 0 -> ss0.tr.y
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* 0 : ss0.y + 0 -> ss0.tl.y
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* 1 : ss0.x + 1 -> ss0.br.x
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* 0 : ss0.x + 0 -> ss0.bl.x
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* 1 : ss0.x + 1 -> ss0.tr.x
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* 0 : ss0.x + 0 -> ss0.tl.x
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* By doing a SIMD16 add in a SIMD8 shader, we can generate the 8 pixels
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* coordinates out of 2 subspans coordinates in a single ADD instruction
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* (twice the operation above).
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int_pixel_offset_xy = fs_reg(brw_imm_v(0x11001010));
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half_int_pixel_offset_x = fs_reg(brw_imm_uw(0));
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half_int_pixel_offset_y = fs_reg(brw_imm_uw(0));
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/* On Gfx12.5, because of regioning restrictions, the interpolation code
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* is slightly different and works off X & Y only inputs. The ordering
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* of the half bytes here is a bit odd, with each subspan replicated
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* twice and every other element is discarded :
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* ss0.tl ss0.tl ss0.tr ss0.tr ss0.bl ss0.bl ss0.br ss0.br
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* X offset: 0 0 1 0 0 0 1 0
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* Y offset: 0 0 0 0 1 0 1 0
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int_pixel_offset_x = fs_reg(brw_imm_v(0x01000100));
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int_pixel_offset_y = fs_reg(brw_imm_v(0x01010000));
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/* In coarse pixel dispatch we have to do the same ADD instruction that
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* we do in normal per pixel dispatch, except this time we're not adding
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* 1 in each direction, but instead the coarse pixel size.
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* The coarse pixel size is delivered as 2 u8 in r1.0
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struct brw_reg r1_0 = retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), BRW_REGISTER_TYPE_UB);
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const fs_builder dbld =
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abld.exec_all().group(MIN2(16, dispatch_width) * 2, 0);
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if (devinfo->verx10 >= 125) {
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/* To build the array of half bytes we do and AND operation with the
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int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
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dbld.AND(int_pixel_offset_x, byte_offset(r1_0, 0), brw_imm_v(0x0f000f00));
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/* And the right mask in Y. */
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int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW);
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dbld.AND(int_pixel_offset_y, byte_offset(r1_0, 1), brw_imm_v(0x0f0f0000));
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/* To build the array of half bytes we do and AND operation with the
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int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
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dbld.AND(int_pixel_offset_x, byte_offset(r1_0, 0), brw_imm_v(0x0000f0f0));
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/* And the right mask in Y. */
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int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW);
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dbld.AND(int_pixel_offset_y, byte_offset(r1_0, 1), brw_imm_v(0xff000000));
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/* Finally OR the 2 registers. */
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int_pixel_offset_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW);
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dbld.OR(int_pixel_offset_xy, int_pixel_offset_x, int_pixel_offset_y);
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/* Also compute the half pixel size used to center pixels. */
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half_int_pixel_offset_x = bld.vgrf(BRW_REGISTER_TYPE_UW);
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half_int_pixel_offset_y = bld.vgrf(BRW_REGISTER_TYPE_UW);
381
bld.SHR(half_int_pixel_offset_x, suboffset(r1_0, 0), brw_imm_ud(1));
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bld.SHR(half_int_pixel_offset_y, suboffset(r1_0, 1), brw_imm_ud(1));
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for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
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const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
387
struct brw_reg gi_uw = retype(brw_vec1_grf(1 + i, 0), BRW_REGISTER_TYPE_UW);
389
if (devinfo->verx10 >= 125) {
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const fs_builder dbld =
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abld.exec_all().group(hbld.dispatch_width() * 2, 0);
392
const fs_reg int_pixel_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
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const fs_reg int_pixel_y = dbld.vgrf(BRW_REGISTER_TYPE_UW);
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dbld.ADD(int_pixel_x,
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fs_reg(stride(suboffset(gi_uw, 4), 2, 8, 0)),
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dbld.ADD(int_pixel_y,
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fs_reg(stride(suboffset(gi_uw, 5), 2, 8, 0)),
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if (wm_prog_data->per_coarse_pixel_dispatch) {
403
dbld.ADD(int_pixel_x, int_pixel_x,
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horiz_stride(half_int_pixel_offset_x, 0));
405
dbld.ADD(int_pixel_y, int_pixel_y,
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horiz_stride(half_int_pixel_offset_y, 0));
409
hbld.MOV(offset(pixel_x, hbld, i), horiz_stride(int_pixel_x, 2));
410
hbld.MOV(offset(pixel_y, hbld, i), horiz_stride(int_pixel_y, 2));
412
} else if (devinfo->ver >= 8 || dispatch_width == 8) {
413
/* The "Register Region Restrictions" page says for BDW (and newer,
416
* "When destination spans two registers, the source may be one or
417
* two registers. The destination elements must be evenly split
418
* between the two registers."
420
* Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16
421
* to compute our pixel centers.
423
const fs_builder dbld =
424
abld.exec_all().group(hbld.dispatch_width() * 2, 0);
425
fs_reg int_pixel_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW);
427
dbld.ADD(int_pixel_xy,
428
fs_reg(stride(suboffset(gi_uw, 4), 1, 4, 0)),
429
int_pixel_offset_xy);
431
hbld.emit(FS_OPCODE_PIXEL_X, offset(pixel_x, hbld, i), int_pixel_xy,
432
horiz_stride(half_int_pixel_offset_x, 0));
433
hbld.emit(FS_OPCODE_PIXEL_Y, offset(pixel_y, hbld, i), int_pixel_xy,
434
horiz_stride(half_int_pixel_offset_y, 0));
436
/* The "Register Region Restrictions" page says for SNB, IVB, HSW:
438
* "When destination spans two registers, the source MUST span
441
* Since the GRF source of the ADD will only read a single register,
442
* we must do two separate ADDs in SIMD16.
444
const fs_reg int_pixel_x = hbld.vgrf(BRW_REGISTER_TYPE_UW);
445
const fs_reg int_pixel_y = hbld.vgrf(BRW_REGISTER_TYPE_UW);
447
hbld.ADD(int_pixel_x,
448
fs_reg(stride(suboffset(gi_uw, 4), 2, 4, 0)),
449
fs_reg(brw_imm_v(0x10101010)));
450
hbld.ADD(int_pixel_y,
451
fs_reg(stride(suboffset(gi_uw, 5), 2, 4, 0)),
452
fs_reg(brw_imm_v(0x11001100)));
454
/* As of gfx6, we can no longer mix float and int sources. We have
455
* to turn the integer pixel centers into floats for their actual
458
hbld.MOV(offset(pixel_x, hbld, i), int_pixel_x);
459
hbld.MOV(offset(pixel_y, hbld, i), int_pixel_y);
463
abld = bld.annotate("compute pos.z");
464
if (wm_prog_data->uses_depth_w_coefficients) {
465
assert(!wm_prog_data->uses_src_depth);
466
/* In coarse pixel mode, the HW doesn't interpolate Z coordinate
467
* properly. In the same way we have to add the coarse pixel size to
468
* pixels locations, here we recompute the Z value with 2 coefficients
471
fs_reg coef_payload = fetch_payload_reg(abld, payload.depth_w_coef_reg, BRW_REGISTER_TYPE_F);
472
const fs_reg x_start = brw_vec1_grf(coef_payload.nr, 2);
473
const fs_reg y_start = brw_vec1_grf(coef_payload.nr, 6);
474
const fs_reg z_cx = brw_vec1_grf(coef_payload.nr, 1);
475
const fs_reg z_cy = brw_vec1_grf(coef_payload.nr, 0);
476
const fs_reg z_c0 = brw_vec1_grf(coef_payload.nr, 3);
478
const fs_reg float_pixel_x = abld.vgrf(BRW_REGISTER_TYPE_F);
479
const fs_reg float_pixel_y = abld.vgrf(BRW_REGISTER_TYPE_F);
481
abld.ADD(float_pixel_x, this->pixel_x, negate(x_start));
482
abld.ADD(float_pixel_y, this->pixel_y, negate(y_start));
484
/* r1.0 - 0:7 ActualCoarsePixelShadingSize.X */
485
const fs_reg u8_cps_width = fs_reg(retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UB));
486
/* r1.0 - 15:8 ActualCoarsePixelShadingSize.Y */
487
const fs_reg u8_cps_height = byte_offset(u8_cps_width, 1);
488
const fs_reg u32_cps_width = abld.vgrf(BRW_REGISTER_TYPE_UD);
489
const fs_reg u32_cps_height = abld.vgrf(BRW_REGISTER_TYPE_UD);
490
abld.MOV(u32_cps_width, u8_cps_width);
491
abld.MOV(u32_cps_height, u8_cps_height);
493
const fs_reg f_cps_width = abld.vgrf(BRW_REGISTER_TYPE_F);
494
const fs_reg f_cps_height = abld.vgrf(BRW_REGISTER_TYPE_F);
495
abld.MOV(f_cps_width, u32_cps_width);
496
abld.MOV(f_cps_height, u32_cps_height);
498
/* Center in the middle of the coarse pixel. */
499
abld.MAD(float_pixel_x, float_pixel_x, brw_imm_f(0.5f), f_cps_width);
500
abld.MAD(float_pixel_y, float_pixel_y, brw_imm_f(0.5f), f_cps_height);
502
this->pixel_z = abld.vgrf(BRW_REGISTER_TYPE_F);
503
abld.MAD(this->pixel_z, z_c0, z_cx, float_pixel_x);
504
abld.MAD(this->pixel_z, this->pixel_z, z_cy, float_pixel_y);
507
if (wm_prog_data->uses_src_depth) {
508
assert(!wm_prog_data->uses_depth_w_coefficients);
509
this->pixel_z = fetch_payload_reg(bld, payload.source_depth_reg);
512
if (wm_prog_data->uses_src_w) {
513
abld = bld.annotate("compute pos.w");
514
this->pixel_w = fetch_payload_reg(abld, payload.source_w_reg);
515
this->wpos_w = vgrf(glsl_type::float_type);
516
abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
519
for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
520
this->delta_xy[i] = fetch_barycentric_reg(
521
bld, payload.barycentric_coord_reg[i]);
524
uint32_t centroid_modes = wm_prog_data->barycentric_interp_modes &
525
(1 << BRW_BARYCENTRIC_PERSPECTIVE_CENTROID |
526
1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID);
528
if (devinfo->needs_unlit_centroid_workaround && centroid_modes) {
529
/* Get the pixel/sample mask into f0 so that we know which
530
* pixels are lit. Then, for each channel that is unlit,
531
* replace the centroid data with non-centroid data.
533
for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
534
bld.exec_all().group(1, 0)
535
.MOV(retype(brw_flag_reg(0, i), BRW_REGISTER_TYPE_UW),
536
retype(brw_vec1_grf(1 + i, 7), BRW_REGISTER_TYPE_UW));
539
for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
540
if (!(centroid_modes & (1 << i)))
543
const fs_reg centroid_delta_xy = delta_xy[i];
544
const fs_reg &pixel_delta_xy = delta_xy[i - 1];
546
delta_xy[i] = bld.vgrf(BRW_REGISTER_TYPE_F, 2);
548
for (unsigned c = 0; c < 2; c++) {
549
for (unsigned q = 0; q < dispatch_width / 8; q++) {
550
set_predicate(BRW_PREDICATE_NORMAL,
552
quarter(offset(delta_xy[i], bld, c), q),
553
quarter(offset(centroid_delta_xy, bld, c), q),
554
quarter(offset(pixel_delta_xy, bld, c), q)));
561
static enum brw_conditional_mod
562
cond_for_alpha_func(enum compare_func func)
565
case COMPARE_FUNC_GREATER:
566
return BRW_CONDITIONAL_G;
567
case COMPARE_FUNC_GEQUAL:
568
return BRW_CONDITIONAL_GE;
569
case COMPARE_FUNC_LESS:
570
return BRW_CONDITIONAL_L;
571
case COMPARE_FUNC_LEQUAL:
572
return BRW_CONDITIONAL_LE;
573
case COMPARE_FUNC_EQUAL:
574
return BRW_CONDITIONAL_EQ;
575
case COMPARE_FUNC_NOTEQUAL:
576
return BRW_CONDITIONAL_NEQ;
578
unreachable("Not reached");
583
* Alpha test support for when we compile it into the shader instead
584
* of using the normal fixed-function alpha test.
587
fs_visitor::emit_alpha_test()
589
assert(stage == MESA_SHADER_FRAGMENT);
590
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
591
const fs_builder abld = bld.annotate("Alpha test");
594
if (key->alpha_test_func == COMPARE_FUNC_ALWAYS)
597
if (key->alpha_test_func == COMPARE_FUNC_NEVER) {
599
fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
600
BRW_REGISTER_TYPE_UW));
601
cmp = abld.CMP(bld.null_reg_f(), some_reg, some_reg,
602
BRW_CONDITIONAL_NEQ);
605
fs_reg color = offset(outputs[0], bld, 3);
607
/* f0.1 &= func(color, ref) */
608
cmp = abld.CMP(bld.null_reg_f(), color, brw_imm_f(key->alpha_test_ref),
609
cond_for_alpha_func(key->alpha_test_func));
611
cmp->predicate = BRW_PREDICATE_NORMAL;
612
cmp->flag_subreg = 1;
616
fs_visitor::emit_single_fb_write(const fs_builder &bld,
617
fs_reg color0, fs_reg color1,
618
fs_reg src0_alpha, unsigned components)
620
assert(stage == MESA_SHADER_FRAGMENT);
621
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
623
/* Hand over gl_FragDepth or the payload depth. */
624
const fs_reg dst_depth = fetch_payload_reg(bld, payload.dest_depth_reg);
625
fs_reg src_depth, src_stencil;
627
if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
628
src_depth = frag_depth;
629
} else if (source_depth_to_render_target) {
630
/* If we got here, we're in one of those strange Gen4-5 cases where
631
* we're forced to pass the source depth, unmodified, to the FB write.
632
* In this case, we don't want to use pixel_z because we may not have
633
* set up interpolation. It's also perfectly safe because it only
634
* happens on old hardware (no coarse interpolation) and this is
635
* explicitly the pass-through case.
637
assert(devinfo->ver <= 5);
638
src_depth = fetch_payload_reg(bld, payload.source_depth_reg);
641
if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))
642
src_stencil = frag_stencil;
644
const fs_reg sources[] = {
645
color0, color1, src0_alpha, src_depth, dst_depth, src_stencil,
646
(prog_data->uses_omask ? sample_mask : fs_reg()),
647
brw_imm_ud(components)
649
assert(ARRAY_SIZE(sources) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS);
650
fs_inst *write = bld.emit(FS_OPCODE_FB_WRITE_LOGICAL, fs_reg(),
651
sources, ARRAY_SIZE(sources));
653
if (prog_data->uses_kill) {
654
write->predicate = BRW_PREDICATE_NORMAL;
655
write->flag_subreg = sample_mask_flag_subreg(this);
662
fs_visitor::emit_fb_writes()
664
assert(stage == MESA_SHADER_FRAGMENT);
665
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
666
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
668
fs_inst *inst = NULL;
670
if (source_depth_to_render_target && devinfo->ver == 6) {
671
/* For outputting oDepth on gfx6, SIMD8 writes have to be used. This
672
* would require SIMD8 moves of each half to message regs, e.g. by using
673
* the SIMD lowering pass. Unfortunately this is more difficult than it
674
* sounds because the SIMD8 single-source message lacks channel selects
675
* for the second and third subspans.
677
limit_dispatch_width(8, "Depth writes unsupported in SIMD16+ mode.\n");
680
if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL)) {
681
/* From the 'Render Target Write message' section of the docs:
682
* "Output Stencil is not supported with SIMD16 Render Target Write
685
limit_dispatch_width(8, "gl_FragStencilRefARB unsupported "
686
"in SIMD16+ mode.\n");
689
/* ANV doesn't know about sample mask output during the wm key creation
690
* so we compute if we need replicate alpha and emit alpha to coverage
693
const bool replicate_alpha = key->alpha_test_replicate_alpha ||
694
(key->nr_color_regions > 1 && key->alpha_to_coverage &&
695
(sample_mask.file == BAD_FILE || devinfo->ver == 6));
697
for (int target = 0; target < key->nr_color_regions; target++) {
698
/* Skip over outputs that weren't written. */
699
if (this->outputs[target].file == BAD_FILE)
702
const fs_builder abld = bld.annotate(
703
ralloc_asprintf(this->mem_ctx, "FB write target %d", target));
706
if (devinfo->ver >= 6 && replicate_alpha && target != 0)
707
src0_alpha = offset(outputs[0], bld, 3);
709
inst = emit_single_fb_write(abld, this->outputs[target],
710
this->dual_src_output, src0_alpha, 4);
711
inst->target = target;
714
prog_data->dual_src_blend = (this->dual_src_output.file != BAD_FILE &&
715
this->outputs[0].file != BAD_FILE);
716
assert(!prog_data->dual_src_blend || key->nr_color_regions == 1);
719
/* Even if there's no color buffers enabled, we still need to send
720
* alpha out the pipeline to our null renderbuffer to support
721
* alpha-testing, alpha-to-coverage, and so on.
723
/* FINISHME: Factor out this frequently recurring pattern into a
726
const fs_reg srcs[] = { reg_undef, reg_undef,
727
reg_undef, offset(this->outputs[0], bld, 3) };
728
const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 4);
729
bld.LOAD_PAYLOAD(tmp, srcs, 4, 0);
731
inst = emit_single_fb_write(bld, tmp, reg_undef, reg_undef, 4);
735
inst->last_rt = true;
738
if (devinfo->ver >= 11 && devinfo->ver <= 12 &&
739
prog_data->dual_src_blend) {
740
/* The dual-source RT write messages fail to release the thread
741
* dependency on ICL and TGL with SIMD32 dispatch, leading to hangs.
743
* XXX - Emit an extra single-source NULL RT-write marked LastRT in
744
* order to release the thread dependency without disabling
747
* The dual-source RT write messages may lead to hangs with SIMD16
748
* dispatch on ICL due some unknown reasons, see
749
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
751
limit_dispatch_width(8, "Dual source blending unsupported "
752
"in SIMD16 and SIMD32 modes.\n");
757
fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
759
int slot, urb_offset, length;
760
int starting_urb_offset = 0;
761
const struct brw_vue_prog_data *vue_prog_data =
762
brw_vue_prog_data(this->prog_data);
763
const struct brw_vs_prog_key *vs_key =
764
(const struct brw_vs_prog_key *) this->key;
765
const GLbitfield64 psiz_mask =
766
VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PSIZ | VARYING_BIT_PRIMITIVE_SHADING_RATE;
767
const struct brw_vue_map *vue_map = &vue_prog_data->vue_map;
772
if (stage == MESA_SHADER_TESS_EVAL)
773
urb_handle = fs_reg(retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD));
775
urb_handle = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
777
opcode opcode = SHADER_OPCODE_URB_WRITE_SIMD8;
779
fs_reg per_slot_offsets;
781
if (stage == MESA_SHADER_GEOMETRY) {
782
const struct brw_gs_prog_data *gs_prog_data =
783
brw_gs_prog_data(this->prog_data);
785
/* We need to increment the Global Offset to skip over the control data
786
* header and the extra "Vertex Count" field (1 HWord) at the beginning
787
* of the VUE. We're counting in OWords, so the units are doubled.
789
starting_urb_offset = 2 * gs_prog_data->control_data_header_size_hwords;
790
if (gs_prog_data->static_vertex_count == -1)
791
starting_urb_offset += 2;
793
/* We also need to use per-slot offsets. The per-slot offset is the
794
* Vertex Count. SIMD8 mode processes 8 different primitives at a
795
* time; each may output a different number of vertices.
797
opcode = SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT;
800
/* The URB offset is in 128-bit units, so we need to multiply by 2 */
801
const int output_vertex_size_owords =
802
gs_prog_data->output_vertex_size_hwords * 2;
804
if (gs_vertex_count.file == IMM) {
805
per_slot_offsets = brw_imm_ud(output_vertex_size_owords *
808
per_slot_offsets = vgrf(glsl_type::uint_type);
809
bld.MUL(per_slot_offsets, gs_vertex_count,
810
brw_imm_ud(output_vertex_size_owords));
815
urb_offset = starting_urb_offset;
818
/* SSO shaders can have VUE slots allocated which are never actually
819
* written to, so ignore them when looking for the last (written) slot.
821
int last_slot = vue_map->num_slots - 1;
822
while (last_slot > 0 &&
823
(vue_map->slot_to_varying[last_slot] == BRW_VARYING_SLOT_PAD ||
824
outputs[vue_map->slot_to_varying[last_slot]].file == BAD_FILE)) {
828
bool urb_written = false;
829
for (slot = 0; slot < vue_map->num_slots; slot++) {
830
int varying = vue_map->slot_to_varying[slot];
832
case VARYING_SLOT_PSIZ: {
833
/* The point size varying slot is the vue header and is always in the
834
* vue map. But often none of the special varyings that live there
835
* are written and in that case we can skip writing to the vue
836
* header, provided the corresponding state properly clamps the
837
* values further down the pipeline. */
838
if ((vue_map->slots_valid & psiz_mask) == 0) {
844
fs_reg zero(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
845
bld.MOV(zero, brw_imm_ud(0u));
847
if (vue_map->slots_valid & VARYING_BIT_PRIMITIVE_SHADING_RATE &&
848
this->outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE].file != BAD_FILE) {
849
sources[length++] = this->outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE];
850
} else if (devinfo->has_coarse_pixel_primitive_and_cb) {
851
uint32_t one_fp16 = 0x3C00;
852
fs_reg one_by_one_fp16(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
853
bld.MOV(one_by_one_fp16, brw_imm_ud((one_fp16 << 16) | one_fp16));
854
sources[length++] = one_by_one_fp16;
856
sources[length++] = zero;
859
if (vue_map->slots_valid & VARYING_BIT_LAYER)
860
sources[length++] = this->outputs[VARYING_SLOT_LAYER];
862
sources[length++] = zero;
864
if (vue_map->slots_valid & VARYING_BIT_VIEWPORT)
865
sources[length++] = this->outputs[VARYING_SLOT_VIEWPORT];
867
sources[length++] = zero;
869
if (vue_map->slots_valid & VARYING_BIT_PSIZ)
870
sources[length++] = this->outputs[VARYING_SLOT_PSIZ];
872
sources[length++] = zero;
875
case BRW_VARYING_SLOT_NDC:
876
case VARYING_SLOT_EDGE:
877
unreachable("unexpected scalar vs output");
881
/* gl_Position is always in the vue map, but isn't always written by
882
* the shader. Other varyings (clip distances) get added to the vue
883
* map but don't always get written. In those cases, the
884
* corresponding this->output[] slot will be invalid we and can skip
885
* the urb write for the varying. If we've already queued up a vue
886
* slot for writing we flush a mlen 5 urb write, otherwise we just
887
* advance the urb_offset.
889
if (varying == BRW_VARYING_SLOT_PAD ||
890
this->outputs[varying].file == BAD_FILE) {
898
if (stage == MESA_SHADER_VERTEX && vs_key->clamp_vertex_color &&
899
(varying == VARYING_SLOT_COL0 ||
900
varying == VARYING_SLOT_COL1 ||
901
varying == VARYING_SLOT_BFC0 ||
902
varying == VARYING_SLOT_BFC1)) {
903
/* We need to clamp these guys, so do a saturating MOV into a
904
* temp register and use that for the payload.
906
for (int i = 0; i < 4; i++) {
907
fs_reg reg = fs_reg(VGRF, alloc.allocate(1), outputs[varying].type);
908
fs_reg src = offset(this->outputs[varying], bld, i);
909
set_saturate(true, bld.MOV(reg, src));
910
sources[length++] = reg;
915
/* When using Primitive Replication, there may be multiple slots
918
if (varying == VARYING_SLOT_POS)
919
slot_offset = slot - vue_map->varying_to_slot[VARYING_SLOT_POS];
921
for (unsigned i = 0; i < 4; i++) {
922
sources[length++] = offset(this->outputs[varying], bld,
923
i + (slot_offset * 4));
929
const fs_builder abld = bld.annotate("URB write");
931
/* If we've queued up 8 registers of payload (2 VUE slots), if this is
932
* the last slot or if we need to flush (see BAD_FILE varying case
933
* above), emit a URB write send now to flush out the data.
935
if (length == 8 || (length > 0 && slot == last_slot))
938
fs_reg *payload_sources =
939
ralloc_array(mem_ctx, fs_reg, length + header_size);
940
fs_reg payload = fs_reg(VGRF, alloc.allocate(length + header_size),
941
BRW_REGISTER_TYPE_F);
942
payload_sources[0] = urb_handle;
944
if (opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT)
945
payload_sources[1] = per_slot_offsets;
947
memcpy(&payload_sources[header_size], sources,
948
length * sizeof sources[0]);
950
abld.LOAD_PAYLOAD(payload, payload_sources, length + header_size,
953
fs_inst *inst = abld.emit(opcode, reg_undef, payload);
955
/* For ICL WA 1805992985 one needs additional write in the end. */
956
if (devinfo->ver == 11 && stage == MESA_SHADER_TESS_EVAL)
959
inst->eot = slot == last_slot && stage != MESA_SHADER_GEOMETRY;
961
inst->mlen = length + header_size;
962
inst->offset = urb_offset;
963
urb_offset = starting_urb_offset + slot + 1;
970
/* If we don't have any valid slots to write, just do a minimal urb write
971
* send to terminate the shader. This includes 1 slot of undefined data,
972
* because it's invalid to write 0 data:
974
* From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
975
* Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
976
* Write Data Payload:
978
* "The write data payload can be between 1 and 8 message phases long."
981
/* For GS, just turn EmitVertex() into a no-op. We don't want it to
982
* end the thread, and emit_gs_thread_end() already emits a SEND with
983
* EOT at the end of the program for us.
985
if (stage == MESA_SHADER_GEOMETRY)
988
fs_reg payload = fs_reg(VGRF, alloc.allocate(2), BRW_REGISTER_TYPE_UD);
989
bld.exec_all().MOV(payload, urb_handle);
991
fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload);
998
/* ICL WA 1805992985:
1000
* ICLLP GPU hangs on one of tessellation vkcts tests with DS not done. The
1001
* send cycle, which is a urb write with an eot must be 4 phases long and
1002
* all 8 lanes must valid.
1004
if (devinfo->ver == 11 && stage == MESA_SHADER_TESS_EVAL) {
1005
fs_reg payload = fs_reg(VGRF, alloc.allocate(6), BRW_REGISTER_TYPE_UD);
1007
/* Workaround requires all 8 channels (lanes) to be valid. This is
1008
* understood to mean they all need to be alive. First trick is to find
1009
* a live channel and copy its urb handle for all the other channels to
1010
* make sure all handles are valid.
1012
bld.exec_all().MOV(payload, bld.emit_uniformize(urb_handle));
1014
/* Second trick is to use masked URB write where one can tell the HW to
1015
* actually write data only for selected channels even though all are
1017
* Third trick is to take advantage of the must-be-zero (MBZ) area in
1018
* the very beginning of the URB.
1020
* One masks data to be written only for the first channel and uses
1021
* offset zero explicitly to land data to the MBZ area avoiding trashing
1022
* any other part of the URB.
1024
* Since the WA says that the write needs to be 4 phases long one uses
1025
* 4 slots data. All are explicitly zeros in order to to keep the MBZ
1026
* area written as zeros.
1028
bld.exec_all().MOV(offset(payload, bld, 1), brw_imm_ud(0x10000u));
1029
bld.exec_all().MOV(offset(payload, bld, 2), brw_imm_ud(0u));
1030
bld.exec_all().MOV(offset(payload, bld, 3), brw_imm_ud(0u));
1031
bld.exec_all().MOV(offset(payload, bld, 4), brw_imm_ud(0u));
1032
bld.exec_all().MOV(offset(payload, bld, 5), brw_imm_ud(0u));
1034
fs_inst *inst = bld.exec_all().emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
1035
reg_undef, payload);
1043
fs_visitor::emit_cs_terminate()
1045
assert(devinfo->ver >= 7);
1047
/* We can't directly send from g0, since sends with EOT have to use
1048
* g112-127. So, copy it to a virtual register, The register allocator will
1049
* make sure it uses the appropriate register range.
1051
struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD);
1052
fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
1053
bld.group(8, 0).exec_all().MOV(payload, g0);
1055
/* Send a message to the thread spawner to terminate the thread. */
1056
fs_inst *inst = bld.exec_all()
1057
.emit(CS_OPCODE_CS_TERMINATE, reg_undef, payload);
1062
fs_visitor::emit_barrier()
1064
/* We are getting the barrier ID from the compute shader header */
1065
assert(gl_shader_stage_uses_workgroup(stage));
1067
fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
1069
/* Clear the message payload */
1070
bld.exec_all().group(8, 0).MOV(payload, brw_imm_ud(0u));
1072
if (devinfo->verx10 >= 125) {
1073
/* mov r0.2[31:24] into m0.2[31:24] and m0.2[23:16] */
1074
fs_reg m0_10ub = component(retype(payload, BRW_REGISTER_TYPE_UB), 10);
1076
stride(suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UB), 11),
1078
bld.exec_all().group(2, 0).MOV(m0_10ub, r0_11ub);
1080
assert(gl_shader_stage_is_compute(stage));
1082
uint32_t barrier_id_mask;
1083
switch (devinfo->ver) {
1086
barrier_id_mask = 0x0f000000u; break;
1088
barrier_id_mask = 0x8f000000u; break;
1091
barrier_id_mask = 0x7f000000u; break;
1093
unreachable("barrier is only available on gen >= 7");
1096
/* Copy the barrier id from r0.2 to the message payload reg.2 */
1097
fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD));
1098
bld.exec_all().group(1, 0).AND(component(payload, 2), r0_2,
1099
brw_imm_ud(barrier_id_mask));
1102
/* Emit a gateway "barrier" message using the payload we set up, followed
1103
* by a wait instruction.
1105
bld.exec_all().emit(SHADER_OPCODE_BARRIER, reg_undef, payload);
1108
fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
1110
const brw_base_prog_key *key,
1111
struct brw_stage_prog_data *prog_data,
1112
const nir_shader *shader,
1113
unsigned dispatch_width,
1115
: backend_shader(compiler, log_data, mem_ctx, shader, prog_data,
1117
key(key), gs_compile(NULL), prog_data(prog_data),
1118
live_analysis(this), regpressure_analysis(this),
1119
performance_analysis(this),
1120
dispatch_width(dispatch_width),
1121
bld(fs_builder(this, dispatch_width).at_end())
1126
fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
1128
struct brw_gs_compile *c,
1129
struct brw_gs_prog_data *prog_data,
1130
const nir_shader *shader,
1132
: backend_shader(compiler, log_data, mem_ctx, shader,
1133
&prog_data->base.base, debug_enabled),
1134
key(&c->key.base), gs_compile(c),
1135
prog_data(&prog_data->base.base),
1136
live_analysis(this), regpressure_analysis(this),
1137
performance_analysis(this),
1139
bld(fs_builder(this, dispatch_width).at_end())
1149
this->key_tex = &key->tex;
1151
this->key_tex = NULL;
1153
this->max_dispatch_width = 32;
1154
this->prog_data = this->stage_prog_data;
1156
this->failed = false;
1157
this->fail_msg = NULL;
1159
this->nir_locals = NULL;
1160
this->nir_ssa_values = NULL;
1161
this->nir_system_values = NULL;
1163
memset(&this->payload, 0, sizeof(this->payload));
1164
this->source_depth_to_render_target = false;
1165
this->runtime_check_aads_emit = false;
1166
this->first_non_payload_grf = 0;
1167
this->max_grf = devinfo->ver >= 7 ? GFX7_MRF_HACK_START : BRW_MAX_GRF;
1170
this->last_scratch = 0;
1171
this->push_constant_loc = NULL;
1173
this->shader_stats.scheduler_mode = NULL;
1174
this->shader_stats.promoted_constants = 0,
1177
this->spilled_any_registers = false;
1180
fs_visitor::~fs_visitor()
added
removed
src/intel/compiler/brw_fs_visitor.cpp
