2
* Copyright © 2009 Corbin Simpson
3
* Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6
* Permission is hereby granted, free of charge, to any person obtaining
7
* a copy of this software and associated documentation files (the
8
* "Software"), to deal in the Software without restriction, including
9
* without limitation the rights to use, copy, modify, merge, publish,
10
* distribute, sub license, and/or sell copies of the Software, and to
11
* permit persons to whom the Software is furnished to do so, subject to
12
* the following conditions:
14
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21
* USE OR OTHER DEALINGS IN THE SOFTWARE.
23
* The above copyright notice and this permission notice (including the
24
* next paragraph) shall be included in all copies or substantial portions
28
#include "radeon_drm_bo.h"
29
#include "radeon_drm_cs.h"
30
#include "radeon_drm_public.h"
32
#include "util/os_file.h"
33
#include "util/u_cpu_detect.h"
34
#include "util/u_memory.h"
35
#include "util/u_hash_table.h"
36
#include "util/u_pointer.h"
40
#include <sys/types.h>
44
#include <radeon_surface.h>
46
static struct hash_table *fd_tab = NULL;
47
static mtx_t fd_tab_mutex = _MTX_INITIALIZER_NP;
49
/* Enable/disable feature access for one command stream.
50
* If enable == true, return true on success.
51
* Otherwise, return false.
53
* We basically do the same thing kernel does, because we have to deal
54
* with multiple contexts (here command streams) backed by one winsys. */
55
static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
56
struct radeon_drm_cs **owner,
58
unsigned request, const char *request_name,
61
struct drm_radeon_info info;
62
unsigned value = enable ? 1 : 0;
64
memset(&info, 0, sizeof(info));
68
/* Early exit if we are sure the request will fail. */
75
if (*owner != applier) {
81
/* Pass through the request to the kernel. */
82
info.value = (unsigned long)&value;
83
info.request = request;
84
if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
85
&info, sizeof(info)) != 0) {
90
/* Update the rights in the winsys. */
105
static bool radeon_get_drm_value(int fd, unsigned request,
106
const char *errname, uint32_t *out)
108
struct drm_radeon_info info;
111
memset(&info, 0, sizeof(info));
113
info.value = (unsigned long)out;
114
info.request = request;
116
retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
119
fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
127
/* Helper function to do the ioctls needed for setup and init. */
128
static bool do_winsys_init(struct radeon_drm_winsys *ws)
130
struct drm_radeon_gem_info gem_info;
132
drmVersionPtr version;
134
memset(&gem_info, 0, sizeof(gem_info));
136
/* We do things in a specific order here.
138
* DRM version first. We need to be sure we're running on a KMS chipset.
139
* This is also for some features.
141
* Then, the PCI ID. This is essential and should return usable numbers
142
* for all Radeons. If this fails, we probably got handed an FD for some
145
* The GEM info is actually bogus on the kernel side, as well as our side
146
* (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
147
* we don't actually use the info for anything yet.
149
* The GB and Z pipe requests should always succeed, but they might not
150
* return sensical values for all chipsets, but that's alright because
151
* the pipe drivers already know that.
154
/* Get DRM version. */
155
version = drmGetVersion(ws->fd);
156
if (version->version_major != 2 ||
157
version->version_minor < 12) {
158
fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
159
"only compatible with 2.12.0 (kernel 3.2) or later.\n",
161
version->version_major,
162
version->version_minor,
163
version->version_patchlevel);
164
drmFreeVersion(version);
168
ws->info.drm_major = version->version_major;
169
ws->info.drm_minor = version->version_minor;
170
ws->info.drm_patchlevel = version->version_patchlevel;
171
ws->info.is_amdgpu = false;
172
drmFreeVersion(version);
175
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
180
switch (ws->info.pci_id) {
181
#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
182
#include "pci_ids/r300_pci_ids.h"
185
#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
186
#include "pci_ids/r600_pci_ids.h"
189
#define CHIPSET(pci_id, cfamily) \
191
ws->info.family = CHIP_##cfamily; \
192
ws->info.name = #cfamily; \
195
#include "pci_ids/radeonsi_pci_ids.h"
199
fprintf(stderr, "radeon: Invalid PCI ID.\n");
203
switch (ws->info.family) {
206
fprintf(stderr, "radeon: Unknown family.\n");
216
ws->info.chip_class = R300;
218
case CHIP_R420: /* R4xx-based cores. */
227
ws->info.chip_class = R400;
229
case CHIP_RV515: /* R5xx-based cores. */
235
ws->info.chip_class = R500;
245
ws->info.chip_class = R600;
251
ws->info.chip_class = R700;
264
ws->info.chip_class = EVERGREEN;
268
ws->info.chip_class = CAYMAN;
275
ws->info.chip_class = GFX6;
281
ws->info.chip_class = GFX7;
285
/* Set which chips don't have dedicated VRAM. */
286
switch (ws->info.family) {
301
ws->info.has_dedicated_vram = false;
305
ws->info.has_dedicated_vram = true;
308
ws->info.num_rings[RING_GFX] = 1;
310
ws->info.num_rings[RING_DMA] = 0;
311
/* DMA is disabled on R700. There is IB corruption and hangs. */
312
if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
313
ws->info.num_rings[RING_DMA] = 1;
316
/* Check for UVD and VCE */
317
ws->info.has_video_hw.uvd_decode = false;
318
ws->info.has_video_hw.vce_encode = false;
319
ws->info.vce_fw_version = 0x00000000;
320
if (ws->info.drm_minor >= 32) {
321
uint32_t value = RADEON_CS_RING_UVD;
322
if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
323
"UVD Ring working", &value)) {
324
ws->info.has_video_hw.uvd_decode = value;
325
ws->info.num_rings[RING_UVD] = 1;
328
value = RADEON_CS_RING_VCE;
329
if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
330
NULL, &value) && value) {
332
if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
333
"VCE FW version", &value)) {
334
ws->info.vce_fw_version = value;
335
ws->info.num_rings[RING_VCE] = 1;
336
ws->info.has_video_hw.vce_encode = true;
341
/* Check for userptr support. */
343
struct drm_radeon_gem_userptr args = {0};
345
/* If the ioctl doesn't exist, -EINVAL is returned.
347
* If the ioctl exists, it should return -EACCES
348
* if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
351
ws->info.has_userptr =
352
drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
353
&args, sizeof(args)) == -EACCES;
357
retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
358
&gem_info, sizeof(gem_info));
360
fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
364
ws->info.gart_size = gem_info.gart_size;
365
ws->info.vram_size = gem_info.vram_size;
366
ws->info.vram_vis_size = gem_info.vram_visible;
367
/* Older versions of the kernel driver reported incorrect values, and
368
* didn't support more than 256MB of visible VRAM anyway
370
if (ws->info.drm_minor < 49)
371
ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);
373
ws->info.gart_size_kb = DIV_ROUND_UP(ws->info.gart_size, 1024);
374
ws->info.vram_size_kb = DIV_ROUND_UP(ws->info.vram_size, 1024);
376
/* Radeon allocates all buffers contiguously, which makes large allocations
377
* unlikely to succeed. */
378
if (ws->info.has_dedicated_vram)
379
ws->info.max_alloc_size = ws->info.vram_size * 0.7;
381
ws->info.max_alloc_size = ws->info.gart_size * 0.7;
383
if (ws->info.drm_minor < 40)
384
ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
385
/* Both 32-bit and 64-bit address spaces only have 4GB. */
386
ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 3ull*1024*1024*1024);
388
/* Get max clock frequency info and convert it to MHz */
389
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
390
&ws->info.max_shader_clock);
391
ws->info.max_shader_clock /= 1000;
393
ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
395
/* Generation-specific queries. */
396
if (ws->gen == DRV_R300) {
397
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
399
&ws->info.r300_num_gb_pipes))
402
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
404
&ws->info.r300_num_z_pipes))
407
else if (ws->gen >= DRV_R600) {
408
uint32_t tiling_config = 0;
410
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
412
&ws->info.max_render_backends))
415
/* get the GPU counter frequency, failure is not fatal */
416
radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
417
&ws->info.clock_crystal_freq);
419
radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
422
ws->info.r600_num_banks =
423
ws->info.chip_class >= EVERGREEN ?
424
4 << ((tiling_config & 0xf0) >> 4) :
425
4 << ((tiling_config & 0x30) >> 4);
427
ws->info.pipe_interleave_bytes =
428
ws->info.chip_class >= EVERGREEN ?
429
256 << ((tiling_config & 0xf00) >> 8) :
430
256 << ((tiling_config & 0xc0) >> 6);
432
if (!ws->info.pipe_interleave_bytes)
433
ws->info.pipe_interleave_bytes =
434
ws->info.chip_class >= EVERGREEN ? 512 : 256;
436
radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
437
&ws->info.num_tile_pipes);
439
/* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
440
* pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
441
* reports a different value (12). Fix it by setting what's in the
442
* GB_TILE_MODE array (8).
444
if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
445
ws->info.num_tile_pipes = 8;
447
if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
448
&ws->info.r600_gb_backend_map))
449
ws->info.r600_gb_backend_map_valid = true;
452
ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.max_render_backends);
454
* This fails (silently) on non-GCN or older kernels, overwriting the
455
* default enabled_rb_mask with the result of the last query.
457
if (ws->gen >= DRV_SI)
458
radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
459
&ws->info.enabled_rb_mask);
461
ws->info.r600_has_virtual_memory = false;
462
if (ws->info.drm_minor >= 13) {
463
uint32_t ib_vm_max_size;
465
ws->info.r600_has_virtual_memory = true;
466
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
468
ws->info.r600_has_virtual_memory = false;
469
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
471
ws->info.r600_has_virtual_memory = false;
472
radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
473
&ws->va_unmap_working);
475
if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
476
ws->info.r600_has_virtual_memory = false;
479
/* Get max pipes, this is only needed for compute shaders. All evergreen+
480
* chips have at least 2 pipes, so we use 2 as a default. */
481
ws->info.r600_max_quad_pipes = 2;
482
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
483
&ws->info.r600_max_quad_pipes);
485
/* All GPUs have at least one compute unit */
486
ws->info.num_good_compute_units = 1;
487
radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
488
&ws->info.num_good_compute_units);
490
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
493
switch (ws->info.family) {
496
ws->info.max_tcc_blocks = 2;
502
ws->info.max_tcc_blocks = 4;
505
ws->info.max_tcc_blocks = 8;
508
ws->info.max_tcc_blocks = 12;
511
ws->info.max_tcc_blocks = 16;
514
ws->info.max_tcc_blocks = 0;
518
if (!ws->info.max_se) {
519
switch (ws->info.family) {
538
ws->info.num_se = ws->info.max_se;
540
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
541
&ws->info.max_sa_per_se);
542
if (ws->gen == DRV_SI) {
543
ws->info.max_good_cu_per_sa =
544
ws->info.min_good_cu_per_sa = ws->info.num_good_compute_units /
545
(ws->info.max_se * ws->info.max_sa_per_se);
548
radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
549
&ws->accel_working2);
550
if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
551
fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
552
"returned accel_working2 value %u is smaller than 2. "
553
"Please install a newer kernel.\n",
558
if (ws->info.chip_class == GFX7) {
559
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
560
ws->info.cik_macrotile_mode_array)) {
561
fprintf(stderr, "radeon: Kernel 3.13 is required for Sea Islands support.\n");
566
if (ws->info.chip_class >= GFX6) {
567
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
568
ws->info.si_tile_mode_array)) {
569
fprintf(stderr, "radeon: Kernel 3.10 is required for Southern Islands support.\n");
574
/* Hawaii with old firmware needs type2 nop packet.
575
* accel_working2 with value 3 indicates the new firmware.
577
ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= GFX6 ||
578
(ws->info.family == CHIP_HAWAII &&
579
ws->accel_working2 < 3);
580
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
581
ws->info.ib_alignment = 4096;
582
ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
583
/* HTILE is broken with 1D tiling on old kernels and GFX7. */
584
ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != GFX7 ||
585
ws->info.drm_minor >= 38;
586
ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
587
ws->info.has_bo_metadata = false;
588
ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
589
ws->info.has_eqaa_surface_allocator = false;
590
ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
591
ws->info.kernel_flushes_tc_l2_after_ib = true;
592
/* Old kernels disallowed register writes via COPY_DATA
593
* that are used for indirect compute dispatches. */
594
ws->info.has_indirect_compute_dispatch = ws->info.chip_class == GFX7 ||
595
(ws->info.chip_class == GFX6 &&
596
ws->info.drm_minor >= 45);
597
/* GFX6 doesn't support unaligned loads. */
598
ws->info.has_unaligned_shader_loads = ws->info.chip_class == GFX7 &&
599
ws->info.drm_minor >= 50;
600
ws->info.has_sparse_vm_mappings = false;
601
/* 2D tiling on GFX7 is supported since DRM 2.35.0 */
602
ws->info.has_2d_tiling = ws->info.chip_class <= GFX6 || ws->info.drm_minor >= 35;
603
ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
604
ws->info.max_alignment = 1024*1024;
605
ws->info.has_graphics = true;
606
ws->info.cpdma_prefetch_writes_memory = true;
607
ws->info.max_wave64_per_simd = 10;
608
ws->info.num_physical_sgprs_per_simd = 512;
609
ws->info.num_physical_wave64_vgprs_per_simd = 256;
610
ws->info.has_3d_cube_border_color_mipmap = true;
611
ws->info.spi_cu_en_has_effect = false;
612
ws->info.spi_cu_en = 0xffff;
613
ws->info.never_stop_sq_perf_counters = false;
615
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL ||
616
strstr(debug_get_option("AMD_DEBUG", ""), "check_vm") != NULL;
617
ws->noop_cs = debug_get_bool_option("RADEON_NOOP", false);
622
static void radeon_winsys_destroy(struct radeon_winsys *rws)
624
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
626
if (util_queue_is_initialized(&ws->cs_queue))
627
util_queue_destroy(&ws->cs_queue);
629
mtx_destroy(&ws->hyperz_owner_mutex);
630
mtx_destroy(&ws->cmask_owner_mutex);
632
if (ws->info.r600_has_virtual_memory)
633
pb_slabs_deinit(&ws->bo_slabs);
634
pb_cache_deinit(&ws->bo_cache);
636
if (ws->gen >= DRV_R600) {
637
radeon_surface_manager_free(ws->surf_man);
640
_mesa_hash_table_destroy(ws->bo_names, NULL);
641
_mesa_hash_table_destroy(ws->bo_handles, NULL);
642
_mesa_hash_table_u64_destroy(ws->bo_vas);
643
mtx_destroy(&ws->bo_handles_mutex);
644
mtx_destroy(&ws->vm32.mutex);
645
mtx_destroy(&ws->vm64.mutex);
646
mtx_destroy(&ws->bo_fence_lock);
654
static void radeon_query_info(struct radeon_winsys *rws,
655
struct radeon_info *info,
656
bool enable_smart_access_memory,
657
bool disable_smart_access_memory)
659
*info = ((struct radeon_drm_winsys *)rws)->info;
662
static bool radeon_cs_request_feature(struct radeon_cmdbuf *rcs,
663
enum radeon_feature_id fid,
666
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
669
case RADEON_FID_R300_HYPERZ_ACCESS:
670
return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
671
&cs->ws->hyperz_owner_mutex,
672
RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
675
case RADEON_FID_R300_CMASK_ACCESS:
676
return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
677
&cs->ws->cmask_owner_mutex,
678
RADEON_INFO_WANT_CMASK, "AA optimizations",
684
uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws)
688
if (!ws->info.has_gpu_reset_status_query)
691
radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
692
"gpu-reset-counter", (uint32_t*)&retval);
696
static uint64_t radeon_query_value(struct radeon_winsys *rws,
697
enum radeon_value_id value)
699
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
703
case RADEON_REQUESTED_VRAM_MEMORY:
704
return ws->allocated_vram;
705
case RADEON_REQUESTED_GTT_MEMORY:
706
return ws->allocated_gtt;
707
case RADEON_MAPPED_VRAM:
708
return ws->mapped_vram;
709
case RADEON_MAPPED_GTT:
710
return ws->mapped_gtt;
711
case RADEON_BUFFER_WAIT_TIME_NS:
712
return ws->buffer_wait_time;
713
case RADEON_NUM_MAPPED_BUFFERS:
714
return ws->num_mapped_buffers;
715
case RADEON_TIMESTAMP:
716
if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
721
radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
724
case RADEON_NUM_GFX_IBS:
725
return ws->num_gfx_IBs;
726
case RADEON_NUM_SDMA_IBS:
727
return ws->num_sdma_IBs;
728
case RADEON_NUM_BYTES_MOVED:
729
radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
730
"num-bytes-moved", (uint32_t*)&retval);
732
case RADEON_NUM_EVICTIONS:
733
case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
734
case RADEON_VRAM_VIS_USAGE:
735
case RADEON_GFX_BO_LIST_COUNTER:
736
case RADEON_GFX_IB_SIZE_COUNTER:
737
case RADEON_SLAB_WASTED_VRAM:
738
case RADEON_SLAB_WASTED_GTT:
739
return 0; /* unimplemented */
740
case RADEON_VRAM_USAGE:
741
radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
742
"vram-usage", (uint32_t*)&retval);
744
case RADEON_GTT_USAGE:
745
radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
746
"gtt-usage", (uint32_t*)&retval);
748
case RADEON_GPU_TEMPERATURE:
749
radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
750
"gpu-temp", (uint32_t*)&retval);
752
case RADEON_CURRENT_SCLK:
753
radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
754
"current-gpu-sclk", (uint32_t*)&retval);
756
case RADEON_CURRENT_MCLK:
757
radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
758
"current-gpu-mclk", (uint32_t*)&retval);
760
case RADEON_CS_THREAD_TIME:
761
return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
766
static bool radeon_read_registers(struct radeon_winsys *rws,
768
unsigned num_registers, uint32_t *out)
770
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
773
for (i = 0; i < num_registers; i++) {
774
uint32_t reg = reg_offset + i*4;
776
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, ®))
783
DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true)
785
static bool radeon_winsys_unref(struct radeon_winsys *ws)
787
struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
790
/* When the reference counter drops to zero, remove the fd from the table.
791
* This must happen while the mutex is locked, so that
792
* radeon_drm_winsys_create in another thread doesn't get the winsys
793
* from the table when the counter drops to 0. */
794
mtx_lock(&fd_tab_mutex);
796
destroy = pipe_reference(&rws->reference, NULL);
797
if (destroy && fd_tab) {
798
_mesa_hash_table_remove_key(fd_tab, intptr_to_pointer(rws->fd));
799
if (_mesa_hash_table_num_entries(fd_tab) == 0) {
800
_mesa_hash_table_destroy(fd_tab, NULL);
805
mtx_unlock(&fd_tab_mutex);
809
static void radeon_pin_threads_to_L3_cache(struct radeon_winsys *ws,
812
struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
814
if (util_queue_is_initialized(&rws->cs_queue)) {
815
util_set_thread_affinity(rws->cs_queue.threads[0],
816
util_get_cpu_caps()->L3_affinity_mask[cache],
817
NULL, util_get_cpu_caps()->num_cpu_mask_bits);
821
static bool radeon_cs_is_secure(struct radeon_cmdbuf* cs)
826
PUBLIC struct radeon_winsys *
827
radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
828
radeon_screen_create_t screen_create)
830
struct radeon_drm_winsys *ws;
832
mtx_lock(&fd_tab_mutex);
834
fd_tab = util_hash_table_create_fd_keys();
837
ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
839
pipe_reference(NULL, &ws->reference);
840
mtx_unlock(&fd_tab_mutex);
844
ws = CALLOC_STRUCT(radeon_drm_winsys);
846
mtx_unlock(&fd_tab_mutex);
850
ws->fd = os_dupfd_cloexec(fd);
852
if (!do_winsys_init(ws))
855
pb_cache_init(&ws->bo_cache, RADEON_MAX_CACHED_HEAPS,
856
500000, ws->check_vm ? 1.0f : 2.0f, 0,
857
MIN2(ws->info.vram_size, ws->info.gart_size), NULL,
859
radeon_bo_can_reclaim);
861
if (ws->info.r600_has_virtual_memory) {
862
/* There is no fundamental obstacle to using slab buffer allocation
863
* without GPUVM, but enabling it requires making sure that the drivers
864
* honor the address offset.
866
if (!pb_slabs_init(&ws->bo_slabs,
867
RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2,
868
RADEON_MAX_SLAB_HEAPS, false,
870
radeon_bo_can_reclaim_slab,
871
radeon_bo_slab_alloc,
872
radeon_bo_slab_free))
875
ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2;
877
ws->info.min_alloc_size = ws->info.gart_page_size;
880
if (ws->gen >= DRV_R600) {
881
ws->surf_man = radeon_surface_manager_new(ws->fd);
887
pipe_reference_init(&ws->reference, 1);
890
ws->base.unref = radeon_winsys_unref;
891
ws->base.destroy = radeon_winsys_destroy;
892
ws->base.query_info = radeon_query_info;
893
ws->base.pin_threads_to_L3_cache = radeon_pin_threads_to_L3_cache;
894
ws->base.cs_request_feature = radeon_cs_request_feature;
895
ws->base.query_value = radeon_query_value;
896
ws->base.read_registers = radeon_read_registers;
897
ws->base.cs_is_secure = radeon_cs_is_secure;
899
radeon_drm_bo_init_functions(ws);
900
radeon_drm_cs_init_functions(ws);
901
radeon_surface_init_functions(ws);
903
(void) mtx_init(&ws->hyperz_owner_mutex, mtx_plain);
904
(void) mtx_init(&ws->cmask_owner_mutex, mtx_plain);
906
ws->bo_names = util_hash_table_create_ptr_keys();
907
ws->bo_handles = util_hash_table_create_ptr_keys();
908
ws->bo_vas = _mesa_hash_table_u64_create(NULL);
909
(void) mtx_init(&ws->bo_handles_mutex, mtx_plain);
910
(void) mtx_init(&ws->vm32.mutex, mtx_plain);
911
(void) mtx_init(&ws->vm64.mutex, mtx_plain);
912
(void) mtx_init(&ws->bo_fence_lock, mtx_plain);
913
list_inithead(&ws->vm32.holes);
914
list_inithead(&ws->vm64.holes);
916
/* The kernel currently returns 8MB. Make sure this doesn't change. */
917
if (ws->va_start > 8 * 1024 * 1024) {
918
/* Not enough 32-bit address space. */
919
radeon_winsys_destroy(&ws->base);
920
mtx_unlock(&fd_tab_mutex);
924
ws->vm32.start = ws->va_start;
925
ws->vm32.end = 1ull << 32;
927
/* The maximum is 8GB of virtual address space limited by the kernel.
928
* It's obviously not enough for bigger cards, like Hawaiis with 4GB
929
* and 8GB of physical memory and 4GB of GART.
931
* Older kernels set the limit to 4GB, which is even worse, so they only
932
* have 32-bit address space.
934
if (ws->info.drm_minor >= 41) {
935
ws->vm64.start = 1ull << 32;
936
ws->vm64.end = 1ull << 33;
939
/* TTM aligns the BO size to the CPU page size */
940
ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
941
ws->info.pte_fragment_size = 64 * 1024; /* GPUVM page size */
943
if (ws->num_cpus > 1 && debug_get_option_thread())
944
util_queue_init(&ws->cs_queue, "rcs", 8, 1, 0, NULL);
946
/* Create the screen at the end. The winsys must be initialized
949
* Alternatively, we could create the screen based on "ws->gen"
950
* and link all drivers into one binary blob. */
951
ws->base.screen = screen_create(&ws->base, config);
952
if (!ws->base.screen) {
953
radeon_winsys_destroy(&ws->base);
954
mtx_unlock(&fd_tab_mutex);
958
_mesa_hash_table_insert(fd_tab, intptr_to_pointer(ws->fd), ws);
960
/* We must unlock the mutex once the winsys is fully initialized, so that
961
* other threads attempting to create the winsys from the same fd will
962
* get a fully initialized winsys and not just half-way initialized. */
963
mtx_unlock(&fd_tab_mutex);
968
if (ws->info.r600_has_virtual_memory)
969
pb_slabs_deinit(&ws->bo_slabs);
971
pb_cache_deinit(&ws->bo_cache);
973
mtx_unlock(&fd_tab_mutex);
975
radeon_surface_manager_free(ws->surf_man);
added
removed
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
