2
* Copyright 2015 Intel Corporation
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
* copy of this software and associated documentation files (the "Software"),
6
* to deal in the Software without restriction, including without limitation
7
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
* and/or sell copies of the Software, and to permit persons to whom the
9
* Software is furnished to do so, subject to the following conditions:
11
* The above copyright notice and this permission notice (including the next
12
* paragraph) shall be included in all copies or substantial portions of the
15
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28
#include "genxml/genX_bits.h"
36
#include "isl_gfx12.h"
40
isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
41
uint32_t yt1, uint32_t yt2,
42
char *dst, const char *src,
43
uint32_t dst_pitch, int32_t src_pitch,
45
enum isl_tiling tiling,
46
isl_memcpy_type copy_type)
49
if (copy_type == ISL_MEMCPY_STREAMING_LOAD) {
50
_isl_memcpy_linear_to_tiled_sse41(
51
xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
57
_isl_memcpy_linear_to_tiled(
58
xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
63
isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
64
uint32_t yt1, uint32_t yt2,
65
char *dst, const char *src,
66
int32_t dst_pitch, uint32_t src_pitch,
68
enum isl_tiling tiling,
69
isl_memcpy_type copy_type)
72
if (copy_type == ISL_MEMCPY_STREAMING_LOAD) {
73
_isl_memcpy_tiled_to_linear_sse41(
74
xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
80
_isl_memcpy_tiled_to_linear(
81
xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
85
void PRINTFLIKE(3, 4) UNUSED
86
__isl_finishme(const char *file, int line, const char *fmt, ...)
92
vsnprintf(buf, sizeof(buf), fmt, ap);
95
fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf);
99
isl_device_setup_mocs(struct isl_device *dev)
101
if (dev->info->ver >= 12) {
102
if (intel_device_info_is_dg2(dev->info)) {
103
/* L3CC=WB; BSpec: 45101 */
104
dev->mocs.internal = 3 << 1;
105
dev->mocs.external = 3 << 1;
107
/* XY_BLOCK_COPY_BLT MOCS fields have programming notes which say:
109
* "Destination MOCS value, which is used to program MOCS index
110
* for writing to memory, should select a MOCS register having
111
* "L3 Cacheability Control" programmed as uncacheable(UC) and
112
* "Global GO" parameter set as GOMemory (pushes GO point to
113
* memory). The MOCS Register may have L3 Lookup programmed as
114
* UCL3LKDIS for better efficiency."
116
* The GO:Memory setting requires us to use MOCS 1 or 2. MOCS 2
117
* has LKUP set to 0 and is marked "Non-Coherent", which we assume
118
* is probably the "better efficiency" they mention...
120
* "Source MOCS value, which is used to program MOCS index for
121
* reading from memory, should select a MOCS register having
122
* "L3 Cacheability Control" programmed as uncacheable(UC).
123
* The MOCS Register may have L3 Lookup programmed as UCL3LKDIS
124
* for better efficiency."
126
* Any MOCS except 3 should work. We use MOCS 2...
128
dev->mocs.blitter_dst = 2 << 1;
129
dev->mocs.blitter_src = 2 << 1;
130
} else if (dev->info->platform == INTEL_PLATFORM_DG1) {
132
dev->mocs.internal = 5 << 1;
133
/* Displayables on DG1 are free to cache in L3 since L3 is transient
134
* and flushed at bottom of each submission.
136
dev->mocs.external = 5 << 1;
138
/* TC=1/LLC Only, LeCC=1/UC, LRUM=0, L3CC=3/WB */
139
dev->mocs.external = 61 << 1;
140
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
141
dev->mocs.internal = 2 << 1;
143
/* L1 - HDC:L1 + L3 + LLC */
144
dev->mocs.l1_hdc_l3_llc = 48 << 1;
146
} else if (dev->info->ver >= 9) {
147
/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
148
dev->mocs.external = 1 << 1;
149
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
150
dev->mocs.internal = 2 << 1;
151
} else if (dev->info->ver >= 8) {
152
/* MEMORY_OBJECT_CONTROL_STATE:
153
* .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
154
* .TargetCache = L3DefertoPATforLLCeLLCselection,
157
dev->mocs.external = 0x18;
158
/* MEMORY_OBJECT_CONTROL_STATE:
159
* .MemoryTypeLLCeLLCCacheabilityControl = WB,
160
* .TargetCache = L3DefertoPATforLLCeLLCselection,
163
dev->mocs.internal = 0x78;
164
} else if (dev->info->ver >= 7) {
165
if (dev->info->platform == INTEL_PLATFORM_HSW) {
166
/* MEMORY_OBJECT_CONTROL_STATE:
167
* .LLCeLLCCacheabilityControlLLCCC = 0,
168
* .L3CacheabilityControlL3CC = 1,
170
dev->mocs.internal = 1;
171
dev->mocs.external = 1;
173
/* MEMORY_OBJECT_CONTROL_STATE:
174
* .GraphicsDataTypeGFDT = 0,
175
* .LLCCacheabilityControlLLCCC = 0,
176
* .L3CacheabilityControlL3CC = 1,
178
dev->mocs.internal = 1;
179
dev->mocs.external = 1;
182
dev->mocs.internal = 0;
183
dev->mocs.external = 0;
188
* Return an appropriate MOCS entry for the given usage flags.
191
isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
195
return dev->mocs.external;
197
if (dev->info->verx10 == 120 && dev->info->platform != INTEL_PLATFORM_DG1) {
198
if (usage & ISL_SURF_USAGE_STAGING_BIT)
199
return dev->mocs.internal;
201
if (usage & ISL_SURF_USAGE_CPB_BIT)
202
return dev->mocs.internal;
204
/* Using L1:HDC for storage buffers breaks Vulkan memory model
205
* tests that use shader atomics. This isn't likely to work out,
206
* and we can't know a priori whether they'll be used. So just
207
* continue with ordinary internal MOCS for now.
209
if (usage & ISL_SURF_USAGE_STORAGE_BIT)
210
return dev->mocs.internal;
212
if (usage & (ISL_SURF_USAGE_CONSTANT_BUFFER_BIT |
213
ISL_SURF_USAGE_RENDER_TARGET_BIT |
214
ISL_SURF_USAGE_TEXTURE_BIT))
215
return dev->mocs.l1_hdc_l3_llc;
218
return dev->mocs.internal;
222
isl_device_init(struct isl_device *dev,
223
const struct intel_device_info *info)
225
/* Gfx8+ don't have bit6 swizzling, ensure callsite is not confused. */
226
assert(!(info->has_bit6_swizzle && info->ver >= 8));
229
dev->use_separate_stencil = ISL_GFX_VER(dev) >= 6;
230
dev->has_bit6_swizzling = info->has_bit6_swizzle;
232
/* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
233
* device properties at buildtime. Verify that the macros with the device
234
* properties chosen during runtime.
236
ISL_GFX_VER_SANITIZE(dev);
237
ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev);
239
/* Did we break hiz or stencil? */
240
if (ISL_DEV_USE_SEPARATE_STENCIL(dev))
241
assert(info->has_hiz_and_separate_stencil);
242
if (info->must_use_separate_stencil)
243
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
245
dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
246
dev->ss.align = isl_align(dev->ss.size, 32);
248
dev->ss.clear_color_state_size =
249
isl_align(CLEAR_COLOR_length(info) * 4, 64);
250
dev->ss.clear_color_state_offset =
251
RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;
253
dev->ss.clear_value_size =
254
isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info) +
255
RENDER_SURFACE_STATE_GreenClearColor_bits(info) +
256
RENDER_SURFACE_STATE_BlueClearColor_bits(info) +
257
RENDER_SURFACE_STATE_AlphaClearColor_bits(info), 32) / 8;
259
dev->ss.clear_value_offset =
260
RENDER_SURFACE_STATE_RedClearColor_start(info) / 32 * 4;
262
assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) % 8 == 0);
263
dev->ss.addr_offset =
264
RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) / 8;
266
/* The "Auxiliary Surface Base Address" field starts a bit higher up
267
* because the bottom 12 bits are used for other things. Round down to
268
* the nearest dword before.
270
dev->ss.aux_addr_offset =
271
(RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info) & ~31) / 8;
273
dev->ds.size = _3DSTATE_DEPTH_BUFFER_length(info) * 4;
274
assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
275
dev->ds.depth_offset =
276
_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
278
if (dev->use_separate_stencil) {
279
dev->ds.size += _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
280
_3DSTATE_HIER_DEPTH_BUFFER_length(info) * 4 +
281
_3DSTATE_CLEAR_PARAMS_length(info) * 4;
283
assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
284
dev->ds.stencil_offset =
285
_3DSTATE_DEPTH_BUFFER_length(info) * 4 +
286
_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) / 8;
288
assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
290
_3DSTATE_DEPTH_BUFFER_length(info) * 4 +
291
_3DSTATE_STENCIL_BUFFER_length(info) * 4 +
292
_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
294
dev->ds.stencil_offset = 0;
295
dev->ds.hiz_offset = 0;
298
if (ISL_GFX_VER(dev) >= 7) {
299
/* From the IVB PRM, SURFACE_STATE::Height,
301
* For typed buffer and structured buffer surfaces, the number
302
* of entries in the buffer ranges from 1 to 2^27. For raw buffer
303
* surfaces, the number of entries in the buffer is the number of bytes
304
* which can range from 1 to 2^30.
306
* This limit is only concerned with raw buffers.
308
dev->max_buffer_size = 1ull << 30;
310
dev->max_buffer_size = 1ull << 27;
313
dev->cpb.size = _3DSTATE_CPSIZE_CONTROL_BUFFER_length(info) * 4;
315
_3DSTATE_CPSIZE_CONTROL_BUFFER_SurfaceBaseAddress_start(info) / 8;
317
isl_device_setup_mocs(dev);
321
* @brief Query the set of multisamples supported by the device.
323
* This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
326
isl_sample_count_mask_t ATTRIBUTE_CONST
327
isl_device_get_sample_counts(struct isl_device *dev)
329
if (ISL_GFX_VER(dev) >= 9) {
330
return ISL_SAMPLE_COUNT_1_BIT |
331
ISL_SAMPLE_COUNT_2_BIT |
332
ISL_SAMPLE_COUNT_4_BIT |
333
ISL_SAMPLE_COUNT_8_BIT |
334
ISL_SAMPLE_COUNT_16_BIT;
335
} else if (ISL_GFX_VER(dev) >= 8) {
336
return ISL_SAMPLE_COUNT_1_BIT |
337
ISL_SAMPLE_COUNT_2_BIT |
338
ISL_SAMPLE_COUNT_4_BIT |
339
ISL_SAMPLE_COUNT_8_BIT;
340
} else if (ISL_GFX_VER(dev) >= 7) {
341
return ISL_SAMPLE_COUNT_1_BIT |
342
ISL_SAMPLE_COUNT_4_BIT |
343
ISL_SAMPLE_COUNT_8_BIT;
344
} else if (ISL_GFX_VER(dev) >= 6) {
345
return ISL_SAMPLE_COUNT_1_BIT |
346
ISL_SAMPLE_COUNT_4_BIT;
348
return ISL_SAMPLE_COUNT_1_BIT;
353
* Returns an isl_tile_info representation of the given isl_tiling when
354
* combined when used in the given configuration.
356
* @param[in] tiling The tiling format to introspect
357
* @param[in] dim The dimensionality of the surface being tiled
358
* @param[in] msaa_layout The layout of samples in the surface being tiled
359
* @param[in] format_bpb The number of bits per surface element (block) for
360
* the surface being tiled
361
* @param[in] samples The samples in the surface being tiled
362
* @param[out] tile_info Return parameter for the tiling information
365
isl_tiling_get_info(enum isl_tiling tiling,
366
enum isl_surf_dim dim,
367
enum isl_msaa_layout msaa_layout,
370
struct isl_tile_info *tile_info)
372
const uint32_t bs = format_bpb / 8;
373
struct isl_extent4d logical_el;
374
struct isl_extent2d phys_B;
376
if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) {
377
/* It is possible to have non-power-of-two formats in a tiled buffer.
378
* The easiest way to handle this is to treat the tile as if it is three
379
* times as wide. This way no pixel will ever cross a tile boundary.
380
* This really only works on a subset of tiling formats.
382
assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0 ||
383
tiling == ISL_TILING_4);
384
assert(bs % 3 == 0 && isl_is_pow2(format_bpb / 3));
385
isl_tiling_get_info(tiling, dim, msaa_layout, format_bpb / 3, samples,
391
case ISL_TILING_LINEAR:
393
logical_el = isl_extent4d(1, 1, 1, 1);
394
phys_B = isl_extent2d(bs, 1);
399
logical_el = isl_extent4d(512 / bs, 8, 1, 1);
400
phys_B = isl_extent2d(512, 8);
406
logical_el = isl_extent4d(128 / bs, 32, 1, 1);
407
phys_B = isl_extent2d(128, 32);
412
logical_el = isl_extent4d(64, 64, 1, 1);
413
/* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
415
* "If the surface is a stencil buffer (and thus has Tile Mode set
416
* to TILEMODE_WMAJOR), the pitch must be set to 2x the value
417
* computed based on width, as the stencil buffer is stored with two
420
* This, together with the fact that stencil buffers are referred to as
421
* being Y-tiled in the PRMs for older hardware implies that the
422
* physical size of a W-tile is actually the same as for a Y-tile.
424
phys_B = isl_extent2d(128, 32);
428
case ISL_TILING_Ys: {
429
bool is_Ys = tiling == ISL_TILING_Ys;
432
unsigned width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys));
433
unsigned height = 1 << (6 - (ffs(bs) / 2) + (2 * is_Ys));
435
logical_el = isl_extent4d(width / bs, height, 1, 1);
436
phys_B = isl_extent2d(width, height);
440
/* The tables below are taken from the "2D Surfaces" page in the Bspec
441
* which are formulated in terms of the Cv and Cu constants. This is
442
* different from the tables in the "Tile64 Format" page which should be
443
* equivalent but are usually in terms of pixels. Also note that Cv and
444
* Cu are HxW order to match the Bspec table, not WxH order like you
447
* From the Bspec's "Tile64 Format" page:
449
* MSAA Depth/Stencil surface use IMS (Interleaved Multi Samples)
452
* - Use the 1X MSAA (non-MSRT) version of the Tile64 equations and
453
* let the client unit do the swizzling internally
455
* Surfaces using the IMS layout will use the mapping for 1x MSAA.
457
#define tile_extent(bs, cv, cu, a) \
458
isl_extent4d((1 << cu) / bs, 1 << cv, 1, a)
460
/* Only 2D surfaces are handled. */
461
assert(dim == ISL_SURF_DIM_2D);
463
if (samples == 1 || msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
464
switch (format_bpb) {
465
case 128: logical_el = tile_extent(bs, 6, 10, 1); break;
466
case 64: logical_el = tile_extent(bs, 6, 10, 1); break;
467
case 32: logical_el = tile_extent(bs, 7, 9, 1); break;
468
case 16: logical_el = tile_extent(bs, 7, 9, 1); break;
469
case 8: logical_el = tile_extent(bs, 8, 8, 1); break;
470
default: unreachable("Unsupported format size.");
472
} else if (samples == 2) {
473
switch (format_bpb) {
474
case 128: logical_el = tile_extent(bs, 6, 9, 2); break;
475
case 64: logical_el = tile_extent(bs, 6, 9, 2); break;
476
case 32: logical_el = tile_extent(bs, 7, 8, 2); break;
477
case 16: logical_el = tile_extent(bs, 7, 8, 2); break;
478
case 8: logical_el = tile_extent(bs, 8, 7, 2); break;
479
default: unreachable("Unsupported format size.");
482
switch (format_bpb) {
483
case 128: logical_el = tile_extent(bs, 5, 9, 4); break;
484
case 64: logical_el = tile_extent(bs, 5, 9, 4); break;
485
case 32: logical_el = tile_extent(bs, 6, 8, 4); break;
486
case 16: logical_el = tile_extent(bs, 6, 8, 4); break;
487
case 8: logical_el = tile_extent(bs, 7, 7, 4); break;
488
default: unreachable("Unsupported format size.");
494
phys_B.w = logical_el.w * bs;
495
phys_B.h = 64 * 1024 / phys_B.w;
499
/* HiZ buffers are required to have a 128bpb HiZ format. The tiling has
500
* the same physical dimensions as Y-tiling but actually has two HiZ
501
* columns per Y-tiled column.
504
logical_el = isl_extent4d(16, 16, 1, 1);
505
phys_B = isl_extent2d(128, 32);
509
/* CCS surfaces are required to have one of the GENX_CCS_* formats which
510
* have a block size of 1 or 2 bits per block and each CCS element
511
* corresponds to one cache-line pair in the main surface. From the Sky
512
* Lake PRM Vol. 12 in the section on planes:
514
* "The Color Control Surface (CCS) contains the compression status
515
* of the cache-line pairs. The compression state of the cache-line
516
* pair is specified by 2 bits in the CCS. Each CCS cache-line
517
* represents an area on the main surface of 16x16 sets of 128 byte
518
* Y-tiled cache-line-pairs. CCS is always Y tiled."
520
* The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
521
* Since each cache line corresponds to a 16x16 set of cache-line pairs,
522
* that yields total tile area of 128x128 cache-line pairs or CCS
523
* elements. On older hardware, each CCS element is 1 bit and the tile
524
* is 128x256 elements.
526
assert(format_bpb == 1 || format_bpb == 2);
527
logical_el = isl_extent4d(128, 256 / format_bpb, 1, 1);
528
phys_B = isl_extent2d(128, 32);
531
case ISL_TILING_GFX12_CCS:
532
/* From the Bspec, Gen Graphics > Gfx12 > Memory Data Formats > Memory
533
* Compression > Memory Compression - Gfx12:
535
* 4 bits of auxiliary plane data are required for 2 cachelines of
536
* main surface data. This results in a single cacheline of auxiliary
537
* plane data mapping to 4 4K pages of main surface data for the 4K
538
* pages (tile Y ) and 1 64K Tile Ys page.
540
* The Y-tiled pairing bit of 9 shown in the table below that Bspec
541
* section expresses that the 2 cachelines of main surface data are
542
* horizontally adjacent.
544
* TODO: Handle Ys, Yf and their pairing bits.
546
* Therefore, each CCS cacheline represents a 512Bx32 row area and each
547
* element represents a 32Bx4 row area.
549
assert(format_bpb == 4);
550
logical_el = isl_extent4d(16, 8, 1, 1);
551
phys_B = isl_extent2d(64, 1);
555
unreachable("not reached");
558
*tile_info = (struct isl_tile_info) {
560
.format_bpb = format_bpb,
561
.logical_extent_el = logical_el,
562
.phys_extent_B = phys_B,
567
isl_color_value_is_zero(union isl_color_value value,
568
enum isl_format format)
570
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
572
#define RETURN_FALSE_IF_NOT_0(c, i) \
573
if (fmtl->channels.c.bits && value.u32[i] != 0) \
576
RETURN_FALSE_IF_NOT_0(r, 0);
577
RETURN_FALSE_IF_NOT_0(g, 1);
578
RETURN_FALSE_IF_NOT_0(b, 2);
579
RETURN_FALSE_IF_NOT_0(a, 3);
581
#undef RETURN_FALSE_IF_NOT_0
587
isl_color_value_is_zero_one(union isl_color_value value,
588
enum isl_format format)
590
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
592
#define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
593
if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
596
if (isl_format_has_int_channel(format)) {
597
RETURN_FALSE_IF_NOT_0_1(r, 0, u32);
598
RETURN_FALSE_IF_NOT_0_1(g, 1, u32);
599
RETURN_FALSE_IF_NOT_0_1(b, 2, u32);
600
RETURN_FALSE_IF_NOT_0_1(a, 3, u32);
602
RETURN_FALSE_IF_NOT_0_1(r, 0, f32);
603
RETURN_FALSE_IF_NOT_0_1(g, 1, f32);
604
RETURN_FALSE_IF_NOT_0_1(b, 2, f32);
605
RETURN_FALSE_IF_NOT_0_1(a, 3, f32);
608
#undef RETURN_FALSE_IF_NOT_0_1
614
* @param[out] tiling is set only on success
617
isl_surf_choose_tiling(const struct isl_device *dev,
618
const struct isl_surf_init_info *restrict info,
619
enum isl_tiling *tiling)
621
isl_tiling_flags_t tiling_flags = info->tiling_flags;
623
/* HiZ surfaces always use the HiZ tiling */
624
if (info->usage & ISL_SURF_USAGE_HIZ_BIT) {
625
assert(isl_format_is_hiz(info->format));
626
assert(tiling_flags == ISL_TILING_HIZ_BIT);
627
*tiling = isl_tiling_flag_to_enum(tiling_flags);
631
/* CCS surfaces always use the CCS tiling */
632
if (info->usage & ISL_SURF_USAGE_CCS_BIT) {
633
assert(isl_format_get_layout(info->format)->txc == ISL_TXC_CCS);
634
UNUSED bool ivb_ccs = ISL_GFX_VER(dev) < 12 &&
635
tiling_flags == ISL_TILING_CCS_BIT;
636
UNUSED bool tgl_ccs = ISL_GFX_VER(dev) >= 12 &&
637
tiling_flags == ISL_TILING_GFX12_CCS_BIT;
638
assert(ivb_ccs != tgl_ccs);
639
*tiling = isl_tiling_flag_to_enum(tiling_flags);
643
if (ISL_GFX_VERX10(dev) >= 125) {
644
isl_gfx125_filter_tiling(dev, info, &tiling_flags);
645
} else if (ISL_GFX_VER(dev) >= 6) {
646
isl_gfx6_filter_tiling(dev, info, &tiling_flags);
648
isl_gfx4_filter_tiling(dev, info, &tiling_flags);
651
#define CHOOSE(__tiling) \
653
if (tiling_flags & (1u << (__tiling))) { \
654
*tiling = (__tiling); \
659
/* Of the tiling modes remaining, choose the one that offers the best
663
if (info->dim == ISL_SURF_DIM_1D) {
664
/* Prefer linear for 1D surfaces because they do not benefit from
665
* tiling. To the contrary, tiling leads to wasted memory and poor
666
* memory locality due to the swizzling and alignment restrictions
667
* required in tiled surfaces.
669
CHOOSE(ISL_TILING_LINEAR);
672
CHOOSE(ISL_TILING_4);
673
CHOOSE(ISL_TILING_64);
674
CHOOSE(ISL_TILING_Ys);
675
CHOOSE(ISL_TILING_Yf);
676
CHOOSE(ISL_TILING_Y0);
677
CHOOSE(ISL_TILING_X);
678
CHOOSE(ISL_TILING_W);
679
CHOOSE(ISL_TILING_LINEAR);
683
/* No tiling mode accomodates the inputs. */
688
isl_choose_msaa_layout(const struct isl_device *dev,
689
const struct isl_surf_init_info *info,
690
enum isl_tiling tiling,
691
enum isl_msaa_layout *msaa_layout)
693
if (ISL_GFX_VER(dev) >= 8) {
694
return isl_gfx8_choose_msaa_layout(dev, info, tiling, msaa_layout);
695
} else if (ISL_GFX_VER(dev) >= 7) {
696
return isl_gfx7_choose_msaa_layout(dev, info, tiling, msaa_layout);
697
} else if (ISL_GFX_VER(dev) >= 6) {
698
return isl_gfx6_choose_msaa_layout(dev, info, tiling, msaa_layout);
700
return isl_gfx4_choose_msaa_layout(dev, info, tiling, msaa_layout);
705
isl_get_interleaved_msaa_px_size_sa(uint32_t samples)
707
assert(isl_is_pow2(samples));
709
/* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
712
* If the surface is multisampled and it is a depth or stencil surface
713
* or Multisampled Surface StorageFormat in SURFACE_STATE is
714
* MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
717
return (struct isl_extent2d) {
718
.width = 1 << ((ffs(samples) - 0) / 2),
719
.height = 1 << ((ffs(samples) - 1) / 2),
724
isl_msaa_interleaved_scale_px_to_sa(uint32_t samples,
725
uint32_t *width, uint32_t *height)
727
const struct isl_extent2d px_size_sa =
728
isl_get_interleaved_msaa_px_size_sa(samples);
731
*width = isl_align(*width, 2) * px_size_sa.width;
733
*height = isl_align(*height, 2) * px_size_sa.height;
736
static enum isl_array_pitch_span
737
isl_choose_array_pitch_span(const struct isl_device *dev,
738
const struct isl_surf_init_info *restrict info,
739
enum isl_dim_layout dim_layout,
740
const struct isl_extent4d *phys_level0_sa)
742
switch (dim_layout) {
743
case ISL_DIM_LAYOUT_GFX9_1D:
744
case ISL_DIM_LAYOUT_GFX4_2D:
745
if (ISL_GFX_VER(dev) >= 8) {
746
/* QPitch becomes programmable in Broadwell. So choose the
747
* most compact QPitch possible in order to conserve memory.
749
* From the Broadwell PRM >> Volume 2d: Command Reference: Structures
750
* >> RENDER_SURFACE_STATE Surface QPitch (p325):
752
* - Software must ensure that this field is set to a value
753
* sufficiently large such that the array slices in the surface
754
* do not overlap. Refer to the Memory Data Formats section for
755
* information on how surfaces are stored in memory.
757
* - This field specifies the distance in rows between array
758
* slices. It is used only in the following cases:
760
* - Surface Array is enabled OR
761
* - Number of Mulitsamples is not NUMSAMPLES_1 and
762
* Multisampled Surface Storage Format set to MSFMT_MSS OR
763
* - Surface Type is SURFTYPE_CUBE
765
return ISL_ARRAY_PITCH_SPAN_COMPACT;
766
} else if (ISL_GFX_VER(dev) >= 7) {
767
/* Note that Ivybridge introduces
768
* RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
769
* driver more control over the QPitch.
772
if (phys_level0_sa->array_len == 1) {
773
/* The hardware will never use the QPitch. So choose the most
774
* compact QPitch possible in order to conserve memory.
776
return ISL_ARRAY_PITCH_SPAN_COMPACT;
779
if (isl_surf_usage_is_depth_or_stencil(info->usage) ||
780
(info->usage & ISL_SURF_USAGE_HIZ_BIT)) {
781
/* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
782
* Section 6.18.4.7: Surface Arrays (p112):
784
* If Surface Array Spacing is set to ARYSPC_FULL (note that
785
* the depth buffer and stencil buffer have an implied value of
788
return ISL_ARRAY_PITCH_SPAN_FULL;
791
if (info->levels == 1) {
792
/* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
795
return ISL_ARRAY_PITCH_SPAN_COMPACT;
798
return ISL_ARRAY_PITCH_SPAN_FULL;
799
} else if ((ISL_GFX_VER(dev) == 5 || ISL_GFX_VER(dev) == 6) &&
800
ISL_DEV_USE_SEPARATE_STENCIL(dev) &&
801
isl_surf_usage_is_stencil(info->usage)) {
802
/* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
803
* Graphics Core >> Section 7.18.3.7: Surface Arrays:
805
* The separate stencil buffer does not support mip mapping, thus
806
* the storage for LODs other than LOD 0 is not needed.
808
assert(info->levels == 1);
809
return ISL_ARRAY_PITCH_SPAN_COMPACT;
811
if ((ISL_GFX_VER(dev) == 5 || ISL_GFX_VER(dev) == 6) &&
812
ISL_DEV_USE_SEPARATE_STENCIL(dev) &&
813
isl_surf_usage_is_stencil(info->usage)) {
814
/* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
815
* Graphics Core >> Section 7.18.3.7: Surface Arrays:
817
* The separate stencil buffer does not support mip mapping,
818
* thus the storage for LODs other than LOD 0 is not needed.
820
assert(info->levels == 1);
821
assert(phys_level0_sa->array_len == 1);
822
return ISL_ARRAY_PITCH_SPAN_COMPACT;
825
if (phys_level0_sa->array_len == 1) {
826
/* The hardware will never use the QPitch. So choose the most
827
* compact QPitch possible in order to conserve memory.
829
return ISL_ARRAY_PITCH_SPAN_COMPACT;
832
return ISL_ARRAY_PITCH_SPAN_FULL;
835
case ISL_DIM_LAYOUT_GFX4_3D:
836
/* The hardware will never use the QPitch. So choose the most
837
* compact QPitch possible in order to conserve memory.
839
return ISL_ARRAY_PITCH_SPAN_COMPACT;
841
case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
842
/* Each array image in the gfx6 stencil of HiZ surface is compact in the
843
* sense that every LOD is a compact array of the same size as LOD0.
845
return ISL_ARRAY_PITCH_SPAN_COMPACT;
848
unreachable("bad isl_dim_layout");
849
return ISL_ARRAY_PITCH_SPAN_FULL;
853
isl_choose_image_alignment_el(const struct isl_device *dev,
854
const struct isl_surf_init_info *restrict info,
855
enum isl_tiling tiling,
856
enum isl_dim_layout dim_layout,
857
enum isl_msaa_layout msaa_layout,
858
struct isl_extent3d *image_align_el)
860
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
861
if (fmtl->txc == ISL_TXC_MCS) {
863
* IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
865
* Height, width, and layout of MCS buffer in this case must match with
866
* Render Target height, width, and layout. MCS buffer is tiledY.
868
* To avoid wasting memory, choose the smallest alignment possible:
869
* HALIGN_4 and VALIGN_4.
871
*image_align_el = isl_extent3d(4, 4, 1);
873
} else if (fmtl->txc == ISL_TXC_HIZ) {
874
assert(ISL_GFX_VER(dev) >= 6);
875
if (ISL_GFX_VER(dev) == 6) {
876
/* HiZ surfaces on Sandy Bridge are packed tightly. */
877
*image_align_el = isl_extent3d(1, 1, 1);
878
} else if (ISL_GFX_VER(dev) < 12) {
879
/* On gfx7+, HiZ surfaces are always aligned to 16x8 pixels in the
880
* primary surface which works out to 2x2 HiZ elments.
882
*image_align_el = isl_extent3d(2, 2, 1);
884
/* We choose the alignments based on the docs and what we've seen on
885
* prior platforms. From the TGL PRM Vol. 9, "Hierarchical Depth
888
* The height and width of the hierarchical depth buffer that must
889
* be allocated are computed by the following formulas, where HZ
890
* is the hierarchical depth buffer and Z is the depth buffer. The
891
* Z_Height, Z_Width, and Z_Depth values given in these formulas
892
* are those present in 3DSTATE_DEPTH_BUFFER incremented by one.
894
* The note about 3DSTATE_DEPTH_BUFFER tells us that the dimensions
895
* in the following formula refers to the base level. The key formula
896
* for the horizontal alignment is:
898
* HZ_Width (bytes) [=]
899
* ceiling(Z_Width / 16) * 16
901
* This type of formula is used when sizing compression blocks. So,
902
* the docs seem to say that the HiZ format has a block width of 16,
903
* and thus, the surface has a minimum horizontal alignment of 16
904
* pixels. This formula hasn't changed from prior platforms (where
905
* we've chosen a horizontal alignment of 16), so we should be on the
906
* right track. As for the vertical alignment, we're told:
908
* To compute the minimum QPitch for the HZ surface, the height of
909
* each LOD in pixels is determined using the equations for hL in
910
* the GPU Overview volume, using a vertical alignment j=16.
912
* We're not calculating the QPitch right now, but the vertical
913
* alignment is plainly given as 16 rows in the depth buffer.
915
* As a result, we believe that HiZ surfaces are aligned to 16x16
916
* pixels in the primary surface. We divide this area by the HiZ
917
* block dimensions to get the alignment in terms of HiZ blocks.
919
*image_align_el = isl_extent3d(16 / fmtl->bw, 16 / fmtl->bh, 1);
924
if (ISL_GFX_VERX10(dev) >= 125) {
925
isl_gfx125_choose_image_alignment_el(dev, info, tiling, dim_layout,
926
msaa_layout, image_align_el);
927
} else if (ISL_GFX_VER(dev) >= 12) {
928
isl_gfx12_choose_image_alignment_el(dev, info, tiling, dim_layout,
929
msaa_layout, image_align_el);
930
} else if (ISL_GFX_VER(dev) >= 9) {
931
isl_gfx9_choose_image_alignment_el(dev, info, tiling, dim_layout,
932
msaa_layout, image_align_el);
933
} else if (ISL_GFX_VER(dev) >= 8) {
934
isl_gfx8_choose_image_alignment_el(dev, info, tiling, dim_layout,
935
msaa_layout, image_align_el);
936
} else if (ISL_GFX_VER(dev) >= 7) {
937
isl_gfx7_choose_image_alignment_el(dev, info, tiling, dim_layout,
938
msaa_layout, image_align_el);
939
} else if (ISL_GFX_VER(dev) >= 6) {
940
isl_gfx6_choose_image_alignment_el(dev, info, tiling, dim_layout,
941
msaa_layout, image_align_el);
943
isl_gfx4_choose_image_alignment_el(dev, info, tiling, dim_layout,
944
msaa_layout, image_align_el);
948
static enum isl_dim_layout
949
isl_surf_choose_dim_layout(const struct isl_device *dev,
950
enum isl_surf_dim logical_dim,
951
enum isl_tiling tiling,
952
isl_surf_usage_flags_t usage)
954
/* Sandy bridge needs a special layout for HiZ and stencil. */
955
if (ISL_GFX_VER(dev) == 6 &&
956
(tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ))
957
return ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ;
959
if (ISL_GFX_VER(dev) >= 9) {
960
switch (logical_dim) {
961
case ISL_SURF_DIM_1D:
962
/* From the Sky Lake PRM Vol. 5, "1D Surfaces":
964
* One-dimensional surfaces use a tiling mode of linear.
965
* Technically, they are not tiled resources, but the Tiled
966
* Resource Mode field in RENDER_SURFACE_STATE is still used to
967
* indicate the alignment requirements for this linear surface
968
* (See 1D Alignment requirements for how 4K and 64KB Tiled
969
* Resource Modes impact alignment). Alternatively, a 1D surface
970
* can be defined as a 2D tiled surface (e.g. TileY or TileX) with
973
* In other words, ISL_DIM_LAYOUT_GFX9_1D is only used for linear
974
* surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GFX4_2D is used.
976
if (tiling == ISL_TILING_LINEAR)
977
return ISL_DIM_LAYOUT_GFX9_1D;
979
return ISL_DIM_LAYOUT_GFX4_2D;
980
case ISL_SURF_DIM_2D:
981
case ISL_SURF_DIM_3D:
982
return ISL_DIM_LAYOUT_GFX4_2D;
985
switch (logical_dim) {
986
case ISL_SURF_DIM_1D:
987
case ISL_SURF_DIM_2D:
988
/* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
990
* The cube face textures are stored in the same way as 3D surfaces
991
* are stored (see section 6.17.5 for details). For cube surfaces,
992
* however, the depth is equal to the number of faces (always 6) and
993
* is not reduced for each MIP.
995
if (ISL_GFX_VER(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
996
return ISL_DIM_LAYOUT_GFX4_3D;
998
return ISL_DIM_LAYOUT_GFX4_2D;
999
case ISL_SURF_DIM_3D:
1000
return ISL_DIM_LAYOUT_GFX4_3D;
1004
unreachable("bad isl_surf_dim");
1005
return ISL_DIM_LAYOUT_GFX4_2D;
1009
* Calculate the physical extent of the surface's first level, in units of
1013
isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
1014
const struct isl_surf_init_info *restrict info,
1015
enum isl_dim_layout dim_layout,
1016
enum isl_tiling tiling,
1017
enum isl_msaa_layout msaa_layout,
1018
struct isl_extent4d *phys_level0_sa)
1020
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1022
if (isl_format_is_planar(info->format))
1023
unreachable("Planar formats unsupported");
1025
switch (info->dim) {
1026
case ISL_SURF_DIM_1D:
1027
assert(info->height == 1);
1028
assert(info->depth == 1);
1029
assert(info->samples == 1);
1031
switch (dim_layout) {
1032
case ISL_DIM_LAYOUT_GFX4_3D:
1033
unreachable("bad isl_dim_layout");
1035
case ISL_DIM_LAYOUT_GFX9_1D:
1036
case ISL_DIM_LAYOUT_GFX4_2D:
1037
case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
1038
*phys_level0_sa = (struct isl_extent4d) {
1042
.a = info->array_len,
1048
case ISL_SURF_DIM_2D:
1049
if (ISL_GFX_VER(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT))
1050
assert(dim_layout == ISL_DIM_LAYOUT_GFX4_3D);
1052
assert(dim_layout == ISL_DIM_LAYOUT_GFX4_2D ||
1053
dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
1055
if (tiling == ISL_TILING_Ys && info->samples > 1)
1056
isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__);
1058
switch (msaa_layout) {
1059
case ISL_MSAA_LAYOUT_NONE:
1060
assert(info->depth == 1);
1061
assert(info->samples == 1);
1063
*phys_level0_sa = (struct isl_extent4d) {
1067
.a = info->array_len,
1071
case ISL_MSAA_LAYOUT_ARRAY:
1072
assert(info->depth == 1);
1073
assert(info->levels == 1);
1074
assert(isl_format_supports_multisampling(dev->info, info->format));
1075
assert(fmtl->bw == 1 && fmtl->bh == 1);
1077
*phys_level0_sa = (struct isl_extent4d) {
1081
.a = info->array_len * info->samples,
1085
case ISL_MSAA_LAYOUT_INTERLEAVED:
1086
assert(info->depth == 1);
1087
assert(info->levels == 1);
1088
assert(isl_format_supports_multisampling(dev->info, info->format));
1090
*phys_level0_sa = (struct isl_extent4d) {
1094
.a = info->array_len,
1097
isl_msaa_interleaved_scale_px_to_sa(info->samples,
1099
&phys_level0_sa->h);
1104
case ISL_SURF_DIM_3D:
1105
assert(info->array_len == 1);
1106
assert(info->samples == 1);
1109
isl_finishme("%s:%s: compression block with depth > 1",
1110
__FILE__, __func__);
1113
switch (dim_layout) {
1114
case ISL_DIM_LAYOUT_GFX9_1D:
1115
case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
1116
unreachable("bad isl_dim_layout");
1118
case ISL_DIM_LAYOUT_GFX4_2D:
1119
assert(ISL_GFX_VER(dev) >= 9);
1121
*phys_level0_sa = (struct isl_extent4d) {
1129
case ISL_DIM_LAYOUT_GFX4_3D:
1130
assert(ISL_GFX_VER(dev) < 9);
1131
*phys_level0_sa = (struct isl_extent4d) {
1144
* Calculate the pitch between physical array slices, in units of rows of
1148
isl_calc_array_pitch_el_rows_gfx4_2d(
1149
const struct isl_device *dev,
1150
const struct isl_surf_init_info *restrict info,
1151
const struct isl_tile_info *tile_info,
1152
const struct isl_extent3d *image_align_sa,
1153
const struct isl_extent4d *phys_level0_sa,
1154
enum isl_array_pitch_span array_pitch_span,
1155
const struct isl_extent2d *phys_slice0_sa)
1157
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1158
uint32_t pitch_sa_rows = 0;
1160
switch (array_pitch_span) {
1161
case ISL_ARRAY_PITCH_SPAN_COMPACT:
1162
pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
1164
case ISL_ARRAY_PITCH_SPAN_FULL: {
1165
/* The QPitch equation is found in the Broadwell PRM >> Volume 5:
1166
* Memory Views >> Common Surface Formats >> Surface Layout >> 2D
1167
* Surfaces >> Surface Arrays.
1169
uint32_t H0_sa = phys_level0_sa->h;
1170
uint32_t H1_sa = isl_minify(H0_sa, 1);
1172
uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
1173
uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
1176
if (ISL_GFX_VER(dev) >= 7) {
1177
/* The QPitch equation changed slightly in Ivybridge. */
1183
pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
1185
if (ISL_GFX_VER(dev) == 6 && info->samples > 1 &&
1186
(info->height % 4 == 1)) {
1187
/* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
1188
* Graphics Core >> Section 7.18.3.7: Surface Arrays:
1190
* [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
1191
* the value calculated in the equation above , for every
1192
* other odd Surface Height starting from 1 i.e. 1,5,9,13.
1194
* XXX(chadv): Is the errata natural corollary of the physical
1195
* layout of interleaved samples?
1200
pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
1205
assert(pitch_sa_rows % fmtl->bh == 0);
1206
uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
1208
if (ISL_GFX_VER(dev) >= 9 && ISL_GFX_VER(dev) <= 11 &&
1209
fmtl->txc == ISL_TXC_CCS) {
1211
* From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
1213
* "Mip-mapped and arrayed surfaces are supported with MCS buffer
1214
* layout with these alignments in the RT space: Horizontal
1215
* Alignment = 128 and Vertical Alignment = 64."
1217
* From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
1219
* "For non-multisampled render target's CCS auxiliary surface,
1220
* QPitch must be computed with Horizontal Alignment = 128 and
1221
* Surface Vertical Alignment = 256. These alignments are only for
1222
* CCS buffer and not for associated render target."
1224
* The first restriction is already handled by isl_choose_image_alignment_el
1225
* but the second restriction, which is an extension of the first, only
1226
* applies to qpitch and must be applied here.
1228
* The second restriction disappears on Gfx12.
1230
assert(fmtl->bh == 4);
1231
pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
1234
if (ISL_GFX_VER(dev) >= 9 &&
1235
info->dim == ISL_SURF_DIM_3D &&
1236
tile_info->tiling != ISL_TILING_LINEAR) {
1237
/* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
1239
* Tile Mode != Linear: This field must be set to an integer multiple
1240
* of the tile height
1242
pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
1245
return pitch_el_rows;
1249
* A variant of isl_calc_phys_slice0_extent_sa() specific to
1250
* ISL_DIM_LAYOUT_GFX4_2D.
1253
isl_calc_phys_slice0_extent_sa_gfx4_2d(
1254
const struct isl_device *dev,
1255
const struct isl_surf_init_info *restrict info,
1256
enum isl_msaa_layout msaa_layout,
1257
const struct isl_extent3d *image_align_sa,
1258
const struct isl_extent4d *phys_level0_sa,
1259
struct isl_extent2d *phys_slice0_sa)
1261
assert(phys_level0_sa->depth == 1);
1263
if (info->levels == 1) {
1264
/* Do not pad the surface to the image alignment.
1266
* For tiled surfaces, using a reduced alignment here avoids wasting CPU
1267
* cycles on the below mipmap layout caluclations. Reducing the
1268
* alignment here is safe because we later align the row pitch and array
1269
* pitch to the tile boundary. It is safe even for
1270
* ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
1271
* to accomodate the interleaved samples.
1273
* For linear surfaces, reducing the alignment here permits us to later
1274
* choose an arbitrary, non-aligned row pitch. If the surface backs
1275
* a VkBuffer, then an arbitrary pitch may be needed to accomodate
1276
* VkBufferImageCopy::bufferRowLength.
1278
*phys_slice0_sa = (struct isl_extent2d) {
1279
.w = phys_level0_sa->w,
1280
.h = phys_level0_sa->h,
1285
uint32_t slice_top_w = 0;
1286
uint32_t slice_bottom_w = 0;
1287
uint32_t slice_left_h = 0;
1288
uint32_t slice_right_h = 0;
1290
uint32_t W0 = phys_level0_sa->w;
1291
uint32_t H0 = phys_level0_sa->h;
1293
for (uint32_t l = 0; l < info->levels; ++l) {
1294
uint32_t W = isl_minify(W0, l);
1295
uint32_t H = isl_minify(H0, l);
1297
uint32_t w = isl_align_npot(W, image_align_sa->w);
1298
uint32_t h = isl_align_npot(H, image_align_sa->h);
1304
} else if (l == 1) {
1307
} else if (l == 2) {
1308
slice_bottom_w += w;
1315
*phys_slice0_sa = (struct isl_extent2d) {
1316
.w = MAX(slice_top_w, slice_bottom_w),
1317
.h = MAX(slice_left_h, slice_right_h),
1322
isl_calc_phys_total_extent_el_gfx4_2d(
1323
const struct isl_device *dev,
1324
const struct isl_surf_init_info *restrict info,
1325
const struct isl_tile_info *tile_info,
1326
enum isl_msaa_layout msaa_layout,
1327
const struct isl_extent3d *image_align_sa,
1328
const struct isl_extent4d *phys_level0_sa,
1329
enum isl_array_pitch_span array_pitch_span,
1330
uint32_t *array_pitch_el_rows,
1331
struct isl_extent4d *phys_total_el)
1333
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1335
struct isl_extent2d phys_slice0_sa;
1336
isl_calc_phys_slice0_extent_sa_gfx4_2d(dev, info, msaa_layout,
1337
image_align_sa, phys_level0_sa,
1339
*array_pitch_el_rows =
1340
isl_calc_array_pitch_el_rows_gfx4_2d(dev, info, tile_info,
1341
image_align_sa, phys_level0_sa,
1345
if (tile_info->tiling == ISL_TILING_64) {
1346
*phys_total_el = (struct isl_extent4d) {
1347
.w = isl_align_div_npot(phys_slice0_sa.w, fmtl->bw),
1348
.h = isl_align_div_npot(phys_slice0_sa.h, fmtl->bh),
1349
.d = isl_align_div_npot(phys_level0_sa->d, fmtl->bd),
1350
.a = phys_level0_sa->array_len,
1353
*phys_total_el = (struct isl_extent4d) {
1354
.w = isl_align_div_npot(phys_slice0_sa.w, fmtl->bw),
1355
.h = *array_pitch_el_rows * (phys_level0_sa->array_len - 1) +
1356
isl_align_div_npot(phys_slice0_sa.h, fmtl->bh),
1364
* A variant of isl_calc_phys_slice0_extent_sa() specific to
1365
* ISL_DIM_LAYOUT_GFX4_3D.
1368
isl_calc_phys_total_extent_el_gfx4_3d(
1369
const struct isl_device *dev,
1370
const struct isl_surf_init_info *restrict info,
1371
const struct isl_extent3d *image_align_sa,
1372
const struct isl_extent4d *phys_level0_sa,
1373
uint32_t *array_pitch_el_rows,
1374
struct isl_extent4d *phys_total_el)
1376
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1378
assert(info->samples == 1);
1380
if (info->dim != ISL_SURF_DIM_3D) {
1381
/* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1383
* The cube face textures are stored in the same way as 3D surfaces
1384
* are stored (see section 6.17.5 for details). For cube surfaces,
1385
* however, the depth is equal to the number of faces (always 6) and
1386
* is not reduced for each MIP.
1388
assert(ISL_GFX_VER(dev) == 4);
1389
assert(info->usage & ISL_SURF_USAGE_CUBE_BIT);
1390
assert(phys_level0_sa->array_len == 6);
1392
assert(phys_level0_sa->array_len == 1);
1395
uint32_t total_w = 0;
1396
uint32_t total_h = 0;
1398
uint32_t W0 = phys_level0_sa->w;
1399
uint32_t H0 = phys_level0_sa->h;
1400
uint32_t D0 = phys_level0_sa->d;
1401
uint32_t A0 = phys_level0_sa->a;
1403
for (uint32_t l = 0; l < info->levels; ++l) {
1404
uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w);
1405
uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h);
1406
uint32_t level_d = info->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : A0;
1408
uint32_t max_layers_horiz = MIN(level_d, 1u << l);
1409
uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
1411
total_w = MAX(total_w, level_w * max_layers_horiz);
1412
total_h += level_h * max_layers_vert;
1415
/* GFX4_3D layouts don't really have an array pitch since each LOD has a
1416
* different number of horizontal and vertical layers. We have to set it
1417
* to something, so at least make it true for LOD0.
1419
*array_pitch_el_rows =
1420
isl_align_npot(phys_level0_sa->h, image_align_sa->h) / fmtl->bw;
1421
*phys_total_el = (struct isl_extent4d) {
1422
.w = isl_assert_div(total_w, fmtl->bw),
1423
.h = isl_assert_div(total_h, fmtl->bh),
1430
* A variant of isl_calc_phys_slice0_extent_sa() specific to
1431
* ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ.
1434
isl_calc_phys_total_extent_el_gfx6_stencil_hiz(
1435
const struct isl_device *dev,
1436
const struct isl_surf_init_info *restrict info,
1437
const struct isl_tile_info *tile_info,
1438
const struct isl_extent3d *image_align_sa,
1439
const struct isl_extent4d *phys_level0_sa,
1440
uint32_t *array_pitch_el_rows,
1441
struct isl_extent4d *phys_total_el)
1443
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1445
const struct isl_extent2d tile_extent_sa = {
1446
.w = tile_info->logical_extent_el.w * fmtl->bw,
1447
.h = tile_info->logical_extent_el.h * fmtl->bh,
1449
/* Tile size is a multiple of image alignment */
1450
assert(tile_extent_sa.w % image_align_sa->w == 0);
1451
assert(tile_extent_sa.h % image_align_sa->h == 0);
1453
const uint32_t W0 = phys_level0_sa->w;
1454
const uint32_t H0 = phys_level0_sa->h;
1456
/* Each image has the same height as LOD0 because the hardware thinks
1457
* everything is LOD0
1459
const uint32_t H = isl_align(H0, image_align_sa->h) * phys_level0_sa->a;
1461
uint32_t total_top_w = 0;
1462
uint32_t total_bottom_w = 0;
1463
uint32_t total_h = 0;
1465
for (uint32_t l = 0; l < info->levels; ++l) {
1466
const uint32_t W = isl_minify(W0, l);
1468
const uint32_t w = isl_align(W, tile_extent_sa.w);
1469
const uint32_t h = isl_align(H, tile_extent_sa.h);
1474
} else if (l == 1) {
1478
total_bottom_w += w;
1482
*array_pitch_el_rows =
1483
isl_assert_div(isl_align(H0, image_align_sa->h), fmtl->bh);
1484
*phys_total_el = (struct isl_extent4d) {
1485
.w = isl_assert_div(MAX(total_top_w, total_bottom_w), fmtl->bw),
1486
.h = isl_assert_div(total_h, fmtl->bh),
1493
* A variant of isl_calc_phys_slice0_extent_sa() specific to
1494
* ISL_DIM_LAYOUT_GFX9_1D.
1497
isl_calc_phys_total_extent_el_gfx9_1d(
1498
const struct isl_device *dev,
1499
const struct isl_surf_init_info *restrict info,
1500
const struct isl_extent3d *image_align_sa,
1501
const struct isl_extent4d *phys_level0_sa,
1502
uint32_t *array_pitch_el_rows,
1503
struct isl_extent4d *phys_total_el)
1505
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1507
assert(phys_level0_sa->height == 1);
1508
assert(phys_level0_sa->depth == 1);
1509
assert(info->samples == 1);
1510
assert(image_align_sa->w >= fmtl->bw);
1512
uint32_t slice_w = 0;
1513
const uint32_t W0 = phys_level0_sa->w;
1515
for (uint32_t l = 0; l < info->levels; ++l) {
1516
uint32_t W = isl_minify(W0, l);
1517
uint32_t w = isl_align_npot(W, image_align_sa->w);
1522
*array_pitch_el_rows = 1;
1523
*phys_total_el = (struct isl_extent4d) {
1524
.w = isl_assert_div(slice_w, fmtl->bw),
1525
.h = phys_level0_sa->array_len,
1532
* Calculate the two-dimensional total physical extent of the surface, in
1533
* units of surface elements.
1536
isl_calc_phys_total_extent_el(const struct isl_device *dev,
1537
const struct isl_surf_init_info *restrict info,
1538
const struct isl_tile_info *tile_info,
1539
enum isl_dim_layout dim_layout,
1540
enum isl_msaa_layout msaa_layout,
1541
const struct isl_extent3d *image_align_sa,
1542
const struct isl_extent4d *phys_level0_sa,
1543
enum isl_array_pitch_span array_pitch_span,
1544
uint32_t *array_pitch_el_rows,
1545
struct isl_extent4d *phys_total_el)
1547
switch (dim_layout) {
1548
case ISL_DIM_LAYOUT_GFX9_1D:
1549
assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
1550
isl_calc_phys_total_extent_el_gfx9_1d(dev, info,
1551
image_align_sa, phys_level0_sa,
1552
array_pitch_el_rows,
1555
case ISL_DIM_LAYOUT_GFX4_2D:
1556
isl_calc_phys_total_extent_el_gfx4_2d(dev, info, tile_info, msaa_layout,
1557
image_align_sa, phys_level0_sa,
1559
array_pitch_el_rows,
1562
case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
1563
assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
1564
isl_calc_phys_total_extent_el_gfx6_stencil_hiz(dev, info, tile_info,
1567
array_pitch_el_rows,
1570
case ISL_DIM_LAYOUT_GFX4_3D:
1571
assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
1572
isl_calc_phys_total_extent_el_gfx4_3d(dev, info,
1573
image_align_sa, phys_level0_sa,
1574
array_pitch_el_rows,
1579
unreachable("invalid value for dim_layout");
1583
isl_calc_row_pitch_alignment(const struct isl_device *dev,
1584
const struct isl_surf_init_info *surf_info,
1585
const struct isl_tile_info *tile_info)
1587
if (tile_info->tiling != ISL_TILING_LINEAR) {
1588
/* According to BSpec: 44930, Gfx12's CCS-compressed surface pitches must
1589
* be 512B-aligned. CCS is only support on Y tilings.
1591
* Only consider 512B alignment when :
1592
* - AUX is not explicitly disabled
1593
* - the caller has specified no pitch
1595
* isl_surf_get_ccs_surf() will check that the main surface alignment
1596
* matches CCS expectations.
1598
if (ISL_GFX_VER(dev) >= 12 &&
1599
isl_format_supports_ccs_e(dev->info, surf_info->format) &&
1600
tile_info->tiling != ISL_TILING_X &&
1601
!(surf_info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) &&
1602
surf_info->row_pitch_B == 0) {
1603
return isl_align(tile_info->phys_extent_B.width, 512);
1606
return tile_info->phys_extent_B.width;
1609
/* We only support tiled fragment shading rate buffers. */
1610
assert((surf_info->usage & ISL_SURF_USAGE_CPB_BIT) == 0);
1612
/* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1613
* RENDER_SURFACE_STATE Surface Pitch (p349):
1615
* - For linear render target surfaces and surfaces accessed with the
1616
* typed data port messages, the pitch must be a multiple of the
1617
* element size for non-YUV surface formats. Pitch must be
1618
* a multiple of 2 * element size for YUV surface formats.
1620
* - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1621
* ignore because isl doesn't do buffers.]
1623
* - For other linear surfaces, the pitch can be any multiple of
1626
const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
1627
const uint32_t bs = fmtl->bpb / 8;
1630
if (surf_info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
1631
if (isl_format_is_yuv(surf_info->format)) {
1640
/* From the Broadwell PRM >> Volume 2c: Command Reference: Registers >>
1641
* PRI_STRIDE Stride (p1254):
1643
* "When using linear memory, this must be at least 64 byte aligned."
1645
* However, when displaying on NVIDIA and recent AMD GPUs via PRIME,
1646
* we need a larger pitch of 256 bytes.
1648
* If the ISL caller didn't specify a row_pitch_B, then we should assume
1649
* the NVIDIA/AMD requirements. Otherwise, if we have a specified
1650
* row_pitch_B, this is probably because the caller is trying to import a
1651
* buffer. In that case we limit the minimum row pitch to the Intel HW
1654
if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
1655
if (surf_info->row_pitch_B == 0)
1656
alignment = isl_align(alignment, 256);
1658
alignment = isl_align(alignment, 64);
1665
isl_calc_linear_min_row_pitch(const struct isl_device *dev,
1666
const struct isl_surf_init_info *info,
1667
const struct isl_extent4d *phys_total_el,
1668
uint32_t alignment_B)
1670
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1671
const uint32_t bs = fmtl->bpb / 8;
1673
return isl_align_npot(bs * phys_total_el->w, alignment_B);
1677
isl_calc_tiled_min_row_pitch(const struct isl_device *dev,
1678
const struct isl_surf_init_info *surf_info,
1679
const struct isl_tile_info *tile_info,
1680
const struct isl_extent4d *phys_total_el,
1681
uint32_t alignment_B)
1683
const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
1685
assert(fmtl->bpb % tile_info->format_bpb == 0);
1687
const uint32_t tile_el_scale = fmtl->bpb / tile_info->format_bpb;
1688
const uint32_t total_w_tl =
1689
isl_align_div(phys_total_el->w * tile_el_scale,
1690
tile_info->logical_extent_el.width);
1692
/* In some cases the alignment of the pitch might be > to the tile size
1693
* (for example Gfx12 CCS requires 512B alignment while the tile's width
1694
* can be 128B), so align the row pitch to the alignment.
1696
assert(alignment_B >= tile_info->phys_extent_B.width);
1697
return isl_align(total_w_tl * tile_info->phys_extent_B.width, alignment_B);
1701
isl_calc_min_row_pitch(const struct isl_device *dev,
1702
const struct isl_surf_init_info *surf_info,
1703
const struct isl_tile_info *tile_info,
1704
const struct isl_extent4d *phys_total_el,
1705
uint32_t alignment_B)
1707
if (tile_info->tiling == ISL_TILING_LINEAR) {
1708
return isl_calc_linear_min_row_pitch(dev, surf_info, phys_total_el,
1711
return isl_calc_tiled_min_row_pitch(dev, surf_info, tile_info,
1712
phys_total_el, alignment_B);
1717
* Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1718
* size is `bits` bits?
1720
* Hardware pitch fields are offset by 1. For example, if the size of
1721
* RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1722
* pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1723
* RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1726
pitch_in_range(uint32_t n, uint32_t bits)
1729
return likely(bits != 0 && 1 <= n && n <= (1 << bits));
1733
isl_calc_row_pitch(const struct isl_device *dev,
1734
const struct isl_surf_init_info *surf_info,
1735
const struct isl_tile_info *tile_info,
1736
enum isl_dim_layout dim_layout,
1737
const struct isl_extent4d *phys_total_el,
1738
uint32_t *out_row_pitch_B)
1740
uint32_t alignment_B =
1741
isl_calc_row_pitch_alignment(dev, surf_info, tile_info);
1743
const uint32_t min_row_pitch_B =
1744
isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el,
1747
if (surf_info->row_pitch_B != 0) {
1748
if (surf_info->row_pitch_B < min_row_pitch_B)
1751
if (surf_info->row_pitch_B % alignment_B != 0)
1755
const uint32_t row_pitch_B =
1756
surf_info->row_pitch_B != 0 ? surf_info->row_pitch_B : min_row_pitch_B;
1758
const uint32_t row_pitch_tl = row_pitch_B / tile_info->phys_extent_B.width;
1760
if (row_pitch_B == 0)
1763
if (dim_layout == ISL_DIM_LAYOUT_GFX9_1D) {
1764
/* SurfacePitch is ignored for this layout. */
1768
if ((surf_info->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
1769
ISL_SURF_USAGE_TEXTURE_BIT |
1770
ISL_SURF_USAGE_STORAGE_BIT)) &&
1771
!pitch_in_range(row_pitch_B, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info)))
1774
if ((surf_info->usage & (ISL_SURF_USAGE_CCS_BIT |
1775
ISL_SURF_USAGE_MCS_BIT)) &&
1776
!pitch_in_range(row_pitch_tl, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info)))
1779
if ((surf_info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1780
!pitch_in_range(row_pitch_B, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
1783
if ((surf_info->usage & ISL_SURF_USAGE_HIZ_BIT) &&
1784
!pitch_in_range(row_pitch_B, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
1787
const uint32_t stencil_pitch_bits = dev->use_separate_stencil ?
1788
_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev->info) :
1789
_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info);
1791
if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
1792
!pitch_in_range(row_pitch_B, stencil_pitch_bits))
1795
if ((surf_info->usage & ISL_SURF_USAGE_CPB_BIT) &&
1796
!pitch_in_range(row_pitch_B, _3DSTATE_CPSIZE_CONTROL_BUFFER_SurfacePitch_bits(dev->info)))
1800
*out_row_pitch_B = row_pitch_B;
1805
isl_surf_init_s(const struct isl_device *dev,
1806
struct isl_surf *surf,
1807
const struct isl_surf_init_info *restrict info)
1809
/* Some sanity checks */
1810
assert(!(info->usage & ISL_SURF_USAGE_CPB_BIT) ||
1811
dev->info->has_coarse_pixel_primitive_and_cb);
1813
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1815
const struct isl_extent4d logical_level0_px = {
1819
.a = info->array_len,
1822
enum isl_tiling tiling;
1823
if (!isl_surf_choose_tiling(dev, info, &tiling))
1826
const enum isl_dim_layout dim_layout =
1827
isl_surf_choose_dim_layout(dev, info->dim, tiling, info->usage);
1829
enum isl_msaa_layout msaa_layout;
1830
if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout))
1833
struct isl_tile_info tile_info;
1834
isl_tiling_get_info(tiling, info->dim, msaa_layout, fmtl->bpb,
1835
info->samples, &tile_info);
1837
struct isl_extent3d image_align_el;
1838
isl_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout,
1841
struct isl_extent3d image_align_sa =
1842
isl_extent3d_el_to_sa(info->format, image_align_el);
1844
struct isl_extent4d phys_level0_sa;
1845
isl_calc_phys_level0_extent_sa(dev, info, dim_layout, tiling, msaa_layout,
1848
enum isl_array_pitch_span array_pitch_span =
1849
isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa);
1851
uint32_t array_pitch_el_rows;
1852
struct isl_extent4d phys_total_el;
1853
isl_calc_phys_total_extent_el(dev, info, &tile_info,
1854
dim_layout, msaa_layout,
1855
&image_align_sa, &phys_level0_sa,
1856
array_pitch_span, &array_pitch_el_rows,
1859
uint32_t row_pitch_B;
1860
if (!isl_calc_row_pitch(dev, info, &tile_info, dim_layout,
1861
&phys_total_el, &row_pitch_B))
1864
uint32_t base_alignment_B;
1866
if (tiling == ISL_TILING_LINEAR) {
1867
/* LINEAR tiling has no concept of intra-tile arrays */
1868
assert(phys_total_el.d == 1 && phys_total_el.a == 1);
1870
size_B = (uint64_t) row_pitch_B * phys_total_el.h;
1872
/* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1874
* "The Base Address for linear render target surfaces and surfaces
1875
* accessed with the typed surface read/write data port messages must
1876
* be element-size aligned, for non-YUV surface formats, or a
1877
* multiple of 2 element-sizes for YUV surface formats. Other linear
1878
* surfaces have no alignment requirements (byte alignment is
1881
base_alignment_B = MAX(1, info->min_alignment_B);
1882
if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
1883
if (isl_format_is_yuv(info->format)) {
1884
base_alignment_B = MAX(base_alignment_B, fmtl->bpb / 4);
1886
base_alignment_B = MAX(base_alignment_B, fmtl->bpb / 8);
1889
base_alignment_B = isl_round_up_to_power_of_two(base_alignment_B);
1891
/* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
1893
* "For Linear memory, this field specifies the stride in chunks of
1894
* 64 bytes (1 cache line)."
1896
if (isl_surf_usage_is_display(info->usage))
1897
base_alignment_B = MAX(base_alignment_B, 64);
1899
/* Pitches must make sense with the tiling */
1900
assert(row_pitch_B % tile_info.phys_extent_B.width == 0);
1902
uint32_t array_slices, array_pitch_tl_rows;
1903
if (phys_total_el.d > 1) {
1904
assert(phys_total_el.a == 1);
1905
array_pitch_tl_rows = isl_assert_div(array_pitch_el_rows,
1906
tile_info.logical_extent_el.h);
1907
array_slices = isl_align_div(phys_total_el.d,
1908
tile_info.logical_extent_el.d);
1909
} else if (phys_total_el.a > 1) {
1910
assert(phys_total_el.d == 1);
1911
array_pitch_tl_rows = isl_assert_div(array_pitch_el_rows,
1912
tile_info.logical_extent_el.h);
1913
array_slices = isl_align_div(phys_total_el.a,
1914
tile_info.logical_extent_el.a);
1916
assert(phys_total_el.d == 1 && phys_total_el.a == 1);
1917
array_pitch_tl_rows = 0;
1921
const uint32_t total_h_tl =
1922
(array_slices - 1) * array_pitch_tl_rows +
1923
isl_align_div(phys_total_el.h, tile_info.logical_extent_el.height);
1925
size_B = (uint64_t) total_h_tl * tile_info.phys_extent_B.height * row_pitch_B;
1927
const uint32_t tile_size_B = tile_info.phys_extent_B.width *
1928
tile_info.phys_extent_B.height;
1929
assert(isl_is_pow2(info->min_alignment_B) && isl_is_pow2(tile_size_B));
1930
base_alignment_B = MAX(info->min_alignment_B, tile_size_B);
1932
/* The diagram in the Bspec section Memory Compression - Gfx12, shows
1933
* that the CCS is indexed in 256B chunks. However, the
1934
* PLANE_AUX_DIST::Auxiliary Surface Distance field is in units of 4K
1935
* pages. We currently don't assign the usage field like we do for main
1936
* surfaces, so just use 4K for now.
1938
if (tiling == ISL_TILING_GFX12_CCS)
1939
base_alignment_B = MAX(base_alignment_B, 4096);
1941
/* Platforms using an aux map require that images be 64K-aligned if
1942
* they're going to used with CCS. This is because the Aux translation
1943
* table maps main surface addresses to aux addresses at a 64K (in the
1944
* main surface) granularity. Because we don't know for sure in ISL if
1945
* a surface will use CCS, we have to guess based on the DISABLE_AUX
1946
* usage bit. The one thing we do know is that we haven't enable CCS on
1947
* linear images yet so we can avoid the extra alignment there.
1949
if (dev->info->has_aux_map &&
1950
!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
1951
base_alignment_B = MAX(base_alignment_B, 64 * 1024);
1955
if (ISL_GFX_VER(dev) < 9) {
1956
/* From the Broadwell PRM Vol 5, Surface Layout:
1958
* "In addition to restrictions on maximum height, width, and depth,
1959
* surfaces are also restricted to a maximum size in bytes. This
1960
* maximum is 2 GB for all products and all surface types."
1962
* This comment is applicable to all Pre-gfx9 platforms.
1964
if (size_B > (uint64_t) 1 << 31)
1966
} else if (ISL_GFX_VER(dev) < 11) {
1967
/* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1968
* "In addition to restrictions on maximum height, width, and depth,
1969
* surfaces are also restricted to a maximum size of 2^38 bytes.
1970
* All pixels within the surface must be contained within 2^38 bytes
1971
* of the base address."
1973
if (size_B > (uint64_t) 1 << 38)
1976
/* gfx11+ platforms raised this limit to 2^44 bytes. */
1977
if (size_B > (uint64_t) 1 << 44)
1981
*surf = (struct isl_surf) {
1983
.dim_layout = dim_layout,
1984
.msaa_layout = msaa_layout,
1986
.format = info->format,
1988
.levels = info->levels,
1989
.samples = info->samples,
1991
.image_alignment_el = image_align_el,
1992
.logical_level0_px = logical_level0_px,
1993
.phys_level0_sa = phys_level0_sa,
1996
.alignment_B = base_alignment_B,
1997
.row_pitch_B = row_pitch_B,
1998
.array_pitch_el_rows = array_pitch_el_rows,
1999
.array_pitch_span = array_pitch_span,
2001
.usage = info->usage,
2008
isl_surf_get_tile_info(const struct isl_surf *surf,
2009
struct isl_tile_info *tile_info)
2011
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2012
isl_tiling_get_info(surf->tiling, surf->dim, surf->msaa_layout, fmtl->bpb,
2013
surf->samples, tile_info);
2017
isl_surf_get_hiz_surf(const struct isl_device *dev,
2018
const struct isl_surf *surf,
2019
struct isl_surf *hiz_surf)
2021
/* HiZ support does not exist prior to Gfx5 */
2022
if (ISL_GFX_VER(dev) < 5)
2025
if (!isl_surf_usage_is_depth(surf->usage))
2028
/* From the Sandy Bridge PRM, Vol 2 Part 1,
2029
* 3DSTATE_DEPTH_BUFFER::Hierarchical Depth Buffer Enable,
2031
* If this field is enabled, the Surface Format of the depth buffer
2032
* cannot be D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT. Use of stencil
2033
* requires the separate stencil buffer.
2035
* On SNB+, HiZ can't be used with combined depth-stencil buffers.
2037
if (isl_surf_usage_is_stencil(surf->usage))
2040
/* Multisampled depth is always interleaved */
2041
assert(surf->msaa_layout == ISL_MSAA_LAYOUT_NONE ||
2042
surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
2044
/* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
2046
* "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
2047
* Target View Extent, and Depth Coordinate Offset X/Y of the
2048
* hierarchical depth buffer are inherited from the depth buffer. The
2049
* height and width of the hierarchical depth buffer that must be
2050
* allocated are computed by the following formulas, where HZ is the
2051
* hierarchical depth buffer and Z is the depth buffer. The Z_Height,
2052
* Z_Width, and Z_Depth values given in these formulas are those present
2053
* in 3DSTATE_DEPTH_BUFFER incremented by one.
2055
* "The value of Z_Height and Z_Width must each be multiplied by 2 before
2056
* being applied to the table below if Number of Multisamples is set to
2057
* NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
2058
* Z_Width must be multiplied by 4 before being applied to the table
2059
* below if Number of Multisamples is set to NUMSAMPLES_8."
2061
* In the Sky Lake PRM, the second paragraph is gone. This means that,
2062
* from Sandy Bridge through Broadwell, HiZ compresses samples in the
2063
* primary depth surface. On Sky Lake and onward, HiZ compresses pixels.
2065
* There are a number of different ways that this discrepency could be
2066
* handled. The way we have chosen is to simply make MSAA HiZ have the
2067
* same number of samples as the parent surface pre-Sky Lake and always be
2068
* single-sampled on Sky Lake and above. Since the block sizes of
2069
* compressed formats are given in samples, this neatly handles everything
2070
* without the need for additional HiZ formats with different block sizes
2073
const unsigned samples = ISL_GFX_VER(dev) >= 9 ? 1 : surf->samples;
2075
const enum isl_format format =
2076
ISL_GFX_VERX10(dev) >= 125 ? ISL_FORMAT_GFX125_HIZ : ISL_FORMAT_HIZ;
2078
return isl_surf_init(dev, hiz_surf,
2081
.width = surf->logical_level0_px.width,
2082
.height = surf->logical_level0_px.height,
2083
.depth = surf->logical_level0_px.depth,
2084
.levels = surf->levels,
2085
.array_len = surf->logical_level0_px.array_len,
2087
.usage = ISL_SURF_USAGE_HIZ_BIT,
2088
.tiling_flags = ISL_TILING_HIZ_BIT);
2092
isl_surf_get_mcs_surf(const struct isl_device *dev,
2093
const struct isl_surf *surf,
2094
struct isl_surf *mcs_surf)
2096
/* It must be multisampled with an array layout */
2097
if (surf->msaa_layout != ISL_MSAA_LAYOUT_ARRAY)
2100
/* We are seeing failures with mcs on dg2, so disable it for now. */
2101
if (intel_device_info_is_dg2(dev->info))
2104
/* The following are true of all multisampled surfaces */
2105
assert(surf->samples > 1);
2106
assert(surf->dim == ISL_SURF_DIM_2D);
2107
assert(surf->levels == 1);
2108
assert(surf->logical_level0_px.depth == 1);
2109
assert(isl_format_supports_multisampling(dev->info, surf->format));
2111
enum isl_format mcs_format;
2112
switch (surf->samples) {
2113
case 2: mcs_format = ISL_FORMAT_MCS_2X; break;
2114
case 4: mcs_format = ISL_FORMAT_MCS_4X; break;
2115
case 8: mcs_format = ISL_FORMAT_MCS_8X; break;
2116
case 16: mcs_format = ISL_FORMAT_MCS_16X; break;
2118
unreachable("Invalid sample count");
2121
return isl_surf_init(dev, mcs_surf,
2122
.dim = ISL_SURF_DIM_2D,
2123
.format = mcs_format,
2124
.width = surf->logical_level0_px.width,
2125
.height = surf->logical_level0_px.height,
2128
.array_len = surf->logical_level0_px.array_len,
2129
.samples = 1, /* MCS surfaces are really single-sampled */
2130
.usage = ISL_SURF_USAGE_MCS_BIT,
2131
.tiling_flags = ISL_TILING_ANY_MASK);
2135
isl_surf_supports_ccs(const struct isl_device *dev,
2136
const struct isl_surf *surf,
2137
const struct isl_surf *hiz_or_mcs_surf)
2139
if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
2142
if (!isl_format_supports_ccs_d(dev->info, surf->format) &&
2143
!isl_format_supports_ccs_e(dev->info, surf->format))
2146
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
2147
* Target(s)", beneath the "Fast Color Clear" bullet (p326):
2149
* - Support is limited to tiled render targets.
2151
* From the Skylake documentation, it is made clear that X-tiling is no
2154
* - MCS and Lossless compression is supported for
2155
* TiledY/TileYs/TileYf non-MSRTs only.
2157
* From the BSpec (44930) for Gfx12:
2159
* Linear CCS is only allowed for Untyped Buffers but only via HDC
2160
* Data-Port messages.
2162
* We never use untyped messages on surfaces created by ISL on Gfx9+ so
2163
* this means linear is out on Gfx12+ as well.
2165
if (surf->tiling == ISL_TILING_LINEAR)
2168
/* TODO: Disable for now, as we're not sure about the meaning of
2169
* 3DSTATE_CPSIZE_CONTROL_BUFFER::CPCBCompressionEnable
2171
if (isl_surf_usage_is_cpb(surf->usage))
2174
if (ISL_GFX_VER(dev) >= 12) {
2175
if (isl_surf_usage_is_stencil(surf->usage)) {
2176
/* HiZ and MCS aren't allowed with stencil */
2177
assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
2179
/* Multi-sampled stencil cannot have CCS */
2180
if (surf->samples > 1)
2182
} else if (isl_surf_usage_is_depth(surf->usage)) {
2183
const struct isl_surf *hiz_surf = hiz_or_mcs_surf;
2185
/* With depth surfaces, HIZ is required for CCS. */
2186
if (hiz_surf == NULL || hiz_surf->size_B == 0)
2189
assert(hiz_surf->usage & ISL_SURF_USAGE_HIZ_BIT);
2190
assert(hiz_surf->tiling == ISL_TILING_HIZ);
2191
assert(isl_format_is_hiz(hiz_surf->format));
2192
} else if (surf->samples > 1) {
2193
const struct isl_surf *mcs_surf = hiz_or_mcs_surf;
2195
/* With multisampled color, CCS requires MCS */
2196
if (mcs_surf == NULL || mcs_surf->size_B == 0)
2199
assert(mcs_surf->usage & ISL_SURF_USAGE_MCS_BIT);
2200
assert(isl_format_is_mcs(mcs_surf->format));
2202
/* Single-sampled color can't have MCS or HiZ */
2203
assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
2206
/* On Gfx12, all CCS-compressed surface pitches must be multiples of
2209
if (surf->row_pitch_B % 512 != 0)
2212
/* According to Wa_1406738321, 3D textures need a blit to a new
2213
* surface in order to perform a resolve. For now, just disable CCS.
2215
if (surf->dim == ISL_SURF_DIM_3D) {
2216
isl_finishme("%s:%s: CCS for 3D textures is disabled, but a workaround"
2217
" is available.", __FILE__, __func__);
2223
* TODO: implement following workaround currently covered by the
2224
* restriction above. If following conditions are met:
2226
* - RENDER_SURFACE_STATE.Surface Type == 3D
2227
* - RENDER_SURFACE_STATE.Auxiliary Surface Mode != AUX_NONE
2228
* - RENDER_SURFACE_STATE.Tiled ResourceMode is TYF or TYS
2230
* Set the value of RENDER_SURFACE_STATE.Mip Tail Start LOD to a mip
2231
* that larger than those present in the surface (i.e. 15)
2234
/* TODO: Handle the other tiling formats */
2235
if (surf->tiling != ISL_TILING_Y0 && surf->tiling != ISL_TILING_4 &&
2236
surf->tiling != ISL_TILING_64)
2239
/* TODO: Handle single-sampled Tile64. */
2240
if (surf->samples == 1 && surf->tiling == ISL_TILING_64)
2243
/* ISL_GFX_VER(dev) < 12 */
2244
if (surf->samples > 1)
2247
/* CCS is only for color images on Gfx7-11 */
2248
if (isl_surf_usage_is_depth_or_stencil(surf->usage))
2251
/* We're single-sampled color so having HiZ or MCS makes no sense */
2252
assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
2254
/* The PRM doesn't say this explicitly, but fast-clears don't appear to
2255
* work for 3D textures until gfx9 where the layout of 3D textures
2256
* changes to match 2D array textures.
2258
if (ISL_GFX_VER(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D)
2261
/* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
2262
* Non-MultiSampler Render Target Restrictions):
2264
* "Support is for non-mip-mapped and non-array surface types only."
2266
* This restriction is lifted on gfx8+. Technically, it may be possible
2267
* to create a CCS for an arrayed or mipmapped image and only enable
2268
* CCS_D when rendering to the base slice. However, there is no
2269
* documentation tell us what the hardware would do in that case or what
2270
* it does if you walk off the bases slice. (Does it ignore CCS or does
2271
* it start scribbling over random memory?) We play it safe and just
2272
* follow the docs and don't allow CCS_D for arrayed or mip-mapped
2275
if (ISL_GFX_VER(dev) <= 7 &&
2276
(surf->levels > 1 || surf->logical_level0_px.array_len > 1))
2279
/* From the Skylake documentation, it is made clear that X-tiling is no
2282
* - MCS and Lossless compression is supported for
2283
* TiledY/TileYs/TileYf non-MSRTs only.
2285
if (ISL_GFX_VER(dev) >= 9 && !isl_tiling_is_any_y(surf->tiling))
2293
isl_surf_get_ccs_surf(const struct isl_device *dev,
2294
const struct isl_surf *surf,
2295
const struct isl_surf *hiz_or_mcs_surf,
2296
struct isl_surf *ccs_surf,
2297
uint32_t row_pitch_B)
2299
if (!isl_surf_supports_ccs(dev, surf, hiz_or_mcs_surf))
2302
if (ISL_GFX_VER(dev) >= 12) {
2303
enum isl_format ccs_format;
2304
switch (isl_format_get_layout(surf->format)->bpb) {
2305
case 8: ccs_format = ISL_FORMAT_GFX12_CCS_8BPP_Y0; break;
2306
case 16: ccs_format = ISL_FORMAT_GFX12_CCS_16BPP_Y0; break;
2307
case 32: ccs_format = ISL_FORMAT_GFX12_CCS_32BPP_Y0; break;
2308
case 64: ccs_format = ISL_FORMAT_GFX12_CCS_64BPP_Y0; break;
2309
case 128: ccs_format = ISL_FORMAT_GFX12_CCS_128BPP_Y0; break;
2314
/* On Gfx12, the CCS is a scaled-down version of the main surface. We
2315
* model this as the CCS compressing a 2D-view of the entire surface.
2318
isl_surf_init(dev, ccs_surf,
2319
.dim = ISL_SURF_DIM_2D,
2320
.format = ccs_format,
2321
.width = isl_surf_get_row_pitch_el(surf),
2322
.height = surf->size_B / surf->row_pitch_B,
2327
.row_pitch_B = row_pitch_B,
2328
.usage = ISL_SURF_USAGE_CCS_BIT,
2329
.tiling_flags = ISL_TILING_GFX12_CCS_BIT);
2330
assert(!ok || ccs_surf->size_B == surf->size_B / 256);
2333
enum isl_format ccs_format;
2334
if (ISL_GFX_VER(dev) >= 9) {
2335
switch (isl_format_get_layout(surf->format)->bpb) {
2336
case 32: ccs_format = ISL_FORMAT_GFX9_CCS_32BPP; break;
2337
case 64: ccs_format = ISL_FORMAT_GFX9_CCS_64BPP; break;
2338
case 128: ccs_format = ISL_FORMAT_GFX9_CCS_128BPP; break;
2339
default: unreachable("Unsupported CCS format");
2342
} else if (surf->tiling == ISL_TILING_Y0) {
2343
switch (isl_format_get_layout(surf->format)->bpb) {
2344
case 32: ccs_format = ISL_FORMAT_GFX7_CCS_32BPP_Y; break;
2345
case 64: ccs_format = ISL_FORMAT_GFX7_CCS_64BPP_Y; break;
2346
case 128: ccs_format = ISL_FORMAT_GFX7_CCS_128BPP_Y; break;
2347
default: unreachable("Unsupported CCS format");
2349
} else if (surf->tiling == ISL_TILING_X) {
2350
switch (isl_format_get_layout(surf->format)->bpb) {
2351
case 32: ccs_format = ISL_FORMAT_GFX7_CCS_32BPP_X; break;
2352
case 64: ccs_format = ISL_FORMAT_GFX7_CCS_64BPP_X; break;
2353
case 128: ccs_format = ISL_FORMAT_GFX7_CCS_128BPP_X; break;
2354
default: unreachable("Unsupported CCS format");
2357
unreachable("Invalid tiling format");
2360
return isl_surf_init(dev, ccs_surf,
2362
.format = ccs_format,
2363
.width = surf->logical_level0_px.width,
2364
.height = surf->logical_level0_px.height,
2365
.depth = surf->logical_level0_px.depth,
2366
.levels = surf->levels,
2367
.array_len = surf->logical_level0_px.array_len,
2369
.row_pitch_B = row_pitch_B,
2370
.usage = ISL_SURF_USAGE_CCS_BIT,
2371
.tiling_flags = ISL_TILING_CCS_BIT);
2375
#define isl_genX_call(dev, func, ...) \
2376
switch (ISL_GFX_VERX10(dev)) { \
2378
isl_gfx4_##func(__VA_ARGS__); \
2381
/* G45 surface state is the same as gfx5 */ \
2383
isl_gfx5_##func(__VA_ARGS__); \
2386
isl_gfx6_##func(__VA_ARGS__); \
2389
isl_gfx7_##func(__VA_ARGS__); \
2392
isl_gfx75_##func(__VA_ARGS__); \
2395
isl_gfx8_##func(__VA_ARGS__); \
2398
isl_gfx9_##func(__VA_ARGS__); \
2401
isl_gfx11_##func(__VA_ARGS__); \
2404
isl_gfx12_##func(__VA_ARGS__); \
2407
isl_gfx125_##func(__VA_ARGS__); \
2410
assert(!"Unknown hardware generation"); \
2414
isl_surf_fill_state_s(const struct isl_device *dev, void *state,
2415
const struct isl_surf_fill_state_info *restrict info)
2418
isl_surf_usage_flags_t _base_usage =
2419
info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
2420
ISL_SURF_USAGE_TEXTURE_BIT |
2421
ISL_SURF_USAGE_STORAGE_BIT);
2422
/* They may only specify one of the above bits at a time */
2423
assert(__builtin_popcount(_base_usage) == 1);
2424
/* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
2425
assert((info->view->usage & ~ISL_SURF_USAGE_CUBE_BIT) == _base_usage);
2428
if (info->surf->dim == ISL_SURF_DIM_3D) {
2429
assert(info->view->base_array_layer + info->view->array_len <=
2430
info->surf->logical_level0_px.depth);
2432
assert(info->view->base_array_layer + info->view->array_len <=
2433
info->surf->logical_level0_px.array_len);
2436
isl_genX_call(dev, surf_fill_state_s, dev, state, info);
2440
isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
2441
const struct isl_buffer_fill_state_info *restrict info)
2443
isl_genX_call(dev, buffer_fill_state_s, dev, state, info);
2447
isl_null_fill_state_s(const struct isl_device *dev, void *state,
2448
const struct isl_null_fill_state_info *restrict info)
2450
isl_genX_call(dev, null_fill_state, dev, state, info);
2454
isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
2455
const struct isl_depth_stencil_hiz_emit_info *restrict info)
2457
if (info->depth_surf && info->stencil_surf) {
2458
if (!dev->info->has_hiz_and_separate_stencil) {
2459
assert(info->depth_surf == info->stencil_surf);
2460
assert(info->depth_address == info->stencil_address);
2462
assert(info->depth_surf->dim == info->stencil_surf->dim);
2465
if (info->depth_surf) {
2466
assert((info->depth_surf->usage & ISL_SURF_USAGE_DEPTH_BIT));
2467
if (info->depth_surf->dim == ISL_SURF_DIM_3D) {
2468
assert(info->view->base_array_layer + info->view->array_len <=
2469
info->depth_surf->logical_level0_px.depth);
2471
assert(info->view->base_array_layer + info->view->array_len <=
2472
info->depth_surf->logical_level0_px.array_len);
2476
if (info->stencil_surf) {
2477
assert((info->stencil_surf->usage & ISL_SURF_USAGE_STENCIL_BIT));
2478
if (info->stencil_surf->dim == ISL_SURF_DIM_3D) {
2479
assert(info->view->base_array_layer + info->view->array_len <=
2480
info->stencil_surf->logical_level0_px.depth);
2482
assert(info->view->base_array_layer + info->view->array_len <=
2483
info->stencil_surf->logical_level0_px.array_len);
2487
isl_genX_call(dev, emit_depth_stencil_hiz_s, dev, batch, info);
2491
isl_emit_cpb_control_s(const struct isl_device *dev, void *batch,
2492
const struct isl_cpb_emit_info *restrict info)
2495
assert((info->surf->usage & ISL_SURF_USAGE_CPB_BIT));
2496
assert(info->surf->dim != ISL_SURF_DIM_3D);
2497
assert(info->surf->tiling == ISL_TILING_4 ||
2498
info->surf->tiling == ISL_TILING_64);
2499
assert(info->surf->format == ISL_FORMAT_R8_UINT);
2502
isl_genX_call(dev, emit_cpb_control_s, dev, batch, info);
2506
* A variant of isl_surf_get_image_offset_sa() specific to
2507
* ISL_DIM_LAYOUT_GFX4_2D.
2510
get_image_offset_sa_gfx4_2d(const struct isl_surf *surf,
2511
uint32_t level, uint32_t logical_array_layer,
2512
uint32_t *x_offset_sa,
2513
uint32_t *y_offset_sa)
2515
assert(level < surf->levels);
2516
if (surf->dim == ISL_SURF_DIM_3D)
2517
assert(logical_array_layer < surf->logical_level0_px.depth);
2519
assert(logical_array_layer < surf->logical_level0_px.array_len);
2521
const struct isl_extent3d image_align_sa =
2522
isl_surf_get_image_alignment_sa(surf);
2524
const uint32_t W0 = surf->phys_level0_sa.width;
2525
const uint32_t H0 = surf->phys_level0_sa.height;
2527
const uint32_t phys_layer = logical_array_layer *
2528
(surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? surf->samples : 1);
2531
uint32_t y = phys_layer * isl_surf_get_array_pitch_sa_rows(surf);
2533
for (uint32_t l = 0; l < level; ++l) {
2535
uint32_t W = isl_minify(W0, l);
2536
x += isl_align_npot(W, image_align_sa.w);
2538
uint32_t H = isl_minify(H0, l);
2539
y += isl_align_npot(H, image_align_sa.h);
2548
* A variant of isl_surf_get_image_offset_sa() specific to
2549
* ISL_DIM_LAYOUT_GFX4_3D.
2552
get_image_offset_sa_gfx4_3d(const struct isl_surf *surf,
2553
uint32_t level, uint32_t logical_z_offset_px,
2554
uint32_t *x_offset_sa,
2555
uint32_t *y_offset_sa)
2557
assert(level < surf->levels);
2558
if (surf->dim == ISL_SURF_DIM_3D) {
2559
assert(surf->phys_level0_sa.array_len == 1);
2560
assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
2562
assert(surf->dim == ISL_SURF_DIM_2D);
2563
assert(surf->usage & ISL_SURF_USAGE_CUBE_BIT);
2564
assert(surf->phys_level0_sa.array_len == 6);
2565
assert(logical_z_offset_px < surf->phys_level0_sa.array_len);
2568
const struct isl_extent3d image_align_sa =
2569
isl_surf_get_image_alignment_sa(surf);
2571
const uint32_t W0 = surf->phys_level0_sa.width;
2572
const uint32_t H0 = surf->phys_level0_sa.height;
2573
const uint32_t D0 = surf->phys_level0_sa.depth;
2574
const uint32_t AL = surf->phys_level0_sa.array_len;
2579
for (uint32_t l = 0; l < level; ++l) {
2580
const uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa.h);
2581
const uint32_t level_d =
2582
isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : AL,
2584
const uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
2586
y += level_h * max_layers_vert;
2589
const uint32_t level_w = isl_align_npot(isl_minify(W0, level), image_align_sa.w);
2590
const uint32_t level_h = isl_align_npot(isl_minify(H0, level), image_align_sa.h);
2591
const uint32_t level_d =
2592
isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, level) : AL,
2595
const uint32_t max_layers_horiz = MIN(level_d, 1u << level);
2597
x += level_w * (logical_z_offset_px % max_layers_horiz);
2598
y += level_h * (logical_z_offset_px / max_layers_horiz);
2605
get_image_offset_sa_gfx6_stencil_hiz(const struct isl_surf *surf,
2607
uint32_t logical_array_layer,
2608
uint32_t *x_offset_sa,
2609
uint32_t *y_offset_sa)
2611
assert(level < surf->levels);
2612
assert(surf->logical_level0_px.depth == 1);
2613
assert(logical_array_layer < surf->logical_level0_px.array_len);
2615
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2617
const struct isl_extent3d image_align_sa =
2618
isl_surf_get_image_alignment_sa(surf);
2620
struct isl_tile_info tile_info;
2621
isl_surf_get_tile_info(surf, &tile_info);
2622
const struct isl_extent2d tile_extent_sa = {
2623
.w = tile_info.logical_extent_el.w * fmtl->bw,
2624
.h = tile_info.logical_extent_el.h * fmtl->bh,
2626
/* Tile size is a multiple of image alignment */
2627
assert(tile_extent_sa.w % image_align_sa.w == 0);
2628
assert(tile_extent_sa.h % image_align_sa.h == 0);
2630
const uint32_t W0 = surf->phys_level0_sa.w;
2631
const uint32_t H0 = surf->phys_level0_sa.h;
2633
/* Each image has the same height as LOD0 because the hardware thinks
2634
* everything is LOD0
2636
const uint32_t H = isl_align(H0, image_align_sa.h);
2638
/* Quick sanity check for consistency */
2639
if (surf->phys_level0_sa.array_len > 1)
2640
assert(surf->array_pitch_el_rows == isl_assert_div(H, fmtl->bh));
2642
uint32_t x = 0, y = 0;
2643
for (uint32_t l = 0; l < level; ++l) {
2644
const uint32_t W = isl_minify(W0, l);
2646
const uint32_t w = isl_align(W, tile_extent_sa.w);
2647
const uint32_t h = isl_align(H * surf->phys_level0_sa.a,
2657
y += H * logical_array_layer;
2664
* A variant of isl_surf_get_image_offset_sa() specific to
2665
* ISL_DIM_LAYOUT_GFX9_1D.
2668
get_image_offset_sa_gfx9_1d(const struct isl_surf *surf,
2669
uint32_t level, uint32_t layer,
2670
uint32_t *x_offset_sa,
2671
uint32_t *y_offset_sa)
2673
assert(level < surf->levels);
2674
assert(layer < surf->phys_level0_sa.array_len);
2675
assert(surf->phys_level0_sa.height == 1);
2676
assert(surf->phys_level0_sa.depth == 1);
2677
assert(surf->samples == 1);
2679
const uint32_t W0 = surf->phys_level0_sa.width;
2680
const struct isl_extent3d image_align_sa =
2681
isl_surf_get_image_alignment_sa(surf);
2685
for (uint32_t l = 0; l < level; ++l) {
2686
uint32_t W = isl_minify(W0, l);
2687
uint32_t w = isl_align_npot(W, image_align_sa.w);
2693
*y_offset_sa = layer * isl_surf_get_array_pitch_sa_rows(surf);
2697
* Calculate the offset, in units of surface samples, to a subimage in the
2700
* @invariant level < surface levels
2701
* @invariant logical_array_layer < logical array length of surface
2702
* @invariant logical_z_offset_px < logical depth of surface at level
2705
isl_surf_get_image_offset_sa(const struct isl_surf *surf,
2707
uint32_t logical_array_layer,
2708
uint32_t logical_z_offset_px,
2709
uint32_t *x_offset_sa,
2710
uint32_t *y_offset_sa,
2711
uint32_t *z_offset_sa,
2712
uint32_t *array_offset)
2714
assert(level < surf->levels);
2715
assert(logical_array_layer < surf->logical_level0_px.array_len);
2716
assert(logical_z_offset_px
2717
< isl_minify(surf->logical_level0_px.depth, level));
2719
switch (surf->dim_layout) {
2720
case ISL_DIM_LAYOUT_GFX9_1D:
2721
get_image_offset_sa_gfx9_1d(surf, level, logical_array_layer,
2722
x_offset_sa, y_offset_sa);
2726
case ISL_DIM_LAYOUT_GFX4_2D:
2727
get_image_offset_sa_gfx4_2d(surf, level, logical_array_layer
2728
+ logical_z_offset_px,
2729
x_offset_sa, y_offset_sa);
2733
case ISL_DIM_LAYOUT_GFX4_3D:
2734
get_image_offset_sa_gfx4_3d(surf, level, logical_array_layer +
2735
logical_z_offset_px,
2736
x_offset_sa, y_offset_sa);
2740
case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
2741
get_image_offset_sa_gfx6_stencil_hiz(surf, level, logical_array_layer +
2742
logical_z_offset_px,
2743
x_offset_sa, y_offset_sa);
2749
unreachable("not reached");
2754
isl_surf_get_image_offset_el(const struct isl_surf *surf,
2756
uint32_t logical_array_layer,
2757
uint32_t logical_z_offset_px,
2758
uint32_t *x_offset_el,
2759
uint32_t *y_offset_el,
2760
uint32_t *z_offset_el,
2761
uint32_t *array_offset)
2763
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2765
assert(level < surf->levels);
2766
assert(logical_array_layer < surf->logical_level0_px.array_len);
2767
assert(logical_z_offset_px
2768
< isl_minify(surf->logical_level0_px.depth, level));
2770
uint32_t x_offset_sa, y_offset_sa, z_offset_sa;
2771
isl_surf_get_image_offset_sa(surf, level,
2772
logical_array_layer,
2773
logical_z_offset_px,
2779
*x_offset_el = x_offset_sa / fmtl->bw;
2780
*y_offset_el = y_offset_sa / fmtl->bh;
2781
*z_offset_el = z_offset_sa / fmtl->bd;
2785
isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2787
uint32_t logical_array_layer,
2788
uint32_t logical_z_offset_px,
2790
uint32_t *x_offset_sa,
2791
uint32_t *y_offset_sa)
2793
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2795
uint32_t x_offset_el, y_offset_el;
2796
isl_surf_get_image_offset_B_tile_el(surf, level,
2797
logical_array_layer,
2798
logical_z_offset_px,
2804
*x_offset_sa = x_offset_el * fmtl->bw;
2806
assert(x_offset_el == 0);
2810
*y_offset_sa = y_offset_el * fmtl->bh;
2812
assert(y_offset_el == 0);
2817
isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
2819
uint32_t logical_array_layer,
2820
uint32_t logical_z_offset_px,
2822
uint32_t *x_offset_el,
2823
uint32_t *y_offset_el)
2825
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2827
uint32_t total_x_offset_el, total_y_offset_el;
2828
uint32_t total_z_offset_el, total_array_offset;
2829
isl_surf_get_image_offset_el(surf, level, logical_array_layer,
2830
logical_z_offset_px,
2834
&total_array_offset);
2836
uint32_t z_offset_el, array_offset;
2837
isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
2838
surf->msaa_layout, fmtl->bpb,
2841
surf->array_pitch_el_rows,
2851
assert(z_offset_el == 0);
2852
assert(array_offset == 0);
2856
isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
2858
uint32_t logical_array_layer,
2859
uint32_t logical_z_offset_px,
2860
uint64_t *start_tile_B,
2861
uint64_t *end_tile_B)
2863
uint32_t start_x_offset_el, start_y_offset_el;
2864
uint32_t start_z_offset_el, start_array_slice;
2865
isl_surf_get_image_offset_el(surf, level, logical_array_layer,
2866
logical_z_offset_px,
2870
&start_array_slice);
2872
/* Compute the size of the subimage in surface elements */
2873
const uint32_t subimage_w_sa = isl_minify(surf->phys_level0_sa.w, level);
2874
const uint32_t subimage_h_sa = isl_minify(surf->phys_level0_sa.h, level);
2875
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2876
const uint32_t subimage_w_el = isl_align_div_npot(subimage_w_sa, fmtl->bw);
2877
const uint32_t subimage_h_el = isl_align_div_npot(subimage_h_sa, fmtl->bh);
2879
/* Find the last pixel */
2880
uint32_t end_x_offset_el = start_x_offset_el + subimage_w_el - 1;
2881
uint32_t end_y_offset_el = start_y_offset_el + subimage_h_el - 1;
2883
/* We only consider one Z or array slice */
2884
const uint32_t end_z_offset_el = start_z_offset_el;
2885
const uint32_t end_array_slice = start_array_slice;
2887
UNUSED uint32_t x_offset_el, y_offset_el, z_offset_el, array_slice;
2888
isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
2889
surf->msaa_layout, fmtl->bpb,
2892
surf->array_pitch_el_rows,
2903
isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
2904
surf->msaa_layout, fmtl->bpb,
2907
surf->array_pitch_el_rows,
2918
/* We want the range we return to be exclusive but the tile containing the
2919
* last pixel (what we just calculated) is inclusive. Add one.
2923
assert(*end_tile_B <= surf->size_B);
2927
isl_surf_get_image_surf(const struct isl_device *dev,
2928
const struct isl_surf *surf,
2930
uint32_t logical_array_layer,
2931
uint32_t logical_z_offset_px,
2932
struct isl_surf *image_surf,
2934
uint32_t *x_offset_sa,
2935
uint32_t *y_offset_sa)
2937
isl_surf_get_image_offset_B_tile_sa(surf,
2939
logical_array_layer,
2940
logical_z_offset_px,
2945
/* Even for cube maps there will be only single face, therefore drop the
2946
* corresponding flag if present.
2948
const isl_surf_usage_flags_t usage =
2949
surf->usage & (~ISL_SURF_USAGE_CUBE_BIT);
2952
ok = isl_surf_init(dev, image_surf,
2953
.dim = ISL_SURF_DIM_2D,
2954
.format = surf->format,
2955
.width = isl_minify(surf->logical_level0_px.w, level),
2956
.height = isl_minify(surf->logical_level0_px.h, level),
2960
.samples = surf->samples,
2961
.row_pitch_B = surf->row_pitch_B,
2963
.tiling_flags = (1 << surf->tiling));
2968
isl_surf_get_uncompressed_surf(const struct isl_device *dev,
2969
const struct isl_surf *surf,
2970
const struct isl_view *view,
2971
struct isl_surf *ucompr_surf,
2972
struct isl_view *ucompr_view,
2974
uint32_t *x_offset_el,
2975
uint32_t *y_offset_el)
2977
const struct isl_format_layout *fmtl =
2978
isl_format_get_layout(surf->format);
2979
const enum isl_format view_format = view->format;
2981
assert(fmtl->bw > 1 || fmtl->bh > 1 || fmtl->bd > 1);
2982
assert(isl_format_is_compressed(surf->format));
2983
assert(!isl_format_is_compressed(view->format));
2984
assert(isl_format_get_layout(view->format)->bpb == fmtl->bpb);
2985
assert(view->levels == 1);
2987
const uint32_t view_width_px =
2988
isl_minify(surf->logical_level0_px.width, view->base_level);
2989
const uint32_t view_height_px =
2990
isl_minify(surf->logical_level0_px.height, view->base_level);
2992
assert(surf->samples == 1);
2993
const uint32_t view_width_el = isl_align_div_npot(view_width_px, fmtl->bw);
2994
const uint32_t view_height_el = isl_align_div_npot(view_height_px, fmtl->bh);
2996
/* If we ever enable 3D block formats, we'll need to re-think this */
2997
assert(fmtl->bd == 1);
2999
if (view->array_len > 1) {
3000
/* The Skylake PRM Vol. 2d, "RENDER_SURFACE_STATE::X Offset" says:
3002
* "If Surface Array is enabled, this field must be zero."
3004
* The PRMs for other hardware have similar text. This is also tricky
3005
* to handle with things like BLORP's SW offsetting because the
3006
* increased surface size required for the offset may result in an image
3007
* height greater than qpitch.
3009
if (view->base_level > 0)
3012
/* On Haswell and earlier, RENDER_SURFACE_STATE doesn't have a QPitch
3013
* field; it only has "array pitch span" which means the QPitch is
3014
* automatically calculated. Since we're smashing the surface format
3015
* (block formats are subtly different) and the number of miplevels,
3016
* that calculation will get thrown off. This means we can't do arrays
3019
* On Broadwell, we do have a QPitch field which we can control.
3020
* However, HALIGN and VALIGN are specified in pixels and are
3021
* hard-coded to align to exactly the block size of the compressed
3022
* texture. This means that, when reinterpreted as a non-compressed
3023
* the QPitch may be anything but the HW requires it to be properly
3026
if (ISL_GFX_VER(dev) < 9)
3029
*ucompr_surf = *surf;
3030
ucompr_surf->levels = 1;
3031
ucompr_surf->format = view_format;
3033
/* We're making an uncompressed view here. The image dimensions
3034
* need to be scaled down by the block size.
3036
assert(ucompr_surf->logical_level0_px.width == view_width_px);
3037
assert(ucompr_surf->logical_level0_px.height == view_height_px);
3038
ucompr_surf->logical_level0_px.width = view_width_el;
3039
ucompr_surf->logical_level0_px.height = view_height_el;
3040
ucompr_surf->phys_level0_sa = isl_surf_get_phys_level0_el(surf);
3042
/* The surface mostly stays as-is; there is no offset */
3047
/* The view remains the same */
3048
*ucompr_view = *view;
3050
/* If only one array slice is requested, directly offset to that slice.
3051
* We could, in theory, still use arrays in some cases but BLORP isn't
3052
* prepared for this and everyone who calls this function should be
3053
* prepared to handle an X/Y offset.
3055
isl_surf_get_image_offset_B_tile_el(surf,
3057
surf->dim == ISL_SURF_DIM_3D ?
3058
0 : view->base_array_layer,
3059
surf->dim == ISL_SURF_DIM_3D ?
3060
view->base_array_layer : 0,
3065
/* Even for cube maps there will be only single face, therefore drop the
3066
* corresponding flag if present.
3068
const isl_surf_usage_flags_t usage =
3069
surf->usage & (~ISL_SURF_USAGE_CUBE_BIT);
3072
ok = isl_surf_init(dev, ucompr_surf,
3073
.dim = ISL_SURF_DIM_2D,
3074
.format = view_format,
3075
.width = view_width_el,
3076
.height = view_height_el,
3081
.row_pitch_B = surf->row_pitch_B,
3083
.tiling_flags = (1 << surf->tiling));
3086
/* The newly created image represents the one subimage we're
3087
* referencing with this view so it only has one array slice and
3090
*ucompr_view = *view;
3091
ucompr_view->base_array_layer = 0;
3092
ucompr_view->base_level = 0;
3099
isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
3100
enum isl_surf_dim dim,
3101
enum isl_msaa_layout msaa_layout,
3104
uint32_t row_pitch_B,
3105
uint32_t array_pitch_el_rows,
3106
uint32_t total_x_offset_el,
3107
uint32_t total_y_offset_el,
3108
uint32_t total_z_offset_el,
3109
uint32_t total_array_offset,
3110
uint64_t *tile_offset_B,
3111
uint32_t *x_offset_el,
3112
uint32_t *y_offset_el,
3113
uint32_t *z_offset_el,
3114
uint32_t *array_offset)
3116
if (tiling == ISL_TILING_LINEAR) {
3117
assert(bpb % 8 == 0);
3118
assert(samples == 1);
3119
assert(total_z_offset_el == 0 && total_array_offset == 0);
3120
*tile_offset_B = (uint64_t)total_y_offset_el * row_pitch_B +
3121
(uint64_t)total_x_offset_el * (bpb / 8);
3129
struct isl_tile_info tile_info;
3130
isl_tiling_get_info(tiling, dim, msaa_layout, bpb, samples, &tile_info);
3132
/* Pitches must make sense with the tiling */
3133
assert(row_pitch_B % tile_info.phys_extent_B.width == 0);
3134
if (tile_info.logical_extent_el.d > 1 || tile_info.logical_extent_el.a > 1)
3135
assert(array_pitch_el_rows % tile_info.logical_extent_el.h == 0);
3137
/* For non-power-of-two formats, we need the address to be both tile and
3138
* element-aligned. The easiest way to achieve this is to work with a tile
3139
* that is three times as wide as the regular tile.
3141
* The tile info returned by get_tile_info has a logical size that is an
3142
* integer number of tile_info.format_bpb size elements. To scale the
3143
* tile, we scale up the physical width and then treat the logical tile
3144
* size as if it has bpb size elements.
3146
const uint32_t tile_el_scale = bpb / tile_info.format_bpb;
3147
tile_info.phys_extent_B.width *= tile_el_scale;
3149
/* Compute the offset into the tile */
3150
*x_offset_el = total_x_offset_el % tile_info.logical_extent_el.w;
3151
*y_offset_el = total_y_offset_el % tile_info.logical_extent_el.h;
3152
*z_offset_el = total_z_offset_el % tile_info.logical_extent_el.d;
3153
*array_offset = total_array_offset % tile_info.logical_extent_el.a;
3155
/* Compute the offset of the tile in units of whole tiles */
3156
uint32_t x_offset_tl = total_x_offset_el / tile_info.logical_extent_el.w;
3157
uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h;
3158
uint32_t z_offset_tl = total_z_offset_el / tile_info.logical_extent_el.d;
3159
uint32_t a_offset_tl = total_array_offset / tile_info.logical_extent_el.a;
3161
/* Compute an array pitch in number of tiles */
3162
uint32_t array_pitch_tl_rows =
3163
array_pitch_el_rows / tile_info.logical_extent_el.h;
3165
/* Add the Z and array offset to the Y offset to get a 2D offset */
3166
y_offset_tl += (z_offset_tl + a_offset_tl) * array_pitch_tl_rows;
3169
(uint64_t)y_offset_tl * tile_info.phys_extent_B.h * row_pitch_B +
3170
(uint64_t)x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w;
3174
isl_surf_get_depth_format(const struct isl_device *dev,
3175
const struct isl_surf *surf)
3177
/* Support for separate stencil buffers began in gfx5. Support for
3178
* interleaved depthstencil buffers ceased in gfx7. The intermediate gens,
3179
* those that supported separate and interleaved stencil, were gfx5 and
3182
* For a list of all available formats, see the Sandybridge PRM >> Volume
3183
* 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
3187
bool has_stencil = surf->usage & ISL_SURF_USAGE_STENCIL_BIT;
3189
assert(surf->usage & ISL_SURF_USAGE_DEPTH_BIT);
3192
assert(ISL_GFX_VER(dev) < 7);
3194
switch (surf->format) {
3196
unreachable("bad isl depth format");
3197
case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS:
3198
assert(ISL_GFX_VER(dev) < 7);
3199
return 0; /* D32_FLOAT_S8X24_UINT */
3200
case ISL_FORMAT_R32_FLOAT:
3201
assert(!has_stencil);
3202
return 1; /* D32_FLOAT */
3203
case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
3205
assert(ISL_GFX_VER(dev) < 7);
3206
return 2; /* D24_UNORM_S8_UINT */
3208
assert(ISL_GFX_VER(dev) >= 5);
3209
return 3; /* D24_UNORM_X8_UINT */
3211
case ISL_FORMAT_R16_UNORM:
3212
assert(!has_stencil);
3213
return 5; /* D16_UNORM */
3218
isl_swizzle_supports_rendering(const struct intel_device_info *devinfo,
3219
struct isl_swizzle swizzle)
3221
if (devinfo->platform == INTEL_PLATFORM_HSW) {
3222
/* From the Haswell PRM,
3223
* RENDER_SURFACE_STATE::Shader Channel Select Red
3225
* "The Shader channel selects also define which shader channels are
3226
* written to which surface channel. If the Shader channel select is
3227
* SCS_ZERO or SCS_ONE then it is not written to the surface. If the
3228
* shader channel select is SCS_RED it is written to the surface red
3229
* channel and so on. If more than one shader channel select is set
3230
* to the same surface channel only the first shader channel in RGBA
3231
* order will be written."
3234
} else if (devinfo->ver <= 7) {
3235
/* Ivy Bridge and early doesn't have any swizzling */
3236
return isl_swizzle_is_identity(swizzle);
3238
/* From the Sky Lake PRM Vol. 2d,
3239
* RENDER_SURFACE_STATE::Shader Channel Select Red
3241
* "For Render Target, Red, Green and Blue Shader Channel Selects
3242
* MUST be such that only valid components can be swapped i.e. only
3243
* change the order of components in the pixel. Any other values for
3244
* these Shader Channel Select fields are not valid for Render
3245
* Targets. This also means that there MUST not be multiple shader
3246
* channels mapped to the same RT channel."
3248
* From the Sky Lake PRM Vol. 2d,
3249
* RENDER_SURFACE_STATE::Shader Channel Select Alpha
3251
* "For Render Target, this field MUST be programmed to
3252
* value = SCS_ALPHA."
3254
return (swizzle.r == ISL_CHANNEL_SELECT_RED ||
3255
swizzle.r == ISL_CHANNEL_SELECT_GREEN ||
3256
swizzle.r == ISL_CHANNEL_SELECT_BLUE) &&
3257
(swizzle.g == ISL_CHANNEL_SELECT_RED ||
3258
swizzle.g == ISL_CHANNEL_SELECT_GREEN ||
3259
swizzle.g == ISL_CHANNEL_SELECT_BLUE) &&
3260
(swizzle.b == ISL_CHANNEL_SELECT_RED ||
3261
swizzle.b == ISL_CHANNEL_SELECT_GREEN ||
3262
swizzle.b == ISL_CHANNEL_SELECT_BLUE) &&
3263
swizzle.r != swizzle.g &&
3264
swizzle.r != swizzle.b &&
3265
swizzle.g != swizzle.b &&
3266
swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
3270
static enum isl_channel_select
3271
swizzle_select(enum isl_channel_select chan, struct isl_swizzle swizzle)
3274
case ISL_CHANNEL_SELECT_ZERO:
3275
case ISL_CHANNEL_SELECT_ONE:
3277
case ISL_CHANNEL_SELECT_RED:
3279
case ISL_CHANNEL_SELECT_GREEN:
3281
case ISL_CHANNEL_SELECT_BLUE:
3283
case ISL_CHANNEL_SELECT_ALPHA:
3286
unreachable("Invalid swizzle component");
3291
* Returns the single swizzle that is equivalent to applying the two given
3292
* swizzles in sequence.
3295
isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second)
3297
return (struct isl_swizzle) {
3298
.r = swizzle_select(first.r, second),
3299
.g = swizzle_select(first.g, second),
3300
.b = swizzle_select(first.b, second),
3301
.a = swizzle_select(first.a, second),
3306
* Returns a swizzle that is the pseudo-inverse of this swizzle.
3309
isl_swizzle_invert(struct isl_swizzle swizzle)
3311
/* Default to zero for channels which do not show up in the swizzle */
3312
enum isl_channel_select chans[4] = {
3313
ISL_CHANNEL_SELECT_ZERO,
3314
ISL_CHANNEL_SELECT_ZERO,
3315
ISL_CHANNEL_SELECT_ZERO,
3316
ISL_CHANNEL_SELECT_ZERO,
3319
/* We go in ABGR order so that, if there are any duplicates, the first one
3320
* is taken if you look at it in RGBA order. This is what Haswell hardware
3321
* does for render target swizzles.
3323
if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
3324
chans[swizzle.a - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_ALPHA;
3325
if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
3326
chans[swizzle.b - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_BLUE;
3327
if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
3328
chans[swizzle.g - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_GREEN;
3329
if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
3330
chans[swizzle.r - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_RED;
3332
return (struct isl_swizzle) { chans[0], chans[1], chans[2], chans[3] };
3336
isl_color_value_channel(union isl_color_value src,
3337
enum isl_channel_select chan,
3340
if (chan == ISL_CHANNEL_SELECT_ZERO)
3342
if (chan == ISL_CHANNEL_SELECT_ONE)
3345
assert(chan >= ISL_CHANNEL_SELECT_RED);
3346
assert(chan < ISL_CHANNEL_SELECT_RED + 4);
3348
return src.u32[chan - ISL_CHANNEL_SELECT_RED];
3351
/** Applies an inverse swizzle to a color value */
3352
union isl_color_value
3353
isl_color_value_swizzle(union isl_color_value src,
3354
struct isl_swizzle swizzle,
3357
uint32_t one = is_float ? 0x3f800000 : 1;
3359
return (union isl_color_value) { .u32 = {
3360
isl_color_value_channel(src, swizzle.r, one),
3361
isl_color_value_channel(src, swizzle.g, one),
3362
isl_color_value_channel(src, swizzle.b, one),
3363
isl_color_value_channel(src, swizzle.a, one),
3367
/** Applies an inverse swizzle to a color value */
3368
union isl_color_value
3369
isl_color_value_swizzle_inv(union isl_color_value src,
3370
struct isl_swizzle swizzle)
3372
union isl_color_value dst = { .u32 = { 0, } };
3374
/* We assign colors in ABGR order so that the first one will be taken in
3375
* RGBA precedence order. According to the PRM docs for shader channel
3376
* select, this matches Haswell hardware behavior.
3378
if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
3379
dst.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = src.u32[3];
3380
if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
3381
dst.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = src.u32[2];
3382
if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
3383
dst.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = src.u32[1];
3384
if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
3385
dst.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = src.u32[0];
3391
isl_format_get_aux_map_encoding(enum isl_format format)
3394
case ISL_FORMAT_R32G32B32A32_FLOAT: return 0x11;
3395
case ISL_FORMAT_R32G32B32X32_FLOAT: return 0x11;
3396
case ISL_FORMAT_R32G32B32A32_SINT: return 0x12;
3397
case ISL_FORMAT_R32G32B32A32_UINT: return 0x13;
3398
case ISL_FORMAT_R16G16B16A16_UNORM: return 0x14;
3399
case ISL_FORMAT_R16G16B16A16_SNORM: return 0x15;
3400
case ISL_FORMAT_R16G16B16A16_SINT: return 0x16;
3401
case ISL_FORMAT_R16G16B16A16_UINT: return 0x17;
3402
case ISL_FORMAT_R16G16B16A16_FLOAT: return 0x10;
3403
case ISL_FORMAT_R16G16B16X16_FLOAT: return 0x10;
3404
case ISL_FORMAT_R32G32_FLOAT: return 0x11;
3405
case ISL_FORMAT_R32G32_SINT: return 0x12;
3406
case ISL_FORMAT_R32G32_UINT: return 0x13;
3407
case ISL_FORMAT_B8G8R8A8_UNORM: return 0xA;
3408
case ISL_FORMAT_B8G8R8X8_UNORM: return 0xA;
3409
case ISL_FORMAT_B8G8R8A8_UNORM_SRGB: return 0xA;
3410
case ISL_FORMAT_B8G8R8X8_UNORM_SRGB: return 0xA;
3411
case ISL_FORMAT_R10G10B10A2_UNORM: return 0x18;
3412
case ISL_FORMAT_R10G10B10A2_UNORM_SRGB: return 0x18;
3413
case ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM: return 0x19;
3414
case ISL_FORMAT_R10G10B10A2_UINT: return 0x1A;
3415
case ISL_FORMAT_R8G8B8A8_UNORM: return 0xA;
3416
case ISL_FORMAT_R8G8B8A8_UNORM_SRGB: return 0xA;
3417
case ISL_FORMAT_R8G8B8A8_SNORM: return 0x1B;
3418
case ISL_FORMAT_R8G8B8A8_SINT: return 0x1C;
3419
case ISL_FORMAT_R8G8B8A8_UINT: return 0x1D;
3420
case ISL_FORMAT_R16G16_UNORM: return 0x14;
3421
case ISL_FORMAT_R16G16_SNORM: return 0x15;
3422
case ISL_FORMAT_R16G16_SINT: return 0x16;
3423
case ISL_FORMAT_R16G16_UINT: return 0x17;
3424
case ISL_FORMAT_R16G16_FLOAT: return 0x10;
3425
case ISL_FORMAT_B10G10R10A2_UNORM: return 0x18;
3426
case ISL_FORMAT_B10G10R10A2_UNORM_SRGB: return 0x18;
3427
case ISL_FORMAT_R11G11B10_FLOAT: return 0x1E;
3428
case ISL_FORMAT_R32_SINT: return 0x12;
3429
case ISL_FORMAT_R32_UINT: return 0x13;
3430
case ISL_FORMAT_R32_FLOAT: return 0x11;
3431
case ISL_FORMAT_R24_UNORM_X8_TYPELESS: return 0x13;
3432
case ISL_FORMAT_B5G6R5_UNORM: return 0xA;
3433
case ISL_FORMAT_B5G6R5_UNORM_SRGB: return 0xA;
3434
case ISL_FORMAT_B5G5R5A1_UNORM: return 0xA;
3435
case ISL_FORMAT_B5G5R5A1_UNORM_SRGB: return 0xA;
3436
case ISL_FORMAT_B4G4R4A4_UNORM: return 0xA;
3437
case ISL_FORMAT_B4G4R4A4_UNORM_SRGB: return 0xA;
3438
case ISL_FORMAT_R8G8_UNORM: return 0xA;
3439
case ISL_FORMAT_R8G8_SNORM: return 0x1B;
3440
case ISL_FORMAT_R8G8_SINT: return 0x1C;
3441
case ISL_FORMAT_R8G8_UINT: return 0x1D;
3442
case ISL_FORMAT_R16_UNORM: return 0x14;
3443
case ISL_FORMAT_R16_SNORM: return 0x15;
3444
case ISL_FORMAT_R16_SINT: return 0x16;
3445
case ISL_FORMAT_R16_UINT: return 0x17;
3446
case ISL_FORMAT_R16_FLOAT: return 0x10;
3447
case ISL_FORMAT_B5G5R5X1_UNORM: return 0xA;
3448
case ISL_FORMAT_B5G5R5X1_UNORM_SRGB: return 0xA;
3449
case ISL_FORMAT_A1B5G5R5_UNORM: return 0xA;
3450
case ISL_FORMAT_A4B4G4R4_UNORM: return 0xA;
3451
case ISL_FORMAT_R8_UNORM: return 0xA;
3452
case ISL_FORMAT_R8_SNORM: return 0x1B;
3453
case ISL_FORMAT_R8_SINT: return 0x1C;
3454
case ISL_FORMAT_R8_UINT: return 0x1D;
3455
case ISL_FORMAT_A8_UNORM: return 0xA;
3456
case ISL_FORMAT_PLANAR_420_8: return 0xF;
3457
case ISL_FORMAT_PLANAR_420_10: return 0x7;
3458
case ISL_FORMAT_PLANAR_420_12: return 0x8;
3459
case ISL_FORMAT_PLANAR_420_16: return 0x8;
3460
case ISL_FORMAT_YCRCB_NORMAL: return 0x3;
3461
case ISL_FORMAT_YCRCB_SWAPY: return 0xB;
3463
unreachable("Unsupported aux-map format!");
3469
* Returns compression format encoding for Unified Lossless Compression
3472
isl_get_render_compression_format(enum isl_format format)
3474
/* From the Bspec, Enumeration_RenderCompressionFormat section (53726): */
3476
case ISL_FORMAT_R32G32B32A32_FLOAT:
3477
case ISL_FORMAT_R32G32B32X32_FLOAT:
3478
case ISL_FORMAT_R32G32B32A32_SINT:
3480
case ISL_FORMAT_R32G32B32A32_UINT:
3482
case ISL_FORMAT_R32G32_FLOAT:
3483
case ISL_FORMAT_R32G32_SINT:
3485
case ISL_FORMAT_R32G32_UINT:
3487
case ISL_FORMAT_R16G16B16A16_UNORM:
3488
case ISL_FORMAT_R16G16B16X16_UNORM:
3489
case ISL_FORMAT_R16G16B16A16_UINT:
3491
case ISL_FORMAT_R16G16B16A16_SNORM:
3492
case ISL_FORMAT_R16G16B16A16_SINT:
3493
case ISL_FORMAT_R16G16B16A16_FLOAT:
3494
case ISL_FORMAT_R16G16B16X16_FLOAT:
3496
case ISL_FORMAT_R16G16_UNORM:
3497
case ISL_FORMAT_R16G16_UINT:
3499
case ISL_FORMAT_R16G16_SNORM:
3500
case ISL_FORMAT_R16G16_SINT:
3501
case ISL_FORMAT_R16G16_FLOAT:
3503
case ISL_FORMAT_B8G8R8A8_UNORM:
3504
case ISL_FORMAT_B8G8R8X8_UNORM:
3505
case ISL_FORMAT_B8G8R8A8_UNORM_SRGB:
3506
case ISL_FORMAT_B8G8R8X8_UNORM_SRGB:
3507
case ISL_FORMAT_R8G8B8A8_UNORM:
3508
case ISL_FORMAT_R8G8B8X8_UNORM:
3509
case ISL_FORMAT_R8G8B8A8_UNORM_SRGB:
3510
case ISL_FORMAT_R8G8B8X8_UNORM_SRGB:
3511
case ISL_FORMAT_R8G8B8A8_UINT:
3513
case ISL_FORMAT_R8G8B8A8_SNORM:
3514
case ISL_FORMAT_R8G8B8A8_SINT:
3516
case ISL_FORMAT_B5G6R5_UNORM:
3517
case ISL_FORMAT_B5G6R5_UNORM_SRGB:
3518
case ISL_FORMAT_B5G5R5A1_UNORM:
3519
case ISL_FORMAT_B5G5R5A1_UNORM_SRGB:
3520
case ISL_FORMAT_B4G4R4A4_UNORM:
3521
case ISL_FORMAT_B4G4R4A4_UNORM_SRGB:
3522
case ISL_FORMAT_B5G5R5X1_UNORM:
3523
case ISL_FORMAT_B5G5R5X1_UNORM_SRGB:
3524
case ISL_FORMAT_A1B5G5R5_UNORM:
3525
case ISL_FORMAT_A4B4G4R4_UNORM:
3526
case ISL_FORMAT_R8G8_UNORM:
3527
case ISL_FORMAT_R8G8_UINT:
3529
case ISL_FORMAT_R8G8_SNORM:
3530
case ISL_FORMAT_R8G8_SINT:
3532
case ISL_FORMAT_R10G10B10A2_UNORM:
3533
case ISL_FORMAT_R10G10B10A2_UNORM_SRGB:
3534
case ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM:
3535
case ISL_FORMAT_R10G10B10A2_UINT:
3536
case ISL_FORMAT_B10G10R10A2_UNORM:
3537
case ISL_FORMAT_B10G10R10X2_UNORM:
3538
case ISL_FORMAT_B10G10R10A2_UNORM_SRGB:
3540
case ISL_FORMAT_R11G11B10_FLOAT:
3542
case ISL_FORMAT_R32_SINT:
3543
case ISL_FORMAT_R32_FLOAT:
3545
case ISL_FORMAT_R32_UINT:
3546
case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
3548
case ISL_FORMAT_R16_UNORM:
3549
case ISL_FORMAT_R16_UINT:
3551
case ISL_FORMAT_R16_SNORM:
3552
case ISL_FORMAT_R16_SINT:
3553
case ISL_FORMAT_R16_FLOAT:
3555
case ISL_FORMAT_R8_UNORM:
3556
case ISL_FORMAT_R8_UINT:
3557
case ISL_FORMAT_A8_UNORM:
3559
case ISL_FORMAT_R8_SNORM:
3560
case ISL_FORMAT_R8_SINT:
3563
unreachable("Unsupported render compression format!");
3569
isl_aux_op_to_name(enum isl_aux_op op)
3571
static const char *names[] = {
3572
[ISL_AUX_OP_NONE] = "none",
3573
[ISL_AUX_OP_FAST_CLEAR] = "fast-clear",
3574
[ISL_AUX_OP_FULL_RESOLVE] = "full-resolve",
3575
[ISL_AUX_OP_PARTIAL_RESOLVE] = "partial-resolve",
3576
[ISL_AUX_OP_AMBIGUATE] = "ambiguate",
3578
assert(op < ARRAY_SIZE(names));
added
removed
src/intel/isl/isl.c
