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Viewing changes to src/freedreno/registers/mdp/mdp5.xml

  • Committer: mmach
  • Date: 2022-09-22 19:56:13 UTC
  • Revision ID: netbit73@gmail.com-20220922195613-wtik9mmy20tmor0i
2022-09-22 21:17:09

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src/freedreno/registers/mdp/mdp5.xml
1
 
<?xml version="1.0" encoding="UTF-8"?>
2
 
<database xmlns="http://nouveau.freedesktop.org/"
3
 
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
 
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5
 
<import file="freedreno_copyright.xml"/>
6
 
<import file="mdp/mdp_common.xml"/>
7
 
 
8
 
<!-- where does this belong? -->
9
 
<domain name="VBIF" width="32">
10
 
</domain>
11
 
 
12
 
<domain name="MDSS" width="32">
13
 
        <reg32 offset="0x00000" name="HW_VERSION">
14
 
                <bitfield name="STEP" low="0" high="15" type="uint"/>
15
 
                <bitfield name="MINOR" low="16" high="27" type="uint"/>
16
 
                <bitfield name="MAJOR" low="28" high="31" type="uint"/>
17
 
        </reg32>
18
 
 
19
 
        <reg32 offset="0x00010" name="HW_INTR_STATUS">
20
 
                <bitfield name="INTR_MDP"  pos="0"  type="boolean"/>
21
 
                <bitfield name="INTR_DSI0" pos="4"  type="boolean"/>
22
 
                <bitfield name="INTR_DSI1" pos="5"  type="boolean"/>
23
 
                <bitfield name="INTR_HDMI" pos="8"  type="boolean"/>
24
 
                <bitfield name="INTR_EDP"  pos="12" type="boolean"/>
25
 
        </reg32>
26
 
</domain>
27
 
 
28
 
<domain name="MDP5" width="32">
29
 
 
30
 
        <enum name="mdp5_intf_type">
31
 
                <value name="INTF_DISABLED" value="0x0"/>
32
 
                <value name="INTF_DSI"  value="0x1"/>
33
 
                <value name="INTF_HDMI" value="0x3"/>
34
 
                <value name="INTF_LCDC" value="0x5"/>
35
 
                <value name="INTF_eDP"  value="0x9"/>
36
 
                <value name="INTF_VIRTUAL"  value="0x64"/>
37
 
                <!-- non-display interfaces are listed below: -->
38
 
                <value name="INTF_WB"  value="0x65"/>
39
 
        </enum>
40
 
 
41
 
        <enum name="mdp5_intfnum">
42
 
                <value name="NO_INTF" value="0"/>
43
 
                <value name="INTF0"   value="1"/>
44
 
                <value name="INTF1"   value="2"/>
45
 
                <value name="INTF2"   value="3"/>
46
 
                <value name="INTF3"   value="4"/>
47
 
        </enum>
48
 
 
49
 
        <enum name="mdp5_pipe">
50
 
                <value name="SSPP_NONE" value="0"/>
51
 
                <value name="SSPP_VIG0" value="1"/>
52
 
                <value name="SSPP_VIG1" value="2"/>
53
 
                <value name="SSPP_VIG2" value="3"/>
54
 
                <value name="SSPP_RGB0" value="4"/>
55
 
                <value name="SSPP_RGB1" value="5"/>
56
 
                <value name="SSPP_RGB2" value="6"/>
57
 
                <value name="SSPP_DMA0" value="7"/>
58
 
                <value name="SSPP_DMA1" value="8"/>
59
 
                <value name="SSPP_VIG3" value="9"/>
60
 
                <value name="SSPP_RGB3" value="10"/>
61
 
                <value name="SSPP_CURSOR0" value="11"/>
62
 
                <value name="SSPP_CURSOR1" value="12"/>
63
 
        </enum>
64
 
 
65
 
        <enum name="mdp5_format">
66
 
                <!-- TODO -->
67
 
                <value name="DUMMY" value="0"/>
68
 
        </enum>
69
 
 
70
 
        <enum name="mdp5_ctl_mode">
71
 
                <value name="MODE_NONE" value="0"/>
72
 
                <value name="MODE_WB_0_BLOCK" value="1"/>
73
 
                <value name="MODE_WB_1_BLOCK" value="2"/>
74
 
                <value name="MODE_WB_0_LINE" value="3"/>
75
 
                <value name="MODE_WB_1_LINE" value="4"/>
76
 
                <value name="MODE_WB_2_LINE" value="5"/>
77
 
        </enum>
78
 
 
79
 
        <enum name="mdp5_pack_3d">
80
 
                <value name="PACK_3D_FRAME_INT" value="0"/>
81
 
                <value name="PACK_3D_H_ROW_INT" value="1"/>
82
 
                <value name="PACK_3D_V_ROW_INT" value="2"/>
83
 
                <value name="PACK_3D_COL_INT"   value="3"/>
84
 
        </enum>
85
 
 
86
 
        <enum name="mdp5_scale_filter">
87
 
                <value name="SCALE_FILTER_NEAREST" value="0"/>
88
 
                <value name="SCALE_FILTER_BIL" value="1"/>
89
 
                <value name="SCALE_FILTER_PCMN" value="2"/>
90
 
                <value name="SCALE_FILTER_CA" value="3"/>
91
 
        </enum>
92
 
 
93
 
        <enum name="mdp5_pipe_bwc">
94
 
                <value name="BWC_LOSSLESS" value="0"/>
95
 
                <value name="BWC_Q_HIGH"   value="1"/>
96
 
                <value name="BWC_Q_MED"    value="2"/>
97
 
        </enum>
98
 
 
99
 
        <enum name="mdp5_cursor_format">
100
 
                <value name="CURSOR_FMT_ARGB8888" value="0"/>
101
 
                <value name="CURSOR_FMT_ARGB1555" value="2"/>
102
 
                <value name="CURSOR_FMT_ARGB4444" value="4"/>
103
 
        </enum>
104
 
 
105
 
        <enum name="mdp5_cursor_alpha">
106
 
                <value name="CURSOR_ALPHA_CONST" value="0"/>
107
 
                <value name="CURSOR_ALPHA_PER_PIXEL" value="2"/>
108
 
        </enum>
109
 
 
110
 
        <bitset name="MDP5_IRQ">
111
 
                <bitfield name="WB_0_DONE"                pos="0"  type="boolean"/>
112
 
                <bitfield name="WB_1_DONE"                pos="1"  type="boolean"/>
113
 
                <bitfield name="WB_2_DONE"                pos="4"  type="boolean"/>
114
 
                <bitfield name="PING_PONG_0_DONE"         pos="8"  type="boolean"/>
115
 
                <bitfield name="PING_PONG_1_DONE"         pos="9"  type="boolean"/>
116
 
                <bitfield name="PING_PONG_2_DONE"         pos="10" type="boolean"/>
117
 
                <bitfield name="PING_PONG_3_DONE"         pos="11" type="boolean"/>
118
 
                <bitfield name="PING_PONG_0_RD_PTR"       pos="12" type="boolean"/>
119
 
                <bitfield name="PING_PONG_1_RD_PTR"       pos="13" type="boolean"/>
120
 
                <bitfield name="PING_PONG_2_RD_PTR"       pos="14" type="boolean"/>
121
 
                <bitfield name="PING_PONG_3_RD_PTR"       pos="15" type="boolean"/>
122
 
                <bitfield name="PING_PONG_0_WR_PTR"       pos="16" type="boolean"/>
123
 
                <bitfield name="PING_PONG_1_WR_PTR"       pos="17" type="boolean"/>
124
 
                <bitfield name="PING_PONG_2_WR_PTR"       pos="18" type="boolean"/>
125
 
                <bitfield name="PING_PONG_3_WR_PTR"       pos="19" type="boolean"/>
126
 
                <bitfield name="PING_PONG_0_AUTO_REF"     pos="20" type="boolean"/>
127
 
                <bitfield name="PING_PONG_1_AUTO_REF"     pos="21" type="boolean"/>
128
 
                <bitfield name="PING_PONG_2_AUTO_REF"     pos="22" type="boolean"/>
129
 
                <bitfield name="PING_PONG_3_AUTO_REF"     pos="23" type="boolean"/>
130
 
                <bitfield name="INTF0_UNDER_RUN"          pos="24" type="boolean"/>
131
 
                <bitfield name="INTF0_VSYNC"              pos="25" type="boolean"/>
132
 
                <bitfield name="INTF1_UNDER_RUN"          pos="26" type="boolean"/>
133
 
                <bitfield name="INTF1_VSYNC"              pos="27" type="boolean"/>
134
 
                <bitfield name="INTF2_UNDER_RUN"          pos="28" type="boolean"/>
135
 
                <bitfield name="INTF2_VSYNC"              pos="29" type="boolean"/>
136
 
                <bitfield name="INTF3_UNDER_RUN"          pos="30" type="boolean"/>
137
 
                <bitfield name="INTF3_VSYNC"              pos="31" type="boolean"/>
138
 
        </bitset>
139
 
 
140
 
        <bitset name="mdp5_smp_alloc" inline="yes">
141
 
        <!-- Use "mdp5_cfg->mdp.smp.clients[enum mdp5_pipe]" instead -->
142
 
                <bitfield name="CLIENT0" low="0"  high="7"  type="uint"/>
143
 
                <bitfield name="CLIENT1" low="8"  high="15" type="uint"/>
144
 
                <bitfield name="CLIENT2" low="16" high="23" type="uint"/>
145
 
        </bitset>
146
 
 
147
 
        <reg32 offset="0x00000" name="HW_VERSION">
148
 
                <bitfield name="STEP" low="0" high="15" type="uint"/>
149
 
                <bitfield name="MINOR" low="16" high="27" type="uint"/>
150
 
                <bitfield name="MAJOR" low="28" high="31" type="uint"/>
151
 
        </reg32>
152
 
 
153
 
        <reg32 offset="0x00004" name="DISP_INTF_SEL">
154
 
                <bitfield name="INTF0" low="0"  high="7"  type="mdp5_intf_type"/>
155
 
                <bitfield name="INTF1" low="8"  high="15" type="mdp5_intf_type"/>
156
 
                <bitfield name="INTF2" low="16" high="23" type="mdp5_intf_type"/>
157
 
                <bitfield name="INTF3" low="24" high="31" type="mdp5_intf_type"/>
158
 
        </reg32>
159
 
        <reg32 offset="0x00010" name="INTR_EN" type="MDP5_IRQ"/>
160
 
        <reg32 offset="0x00014" name="INTR_STATUS" type="MDP5_IRQ"/>
161
 
        <reg32 offset="0x00018" name="INTR_CLEAR" type="MDP5_IRQ"/>
162
 
        <reg32 offset="0x0001C" name="HIST_INTR_EN"/>
163
 
        <reg32 offset="0x00020" name="HIST_INTR_STATUS"/>
164
 
        <reg32 offset="0x00024" name="HIST_INTR_CLEAR"/>
165
 
        <reg32 offset="0x00028" name="SPARE_0">
166
 
                <bitfield name="SPLIT_DPL_SINGLE_FLUSH_EN" pos="0"/>
167
 
        </reg32>
168
 
 
169
 
        <array offset="0x00080" name="SMP_ALLOC_W" length="8" stride="4">
170
 
                <reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
171
 
        </array>
172
 
        <array offset="0x00130" name="SMP_ALLOC_R" length="8" stride="4">
173
 
                <reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
174
 
        </array>
175
 
 
176
 
        <enum name="mdp5_igc_type">
177
 
                <value name="IGC_VIG" value="0"/>               <!-- 0x200 -->
178
 
                <value name="IGC_RGB" value="1"/>               <!-- 0x210 -->
179
 
                <value name="IGC_DMA" value="2"/>               <!-- 0x220 -->
180
 
                <value name="IGC_DSPP" value="3"/>              <!-- 0x300 -->
181
 
        </enum>
182
 
        <array offsets="0x00200,0x00210,0x00220,0x00300" name="IGC" length="3" stride="0x10" index="mdp5_igc_type">
183
 
                <array offset="0x00" name="LUT" length="3" stride="4">
184
 
                        <reg32 offset="0" name="REG">
185
 
                                <bitfield name="VAL" low="0" high="11"/>
186
 
                                <bitfield name="INDEX_UPDATE" pos="25" type="boolean"/>
187
 
                                <!--
188
 
                                        not sure about these:
189
 
                                                /* INDEX_UPDATE */
190
 
                                                data = (1 << 25) | (((~(1 << blk_idx)) & 0x7) << 28);
191
 
                                                MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[0] & 0xFFF) | data);
192
 
                                -->
193
 
                                <bitfield name="DISABLE_PIPE_0" pos="28" type="boolean"/>
194
 
                                <bitfield name="DISABLE_PIPE_1" pos="29" type="boolean"/>
195
 
                                <bitfield name="DISABLE_PIPE_2" pos="30" type="boolean"/>
196
 
                        </reg32>
197
 
                </array>
198
 
        </array>
199
 
        <reg32 offset="0x002f4" name="SPLIT_DPL_EN"/>
200
 
        <reg32 offset="0x002f8" name="SPLIT_DPL_UPPER">
201
 
                <bitfield name="SMART_PANEL" pos="1" type="boolean"/>
202
 
                <bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
203
 
                <bitfield name="INTF1_SW_TRG_MUX" pos="4" type="boolean"/>
204
 
                <bitfield name="INTF2_SW_TRG_MUX" pos="8" type="boolean"/>
205
 
        </reg32>
206
 
        <reg32 offset="0x003f0" name="SPLIT_DPL_LOWER">
207
 
                <bitfield name="SMART_PANEL" pos="1" type="boolean"/>
208
 
                <bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
209
 
                <bitfield name="INTF1_TG_SYNC" pos="4" type="boolean"/>
210
 
                <bitfield name="INTF2_TG_SYNC" pos="8" type="boolean"/>
211
 
        </reg32>
212
 
 
213
 
<!-- check length/index.. -->
214
 
        <array doffsets="mdp5_cfg->ctl.base[0],mdp5_cfg->ctl.base[1],mdp5_cfg->ctl.base[2],mdp5_cfg->ctl.base[3],mdp5_cfg->ctl.base[4]" name="CTL" length="5" stride="0x400">
215
 
                <array offsets="0x000,0x004,0x008,0x00C,0x010,0x024" name="LAYER" length="6" stride="4">
216
 
                        <!--
217
 
                        NOTE: for backwards compat (from when there were fewer stages),
218
 
                        this register has the low three bits of mdp_mixer_stage_id, with
219
 
                        the high bit coming from LAYER_EXT
220
 
                         -->
221
 
                        <reg32 offset="0" name="REG">
222
 
                                <bitfield name="VIG0"  low="0"  high="2"  type="uint"/>
223
 
                                <bitfield name="VIG1"  low="3"  high="5"  type="uint"/>
224
 
                                <bitfield name="VIG2"  low="6"  high="8"  type="uint"/>
225
 
                                <bitfield name="RGB0"  low="9"  high="11" type="uint"/>
226
 
                                <bitfield name="RGB1"  low="12" high="14" type="uint"/>
227
 
                                <bitfield name="RGB2"  low="15" high="17" type="uint"/>
228
 
                                <bitfield name="DMA0"  low="18" high="20" type="uint"/>
229
 
                                <bitfield name="DMA1"  low="21" high="23" type="uint"/>
230
 
                                <bitfield name="BORDER_COLOR" pos="24" type="boolean"/>
231
 
                                <bitfield name="CURSOR_OUT"   pos="25" type="boolean"/>
232
 
                                <bitfield name="VIG3"  low="26"  high="28"  type="uint"/>
233
 
                                <bitfield name="RGB3"  low="29" high="31" type="uint"/>
234
 
                        </reg32>
235
 
                </array>
236
 
                <reg32 offset="0x014" name="OP">
237
 
                        <bitfield name="MODE" low="0" high="3" type="mdp5_ctl_mode"/>
238
 
                        <bitfield name="INTF_NUM" low="4" high="6" type="mdp5_intfnum"/>
239
 
                        <bitfield name="CMD_MODE" pos="17" type="boolean"/>
240
 
                        <bitfield name="PACK_3D_ENABLE" pos="19" type="boolean"/>
241
 
                        <bitfield name="PACK_3D" low="20" high="21" type="mdp5_pack_3d"/>
242
 
                </reg32>
243
 
                <reg32 offset="0x018" name="FLUSH">
244
 
                        <bitfield name="VIG0" pos="0"  type="boolean"/>
245
 
                        <bitfield name="VIG1" pos="1"  type="boolean"/>
246
 
                        <bitfield name="VIG2" pos="2"  type="boolean"/>
247
 
                        <bitfield name="RGB0" pos="3"  type="boolean"/>
248
 
                        <bitfield name="RGB1" pos="4"  type="boolean"/>
249
 
                        <bitfield name="RGB2" pos="5"  type="boolean"/>
250
 
                        <bitfield name="LM0"  pos="6"  type="boolean"/>
251
 
                        <bitfield name="LM1"  pos="7"  type="boolean"/>
252
 
                        <bitfield name="LM2"  pos="8"  type="boolean"/>
253
 
                        <bitfield name="LM3"  pos="9"  type="boolean"/>
254
 
                        <bitfield name="LM4"  pos="10"  type="boolean"/>
255
 
                        <bitfield name="DMA0" pos="11" type="boolean"/>
256
 
                        <bitfield name="DMA1" pos="12" type="boolean"/>
257
 
                        <bitfield name="DSPP0" pos="13" type="boolean"/>
258
 
                        <bitfield name="DSPP1" pos="14" type="boolean"/>
259
 
                        <bitfield name="DSPP2" pos="15" type="boolean"/>
260
 
                        <bitfield name="WB"   pos="16" type="boolean"/>
261
 
                        <bitfield name="CTL"   pos="17" type="boolean"/>
262
 
                        <bitfield name="VIG3" pos="18"  type="boolean"/>
263
 
                        <bitfield name="RGB3" pos="19"  type="boolean"/>
264
 
                        <bitfield name="LM5"  pos="20"  type="boolean"/>
265
 
                        <bitfield name="DSPP3" pos="21" type="boolean"/>
266
 
                        <bitfield name="CURSOR_0" pos="22" type="boolean"/>
267
 
                        <bitfield name="CURSOR_1" pos="23" type="boolean"/>
268
 
                        <bitfield name="CHROMADOWN_0" pos="26" type="boolean"/>
269
 
                        <bitfield name="TIMING_3" pos="28" type="boolean"/>
270
 
                        <bitfield name="TIMING_2" pos="29" type="boolean"/>
271
 
                        <bitfield name="TIMING_1" pos="30" type="boolean"/>
272
 
                        <bitfield name="TIMING_0" pos="31" type="boolean"/>
273
 
                </reg32>
274
 
                <reg32 offset="0x01C" name="START"/>
275
 
                <reg32 offset="0x020" name="PACK_3D"/>
276
 
                <array offsets="0x040,0x044,0x048,0x04C,0x050,0x054" name="LAYER_EXT" length="6" stride="4">
277
 
                        <reg32 offset="0" name="REG">
278
 
                                <bitfield name="VIG0_BIT3"  pos="0"  type="boolean"/>
279
 
                                <bitfield name="VIG1_BIT3"  pos="2"  type="boolean"/>
280
 
                                <bitfield name="VIG2_BIT3"  pos="4"  type="boolean"/>
281
 
                                <bitfield name="VIG3_BIT3"  pos="6"  type="boolean"/>
282
 
                                <bitfield name="RGB0_BIT3"  pos="8"  type="boolean"/>
283
 
                                <bitfield name="RGB1_BIT3"  pos="10"  type="boolean"/>
284
 
                                <bitfield name="RGB2_BIT3"  pos="12"  type="boolean"/>
285
 
                                <bitfield name="RGB3_BIT3"  pos="14"  type="boolean"/>
286
 
                                <bitfield name="DMA0_BIT3"  pos="16"  type="boolean"/>
287
 
                                <bitfield name="DMA1_BIT3"  pos="18"  type="boolean"/>
288
 
                                <bitfield name="CURSOR0" low="20"  high="23"  type="mdp_mixer_stage_id"/>
289
 
                                <bitfield name="CURSOR1" low="26"  high="29"  type="mdp_mixer_stage_id"/>
290
 
                        </reg32>
291
 
                </array>
292
 
        </array>
293
 
 
294
 
        <enum name="mdp5_data_format">
295
 
                <value name="DATA_FORMAT_RGB" value="0"/>
296
 
                <value name="DATA_FORMAT_YUV" value="1"/>
297
 
        </enum>
298
 
 
299
 
        <array doffsets="INVALID_IDX(idx),mdp5_cfg->pipe_vig.base[0],mdp5_cfg->pipe_vig.base[1],mdp5_cfg->pipe_vig.base[2],mdp5_cfg->pipe_rgb.base[0],mdp5_cfg->pipe_rgb.base[1],mdp5_cfg->pipe_rgb.base[2],mdp5_cfg->pipe_dma.base[0],mdp5_cfg->pipe_dma.base[1],mdp5_cfg->pipe_vig.base[3],mdp5_cfg->pipe_rgb.base[3],mdp5_cfg->pipe_cursor.base[0],mdp5_cfg->pipe_cursor.base[1]" name="PIPE" length="10" stride="0x400" index="mdp5_pipe">
300
 
                <reg32 offset="0x200" name="OP_MODE">
301
 
                        <bitfield name="CSC_DST_DATA_FORMAT" pos="19" type="mdp5_data_format"/>
302
 
                        <bitfield name="CSC_SRC_DATA_FORMAT" pos="18" type="mdp5_data_format"/>
303
 
                        <bitfield name="CSC_1_EN" pos="17" type="boolean"/>
304
 
                </reg32>
305
 
                <reg32 offset="0x2C4" name="HIST_CTL_BASE"/>
306
 
                <reg32 offset="0x2F0" name="HIST_LUT_BASE"/>
307
 
                <reg32 offset="0x300" name="HIST_LUT_SWAP"/>
308
 
                <reg32 offset="0x320" name="CSC_1_MATRIX_COEFF_0">
309
 
                        <bitfield name="COEFF_11" low="0" high="12" type="uint"/>
310
 
                        <bitfield name="COEFF_12" low="16" high="28" type="uint"/>
311
 
                </reg32>
312
 
                <reg32 offset="0x324" name="CSC_1_MATRIX_COEFF_1">
313
 
                        <bitfield name="COEFF_13" low="0" high="12" type="uint"/>
314
 
                        <bitfield name="COEFF_21" low="16" high="28" type="uint"/>
315
 
                </reg32>
316
 
                <reg32 offset="0x328" name="CSC_1_MATRIX_COEFF_2">
317
 
                        <bitfield name="COEFF_22" low="0" high="12" type="uint"/>
318
 
                        <bitfield name="COEFF_23" low="16" high="28" type="uint"/>
319
 
                </reg32>
320
 
                <reg32 offset="0x32c" name="CSC_1_MATRIX_COEFF_3">
321
 
                        <bitfield name="COEFF_31" low="0" high="12" type="uint"/>
322
 
                        <bitfield name="COEFF_32" low="16" high="28" type="uint"/>
323
 
                </reg32>
324
 
                <reg32 offset="0x330" name="CSC_1_MATRIX_COEFF_4">
325
 
                        <bitfield name="COEFF_33" low="0" high="12" type="uint"/>
326
 
                </reg32>
327
 
                <array offset="0x334" name="CSC_1_PRE_CLAMP" length="3" stride="4">
328
 
                        <reg32 offset="0" name="REG">
329
 
                                <bitfield name="HIGH"  low="0"  high="7"  type="uint"/>
330
 
                                <bitfield name="LOW"  low="8"  high="15"  type="uint"/>
331
 
                        </reg32>
332
 
                </array>
333
 
                <array offset="0x340" name="CSC_1_POST_CLAMP" length="3" stride="4">
334
 
                        <reg32 offset="0" name="REG">
335
 
                                <bitfield name="HIGH"  low="0"  high="7"  type="uint"/>
336
 
                                <bitfield name="LOW"  low="8"  high="15"  type="uint"/>
337
 
                        </reg32>
338
 
                </array>
339
 
                <array offset="0x34c" name="CSC_1_PRE_BIAS" length="3" stride="4">
340
 
                        <reg32 offset="0" name="REG">
341
 
                                <bitfield name="VALUE"  low="0"  high="8"  type="uint"/>
342
 
                        </reg32>
343
 
                </array>
344
 
                <array offset="0x358" name="CSC_1_POST_BIAS" length="3" stride="4">
345
 
                        <reg32 offset="0" name="REG">
346
 
                                <bitfield name="VALUE"  low="0"  high="8"  type="uint"/>
347
 
                        </reg32>
348
 
                </array>
349
 
                <!-- SSPP: -->
350
 
                <reg32 offset="0x000" name="SRC_SIZE" type="reg_wh"/>
351
 
                <reg32 offset="0x004" name="SRC_IMG_SIZE" type="reg_wh"/>
352
 
                <reg32 offset="0x008" name="SRC_XY" type="reg_xy"/>
353
 
                <reg32 offset="0x00C" name="OUT_SIZE" type="reg_wh"/>
354
 
                <reg32 offset="0x010" name="OUT_XY" type="reg_xy"/>
355
 
                <reg32 offset="0x014" name="SRC0_ADDR"/>
356
 
                <reg32 offset="0x018" name="SRC1_ADDR"/>
357
 
                <reg32 offset="0x01C" name="SRC2_ADDR"/>
358
 
                <reg32 offset="0x020" name="SRC3_ADDR"/>
359
 
                <reg32 offset="0x024" name="SRC_STRIDE_A">
360
 
                        <bitfield name="P0" low="0" high="15" type="uint"/>
361
 
                        <bitfield name="P1" low="16" high="31" type="uint"/>
362
 
                </reg32>
363
 
                <reg32 offset="0x028" name="SRC_STRIDE_B">
364
 
                        <bitfield name="P2" low="0" high="15" type="uint"/>
365
 
                        <bitfield name="P3" low="16" high="31" type="uint"/>
366
 
                </reg32>
367
 
                <reg32 offset="0x02C" name="STILE_FRAME_SIZE"/>
368
 
                <reg32 offset="0x030" name="SRC_FORMAT">
369
 
                        <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
370
 
                        <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
371
 
                        <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
372
 
                        <bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/>
373
 
                        <bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/>
374
 
                        <bitfield name="CPP" low="9" high="10" type="uint">
375
 
                                <brief>8bit characters per pixel minus 1</brief>
376
 
                        </bitfield>
377
 
                        <bitfield name="ROT90" pos="11" type="boolean"/>
378
 
                        <bitfield name="UNPACK_COUNT" low="12" high="13" type="uint"/>
379
 
                        <bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/>
380
 
                        <bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/>
381
 
                        <bitfield name="FETCH_TYPE" low="19" high="20" type="mdp_fetch_type"/>
382
 
                        <bitfield name="CHROMA_SAMP" low="23" high="24" type="mdp_chroma_samp_type"/>
383
 
                </reg32>
384
 
                <reg32 offset="0x034" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
385
 
                <reg32 offset="0x038" name="SRC_OP_MODE">
386
 
                        <bitfield name="BWC_EN" pos="0" type="boolean"/>
387
 
                        <bitfield name="BWC" low="1" high="2" type="mdp5_pipe_bwc"/>
388
 
                        <bitfield name="FLIP_LR" pos="13" type="boolean"/>
389
 
                        <bitfield name="FLIP_UD" pos="14" type="boolean"/>
390
 
                        <bitfield name="IGC_EN" pos="16" type="boolean"/>
391
 
                        <bitfield name="IGC_ROM_0" pos="17" type="boolean"/>
392
 
                        <bitfield name="IGC_ROM_1" pos="18" type="boolean"/>
393
 
                        <bitfield name="DEINTERLACE" pos="22" type="boolean"/>
394
 
                        <bitfield name="DEINTERLACE_ODD" pos="23" type="boolean"/>
395
 
                        <bitfield name="SW_PIX_EXT_OVERRIDE" pos="31" type="boolean"/>
396
 
                </reg32>
397
 
                <reg32 offset="0x03c" name="SRC_CONSTANT_COLOR"/>
398
 
                <reg32 offset="0x048" name="FETCH_CONFIG"/>
399
 
                <reg32 offset="0x04c" name="VC1_RANGE"/>
400
 
                <reg32 offset="0x050" name="REQPRIO_FIFO_WM_0"/>
401
 
                <reg32 offset="0x054" name="REQPRIO_FIFO_WM_1"/>
402
 
                <reg32 offset="0x058" name="REQPRIO_FIFO_WM_2"/>
403
 
                <reg32 offset="0x070" name="SRC_ADDR_SW_STATUS"/>
404
 
                <reg32 offset="0x0a4" name="CURRENT_SRC0_ADDR"/>
405
 
                <reg32 offset="0x0a8" name="CURRENT_SRC1_ADDR"/>
406
 
                <reg32 offset="0x0ac" name="CURRENT_SRC2_ADDR"/>
407
 
                <reg32 offset="0x0b0" name="CURRENT_SRC3_ADDR"/>
408
 
                <reg32 offset="0x0b4" name="DECIMATION">
409
 
                        <bitfield name="VERT" low="0" high="7" type="uint"/>
410
 
                        <bitfield name="HORZ" low="8" high="15" type="uint"/>
411
 
                </reg32>
412
 
                <array offsets="0x100,0x110,0x120" name="SW_PIX_EXT" length="3" stride="0x10" index="mdp_component_type">
413
 
                        <!--
414
 
                                Notes:
415
 
                                o These value only take effect if SW_PIX_EXT_OVERRIDE is set in SRC_OP_MODE register
416
 
                                o For signed values (int): + indicates overfetch, - indicates line drop
417
 
                        -->
418
 
                        <reg32 offset="0x00" name="LR">
419
 
                                <bitfield name="LEFT_RPT" low="0" high="7" type="uint"/>
420
 
                                <bitfield name="LEFT_OVF" low="8" high="15" type="int"/>
421
 
                                <bitfield name="RIGHT_RPT" low="16" high="23" type="uint"/>
422
 
                                <bitfield name="RIGHT_OVF" low="24" high="31" type="int"/>
423
 
                        </reg32>
424
 
                        <reg32 offset="0x04" name="TB">
425
 
                                <bitfield name="TOP_RPT" low="0" high="7" type="uint"/>
426
 
                                <bitfield name="TOP_OVF" low="8" high="15" type="int"/>
427
 
                                <bitfield name="BOTTOM_RPT" low="16" high="23" type="uint"/>
428
 
                                <bitfield name="BOTTOM_OVF" low="24" high="31" type="int"/>
429
 
                        </reg32>
430
 
                        <reg32 offset="0x08" name="REQ_PIXELS">
431
 
                                <bitfield name="LEFT_RIGHT" low="0" high="15" type="uint"/>
432
 
                                <bitfield name="TOP_BOTTOM" low="16" high="31" type="uint"/>
433
 
                        </reg32>
434
 
                </array>
435
 
                <reg32 offset="0x204" name="SCALE_CONFIG">
436
 
                        <bitfield name="SCALEX_EN" pos="0" type="boolean"/>
437
 
                        <bitfield name="SCALEY_EN" pos="1" type="boolean"/>
438
 
                        <bitfield name="SCALEX_FILTER_COMP_0" low="8"  high="9"  type="mdp5_scale_filter"/>
439
 
                        <bitfield name="SCALEY_FILTER_COMP_0" low="10" high="11" type="mdp5_scale_filter"/>
440
 
                        <bitfield name="SCALEX_FILTER_COMP_1_2"  low="12" high="13" type="mdp5_scale_filter"/>
441
 
                        <bitfield name="SCALEY_FILTER_COMP_1_2"  low="14" high="15" type="mdp5_scale_filter"/>
442
 
                        <bitfield name="SCALEX_FILTER_COMP_3" low="16" high="17" type="mdp5_scale_filter"/>
443
 
                        <bitfield name="SCALEY_FILTER_COMP_3" low="18" high="19" type="mdp5_scale_filter"/>
444
 
                </reg32>
445
 
                <reg32 offset="0x210" name="SCALE_PHASE_STEP_X"/>
446
 
                <reg32 offset="0x214" name="SCALE_PHASE_STEP_Y"/>
447
 
                <reg32 offset="0x218" name="SCALE_CR_PHASE_STEP_X"/>
448
 
                <reg32 offset="0x21c" name="SCALE_CR_PHASE_STEP_Y"/>
449
 
                <reg32 offset="0x220" name="SCALE_INIT_PHASE_X"/>
450
 
                <reg32 offset="0x224" name="SCALE_INIT_PHASE_Y"/>
451
 
        </array>
452
 
 
453
 
        <array doffsets="mdp5_cfg->lm.base[0],mdp5_cfg->lm.base[1],mdp5_cfg->lm.base[2],mdp5_cfg->lm.base[3],mdp5_cfg->lm.base[4],mdp5_cfg->lm.base[5]" name="LM" length="6" stride="0x400">
454
 
                <reg32 offset="0x000" name="BLEND_COLOR_OUT">
455
 
                        <bitfield name="STAGE0_FG_ALPHA" pos="1" type="boolean"/>
456
 
                        <bitfield name="STAGE1_FG_ALPHA" pos="2" type="boolean"/>
457
 
                        <bitfield name="STAGE2_FG_ALPHA" pos="3" type="boolean"/>
458
 
                        <bitfield name="STAGE3_FG_ALPHA" pos="4" type="boolean"/>
459
 
                        <bitfield name="STAGE4_FG_ALPHA" pos="5" type="boolean"/>
460
 
                        <bitfield name="STAGE5_FG_ALPHA" pos="6" type="boolean"/>
461
 
                        <bitfield name="STAGE6_FG_ALPHA" pos="7" type="boolean"/>
462
 
                        <bitfield name="SPLIT_LEFT_RIGHT" pos="31" type="boolean"/>
463
 
                </reg32>
464
 
                <reg32 offset="0x004" name="OUT_SIZE" type="reg_wh"/>
465
 
                <reg32 offset="0x008" name="BORDER_COLOR_0"/>
466
 
                <reg32 offset="0x010" name="BORDER_COLOR_1"/>
467
 
                <array offsets="0x020,0x050,0x080,0x0B0,0x230,0x260,0x290" name="BLEND" length="7" stride="0x30">
468
 
                        <reg32 offset="0x00" name="OP_MODE">
469
 
                                <bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
470
 
                                <bitfield name="FG_INV_ALPHA"     pos="2"  type="boolean"/>
471
 
                                <bitfield name="FG_MOD_ALPHA"     pos="3"  type="boolean"/>
472
 
                                <bitfield name="FG_INV_MOD_ALPHA" pos="4"  type="boolean"/>
473
 
                                <bitfield name="FG_TRANSP_EN"     pos="5"  type="boolean"/>
474
 
                                <bitfield name="BG_ALPHA" low="8" high="9" type="mdp_alpha_type"/>
475
 
                                <bitfield name="BG_INV_ALPHA"     pos="10" type="boolean"/>
476
 
                                <bitfield name="BG_MOD_ALPHA"     pos="11" type="boolean"/>
477
 
                                <bitfield name="BG_INV_MOD_ALPHA" pos="12" type="boolean"/>
478
 
                                <bitfield name="BG_TRANSP_EN"     pos="13" type="boolean"/>
479
 
                        </reg32>
480
 
                        <reg32 offset="0x04" name="FG_ALPHA"/>
481
 
                        <reg32 offset="0x08" name="BG_ALPHA"/>
482
 
                        <reg32 offset="0x0c" name="FG_TRANSP_LOW0"/>
483
 
                        <reg32 offset="0x10" name="FG_TRANSP_LOW1"/>
484
 
                        <reg32 offset="0x14" name="FG_TRANSP_HIGH0"/>
485
 
                        <reg32 offset="0x18" name="FG_TRANSP_HIGH1"/>
486
 
                        <reg32 offset="0x1c" name="BG_TRANSP_LOW0"/>
487
 
                        <reg32 offset="0x20" name="BG_TRANSP_LOW1"/>
488
 
                        <reg32 offset="0x24" name="BG_TRANSP_HIGH0"/>
489
 
                        <reg32 offset="0x28" name="BG_TRANSP_HIGH1"/>
490
 
                </array>
491
 
                <reg32 offset="0x0e0" name="CURSOR_IMG_SIZE">
492
 
                        <bitfield name="SRC_W" low="0" high="15" type="uint"/>
493
 
                        <bitfield name="SRC_H" low="16" high="31" type="uint"/>
494
 
                </reg32>
495
 
                <reg32 offset="0x0e4" name="CURSOR_SIZE">
496
 
                        <bitfield name="ROI_W" low="0" high="15" type="uint"/>
497
 
                        <bitfield name="ROI_H" low="16" high="31" type="uint"/>
498
 
                </reg32>
499
 
                <reg32 offset="0x0e8" name="CURSOR_XY">
500
 
                        <bitfield name="SRC_X" low="0" high="15" type="uint"/>
501
 
                        <bitfield name="SRC_Y" low="16" high="31" type="uint"/>
502
 
                </reg32>
503
 
                <reg32 offset="0x0dc" name="CURSOR_STRIDE">
504
 
                        <bitfield name="STRIDE" low="0"  high="15"  type="uint"/>
505
 
                </reg32>
506
 
                <reg32 offset="0x0ec" name="CURSOR_FORMAT">
507
 
                        <bitfield name="FORMAT" low="0"  high="2"  type="mdp5_cursor_format"/>
508
 
                </reg32>
509
 
                <reg32 offset="0x0f0" name="CURSOR_BASE_ADDR"/>
510
 
                <reg32 offset="0x0f4" name="CURSOR_START_XY">
511
 
                        <bitfield name="X_START" low="0" high="15" type="uint"/>
512
 
                        <bitfield name="Y_START" low="16" high="31" type="uint"/>
513
 
                </reg32>
514
 
                <reg32 offset="0x0f8" name="CURSOR_BLEND_CONFIG">
515
 
                        <bitfield name="BLEND_EN" pos="0" type="boolean"/>
516
 
                        <bitfield name="BLEND_ALPHA_SEL" low="1"  high="2"  type="mdp5_cursor_alpha"/>
517
 
                        <bitfield name="BLEND_TRANSP_EN" pos="3" type="boolean"/>
518
 
                </reg32>
519
 
                <reg32 offset="0x0fc" name="CURSOR_BLEND_PARAM"/>
520
 
                <reg32 offset="0x100" name="CURSOR_BLEND_TRANSP_LOW0"/>
521
 
                <reg32 offset="0x104" name="CURSOR_BLEND_TRANSP_LOW1"/>
522
 
                <reg32 offset="0x108" name="CURSOR_BLEND_TRANSP_HIGH0"/>
523
 
                <reg32 offset="0x10c" name="CURSOR_BLEND_TRANSP_HIGH1"/>
524
 
                <reg32 offset="0x110" name="GC_LUT_BASE"/>
525
 
        </array>
526
 
 
527
 
        <array doffsets="mdp5_cfg->dspp.base[0],mdp5_cfg->dspp.base[1],mdp5_cfg->dspp.base[2],mdp5_cfg->dspp.base[3]" name="DSPP" length="4" stride="0x400">
528
 
                <reg32 offset="0x000" name="OP_MODE">
529
 
                        <bitfield name="IGC_LUT_EN" pos="0" type="boolean"/>
530
 
                        <bitfield name="IGC_TBL_IDX" low="1" high="3" type="uint"/>
531
 
                        <bitfield name="PCC_EN" pos="4" type="boolean"/>
532
 
                        <bitfield name="DITHER_EN" pos="8" type="boolean"/>
533
 
                        <bitfield name="HIST_EN" pos="16" type="boolean"/>
534
 
                        <bitfield name="AUTO_CLEAR" pos="17" type="boolean"/>
535
 
                        <bitfield name="HIST_LUT_EN" pos="19" type="boolean"/>
536
 
                        <bitfield name="PA_EN" pos="20" type="boolean"/>
537
 
                        <bitfield name="GAMUT_EN" pos="23" type="boolean"/>
538
 
                        <bitfield name="GAMUT_ORDER" pos="24" type="boolean"/>
539
 
                </reg32>
540
 
                <reg32 offset="0x030" name="PCC_BASE"/>
541
 
                <reg32 offset="0x150" name="DITHER_DEPTH"/>
542
 
                <reg32 offset="0x210" name="HIST_CTL_BASE"/>
543
 
                <reg32 offset="0x230" name="HIST_LUT_BASE"/>
544
 
                <reg32 offset="0x234" name="HIST_LUT_SWAP"/>
545
 
                <reg32 offset="0x238" name="PA_BASE"/>
546
 
                <reg32 offset="0x2dc" name="GAMUT_BASE"/>
547
 
                <reg32 offset="0x2b0" name="GC_BASE"/>
548
 
        </array>
549
 
 
550
 
        <array doffsets="mdp5_cfg->pp.base[0],mdp5_cfg->pp.base[1],mdp5_cfg->pp.base[2],mdp5_cfg->pp.base[3]" name="PP" length="4" stride="0x100">
551
 
                <reg32 offset="0x000" name="TEAR_CHECK_EN"/>
552
 
                <reg32 offset="0x004" name="SYNC_CONFIG_VSYNC">
553
 
                        <bitfield name="COUNT" low="0" high="18" type="uint"/>
554
 
                        <bitfield name="COUNTER_EN" pos="19" type="boolean"/>
555
 
                        <bitfield name="IN_EN" pos="20" type="boolean"/>
556
 
                </reg32>
557
 
                <reg32 offset="0x008" name="SYNC_CONFIG_HEIGHT"/>
558
 
                <reg32 offset="0x00c" name="SYNC_WRCOUNT">
559
 
                        <bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
560
 
                        <bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
561
 
                </reg32>
562
 
                <reg32 offset="0x010" name="VSYNC_INIT_VAL"/>
563
 
                <reg32 offset="0x014" name="INT_COUNT_VAL">
564
 
                        <bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
565
 
                        <bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
566
 
                </reg32>
567
 
                <reg32 offset="0x018" name="SYNC_THRESH">
568
 
                        <bitfield name="START" low="0" high="15" type="uint"/>
569
 
                        <bitfield name="CONTINUE" low="16" high="31" type="uint"/>
570
 
                </reg32>
571
 
                <reg32 offset="0x01c" name="START_POS"/>
572
 
                <reg32 offset="0x020" name="RD_PTR_IRQ"/>
573
 
                <reg32 offset="0x024" name="WR_PTR_IRQ"/>
574
 
                <reg32 offset="0x028" name="OUT_LINE_COUNT"/>
575
 
                <reg32 offset="0x02c" name="PP_LINE_COUNT"/>
576
 
                <reg32 offset="0x030" name="AUTOREFRESH_CONFIG"/>
577
 
                <reg32 offset="0x034" name="FBC_MODE"/>
578
 
                <reg32 offset="0x038" name="FBC_BUDGET_CTL"/>
579
 
                <reg32 offset="0x03c" name="FBC_LOSSY_MODE"/>
580
 
        </array>
581
 
 
582
 
        <enum name="mdp5_block_size">
583
 
                <value name="BLOCK_SIZE_64" value="0"/>
584
 
                <value name="BLOCK_SIZE_128" value="1"/>
585
 
        </enum>
586
 
 
587
 
        <enum name="mdp5_rotate_mode">
588
 
                <value name="ROTATE_0" value="0"/>
589
 
                <value name="ROTATE_90" value="1"/>
590
 
        </enum>
591
 
 
592
 
        <enum name="mdp5_chroma_downsample_method">
593
 
                <value name="DS_MTHD_NO_PIXEL_DROP" value="0"/>
594
 
                <value name="DS_MTHD_PIXEL_DROP" value="1"/>
595
 
        </enum>
596
 
 
597
 
        <array doffsets="mdp5_cfg->wb.base[0],mdp5_cfg->wb.base[1],mdp5_cfg->wb.base[2],mdp5_cfg->wb.base[3],,mdp5_cfg->wb.base[4]" name="WB" length="5" stride="0x400">
598
 
                <reg32 offset="0x000" name="DST_FORMAT">
599
 
                        <bitfield name="DSTC0_OUT" low="0" high="1" type="uint"/>
600
 
                        <bitfield name="DSTC1_OUT" low="2" high="3" type="uint"/>
601
 
                        <bitfield name="DSTC2_OUT" low="4" high="5" type="uint"/>
602
 
                        <bitfield name="DSTC3_OUT" low="6" high="7" type="uint"/>
603
 
                        <bitfield name="DSTC3_EN" pos="8" type="boolean"/>
604
 
                        <bitfield name="DST_BPP" low="9" high="10" type="uint"/>
605
 
                        <bitfield name="PACK_COUNT" low="12" high="13" type="uint"/>
606
 
                        <bitfield name="DST_ALPHA_X" pos="14" type="boolean"/>
607
 
                        <bitfield name="PACK_TIGHT" pos="17" type="boolean"/>
608
 
                        <bitfield name="PACK_ALIGN_MSB" pos="18" type="boolean"/>
609
 
                        <bitfield name="WRITE_PLANES" low="19" high="20" type="uint"/>
610
 
                        <bitfield name="DST_DITHER_EN" pos="22" type="boolean"/>
611
 
                        <bitfield name="DST_CHROMA_SAMP" low="23" high="25" type="uint"/>
612
 
                        <bitfield name="DST_CHROMA_SITE" low="26" high="29" type="uint"/>
613
 
                        <bitfield name="FRAME_FORMAT" low="30" high="31" type="uint"/>
614
 
                </reg32>
615
 
                <reg32 offset="0x004" name="DST_OP_MODE">
616
 
                        <bitfield name="BWC_ENC_EN" pos="0" type="boolean"/>
617
 
                        <bitfield name="BWC_ENC_OP" low="1" high="2" type="uint"/>
618
 
                        <bitfield name="BLOCK_SIZE" low="4" high="4" type="uint"/>
619
 
                        <bitfield name="ROT_MODE" low="5" high="5" type="uint"/>
620
 
                        <bitfield name="ROT_EN" pos="6" type="boolean"/>
621
 
                        <bitfield name="CSC_EN" pos="8" type="boolean"/>
622
 
                        <bitfield name="CSC_SRC_DATA_FORMAT" low="9" high="9" type="uint"/>
623
 
                        <bitfield name="CSC_DST_DATA_FORMAT" low="10" high="10" type="uint"/>
624
 
                        <bitfield name="CHROMA_DWN_SAMPLE_EN" pos="11" type="boolean"/>
625
 
                        <bitfield name="CHROMA_DWN_SAMPLE_FORMAT" low="12" high="12" type="uint"/>
626
 
                        <bitfield name="CHROMA_DWN_SAMPLE_H_MTHD" low="13" high="13" type="uint"/>
627
 
                        <bitfield name="CHROMA_DWN_SAMPLE_V_MTHD" low="14" high="14" type="uint"/>
628
 
                </reg32>
629
 
                <reg32 offset="0x008" name="DST_PACK_PATTERN">
630
 
                        <bitfield name="ELEMENT0" low="0" high="1" type="uint"/>
631
 
                        <bitfield name="ELEMENT1" low="8" high="9" type="uint"/>
632
 
                        <bitfield name="ELEMENT2" low="16" high="17" type="uint"/>
633
 
                        <bitfield name="ELEMENT3" low="24" high="25" type="uint"/>
634
 
                </reg32>
635
 
                <reg32 offset="0x00c" name="DST0_ADDR"/>
636
 
                <reg32 offset="0x010" name="DST1_ADDR"/>
637
 
                <reg32 offset="0x014" name="DST2_ADDR"/>
638
 
                <reg32 offset="0x018" name="DST3_ADDR"/>
639
 
                <reg32 offset="0x01c" name="DST_YSTRIDE0">
640
 
                        <bitfield name="DST0_YSTRIDE" low="0" high="15" type="uint"/>
641
 
                        <bitfield name="DST1_YSTRIDE" low="16" high="31" type="uint"/>
642
 
                </reg32>
643
 
                <reg32 offset="0x020" name="DST_YSTRIDE1">
644
 
                        <bitfield name="DST2_YSTRIDE" low="0" high="15" type="uint"/>
645
 
                        <bitfield name="DST3_YSTRIDE" low="16" high="31" type="uint"/>
646
 
                </reg32>
647
 
                <reg32 offset="0x024" name="DST_DITHER_BITDEPTH"/>
648
 
                <reg32 offset="0x030" name="DITHER_MATRIX_ROW0"/>
649
 
                <reg32 offset="0x034" name="DITHER_MATRIX_ROW1"/>
650
 
                <reg32 offset="0x038" name="DITHER_MATRIX_ROW2"/>
651
 
                <reg32 offset="0x03c" name="DITHER_MATRIX_ROW3"/>
652
 
                <reg32 offset="0x048" name="DST_WRITE_CONFIG"/>
653
 
                <reg32 offset="0x050" name="ROTATION_DNSCALER"/>
654
 
                <reg32 offset="0x060" name="N16_INIT_PHASE_X_0_3"/>
655
 
                <reg32 offset="0x064" name="N16_INIT_PHASE_X_1_2"/>
656
 
                <reg32 offset="0x068" name="N16_INIT_PHASE_Y_0_3"/>
657
 
                <reg32 offset="0x06c" name="N16_INIT_PHASE_Y_1_2"/>
658
 
                <reg32 offset="0x074" name="OUT_SIZE">
659
 
                        <bitfield name="DST_W" low="0" high="15" type="uint"/>
660
 
                        <bitfield name="DST_H" low="16" high="31" type="uint"/>
661
 
                </reg32>
662
 
                <reg32 offset="0x078" name="ALPHA_X_VALUE"/>
663
 
                <reg32 offset="0x260" name="CSC_MATRIX_COEFF_0">
664
 
                        <bitfield name="COEFF_11" low="0" high="12" type="uint"/>
665
 
                        <bitfield name="COEFF_12" low="16" high="28" type="uint"/>
666
 
                </reg32>
667
 
                <reg32 offset="0x264" name="CSC_MATRIX_COEFF_1">
668
 
                        <bitfield name="COEFF_13" low="0" high="12" type="uint"/>
669
 
                        <bitfield name="COEFF_21" low="16" high="28" type="uint"/>
670
 
                </reg32>
671
 
                <reg32 offset="0x268" name="CSC_MATRIX_COEFF_2">
672
 
                        <bitfield name="COEFF_22" low="0" high="12" type="uint"/>
673
 
                        <bitfield name="COEFF_23" low="16" high="28" type="uint"/>
674
 
                </reg32>
675
 
                <reg32 offset="0x26c" name="CSC_MATRIX_COEFF_3">
676
 
                        <bitfield name="COEFF_31" low="0" high="12" type="uint"/>
677
 
                        <bitfield name="COEFF_32" low="16" high="28" type="uint"/>
678
 
                </reg32>
679
 
                <reg32 offset="0x270" name="CSC_MATRIX_COEFF_4">
680
 
                        <bitfield name="COEFF_33" low="0" high="12" type="uint"/>
681
 
                </reg32>
682
 
                <array offset="0x274" name="CSC_COMP_PRECLAMP" length="3" stride="4">
683
 
                        <reg32 offset="0" name="REG">
684
 
                                <bitfield name="HIGH"  low="0"  high="7"  type="uint"/>
685
 
                                <bitfield name="LOW"  low="8"  high="15"  type="uint"/>
686
 
                        </reg32>
687
 
                </array>
688
 
                <array offset="0x280" name="CSC_COMP_POSTCLAMP" length="3" stride="4">
689
 
                        <reg32 offset="0" name="REG">
690
 
                                <bitfield name="HIGH"  low="0"  high="7"  type="uint"/>
691
 
                                <bitfield name="LOW"  low="8"  high="15"  type="uint"/>
692
 
                        </reg32>
693
 
                </array>
694
 
                <array offset="0x28c" name="CSC_COMP_PREBIAS" length="3" stride="4">
695
 
                        <reg32 offset="0" name="REG">
696
 
                                <bitfield name="VALUE"  low="0"  high="8"  type="uint"/>
697
 
                        </reg32>
698
 
                </array>
699
 
                <array offset="0x298" name="CSC_COMP_POSTBIAS" length="3" stride="4">
700
 
                        <reg32 offset="0" name="REG">
701
 
                                <bitfield name="VALUE"  low="0"  high="8"  type="uint"/>
702
 
                        </reg32>
703
 
                </array>
704
 
        </array>
705
 
 
706
 
        <array doffsets="mdp5_cfg->intf.base[0],mdp5_cfg->intf.base[1],mdp5_cfg->intf.base[2],mdp5_cfg->intf.base[3],mdp5_cfg->intf.base[4]" name="INTF" length="5" stride="0x200">
707
 
                <reg32 offset="0x000" name="TIMING_ENGINE_EN"/>
708
 
                <reg32 offset="0x004" name="CONFIG"/>
709
 
                <reg32 offset="0x008" name="HSYNC_CTL">
710
 
                        <bitfield name="PULSEW" low="0" high="15" type="uint"/>
711
 
                        <bitfield name="PERIOD" low="16" high="31" type="uint"/>
712
 
                </reg32>
713
 
                <reg32 offset="0x00c" name="VSYNC_PERIOD_F0" type="uint"/>
714
 
                <reg32 offset="0x010" name="VSYNC_PERIOD_F1" type="uint"/>
715
 
                <reg32 offset="0x014" name="VSYNC_LEN_F0" type="uint"/>
716
 
                <reg32 offset="0x018" name="VSYNC_LEN_F1" type="uint"/>
717
 
                <reg32 offset="0x01c" name="DISPLAY_VSTART_F0" type="uint"/>
718
 
                <reg32 offset="0x020" name="DISPLAY_VSTART_F1" type="uint"/>
719
 
                <reg32 offset="0x024" name="DISPLAY_VEND_F0" type="uint"/>
720
 
                <reg32 offset="0x028" name="DISPLAY_VEND_F1" type="uint"/>
721
 
                <reg32 offset="0x02c" name="ACTIVE_VSTART_F0">
722
 
                        <bitfield name="VAL" low="0" high="30" type="uint"/>
723
 
                        <bitfield name="ACTIVE_V_ENABLE" pos="31" type="boolean"/>
724
 
                </reg32>
725
 
                <reg32 offset="0x030" name="ACTIVE_VSTART_F1">
726
 
                        <bitfield name="VAL" low="0" high="30" type="uint"/>
727
 
                </reg32>
728
 
                <reg32 offset="0x034" name="ACTIVE_VEND_F0" type="uint"/>
729
 
                <reg32 offset="0x038" name="ACTIVE_VEND_F1" type="uint"/>
730
 
                <reg32 offset="0x03c" name="DISPLAY_HCTL">
731
 
                        <bitfield name="START" low="0"  high="15" type="uint"/>
732
 
                        <bitfield name="END"   low="16" high="31" type="uint"/>
733
 
                </reg32>
734
 
                <reg32 offset="0x040" name="ACTIVE_HCTL">
735
 
                        <bitfield name="START" low="0"  high="14" type="uint"/>
736
 
                        <bitfield name="END"   low="16" high="30" type="uint"/>
737
 
                        <bitfield name="ACTIVE_H_ENABLE" pos="31" type="boolean"/>
738
 
                </reg32>
739
 
                <reg32 offset="0x044" name="BORDER_COLOR"/>
740
 
                <reg32 offset="0x048" name="UNDERFLOW_COLOR"/>
741
 
                <reg32 offset="0x04c" name="HSYNC_SKEW"/>
742
 
                <reg32 offset="0x050" name="POLARITY_CTL">
743
 
                        <bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
744
 
                        <bitfield name="VSYNC_LOW" pos="1" type="boolean"/>
745
 
                        <bitfield name="DATA_EN_LOW" pos="2" type="boolean"/>
746
 
                </reg32>
747
 
                <reg32 offset="0x054" name="TEST_CTL"/>
748
 
                <reg32 offset="0x058" name="TP_COLOR0"/>
749
 
                <reg32 offset="0x05c" name="TP_COLOR1"/>
750
 
                <reg32 offset="0x084" name="DSI_CMD_MODE_TRIGGER_EN"/>
751
 
                <reg32 offset="0x090" name="PANEL_FORMAT" type="mdp5_format"/>
752
 
                <reg32 offset="0x0a8" name="FRAME_LINE_COUNT_EN"/>
753
 
                <reg32 offset="0x0ac" name="FRAME_COUNT"/>
754
 
                <reg32 offset="0x0b0" name="LINE_COUNT"/>
755
 
                <reg32 offset="0x0f0" name="DEFLICKER_CONFIG"/>
756
 
                <reg32 offset="0x0f4" name="DEFLICKER_STRNG_COEFF"/>
757
 
                <reg32 offset="0x0f8" name="DEFLICKER_WEAK_COEFF"/>
758
 
                <reg32 offset="0x100" name="TPG_ENABLE"/>
759
 
                <reg32 offset="0x104" name="TPG_MAIN_CONTROL"/>
760
 
                <reg32 offset="0x108" name="TPG_VIDEO_CONFIG"/>
761
 
                <reg32 offset="0x10c" name="TPG_COMPONENT_LIMITS"/>
762
 
                <reg32 offset="0x110" name="TPG_RECTANGLE"/>
763
 
                <reg32 offset="0x114" name="TPG_INITIAL_VALUE"/>
764
 
                <reg32 offset="0x118" name="TPG_BLK_WHITE_PATTERN_FRAME"/>
765
 
                <reg32 offset="0x11c" name="TPG_RGB_MAPPING"/>
766
 
        </array>
767
 
 
768
 
        <array doffsets="mdp5_cfg->ad.base[0],mdp5_cfg->ad.base[1]" name="AD" length="2" stride="0x200">
769
 
                <reg32 offset="0x000" name="BYPASS"/>
770
 
                <reg32 offset="0x004" name="CTRL_0"/>
771
 
                <reg32 offset="0x008" name="CTRL_1"/>
772
 
                <reg32 offset="0x00c" name="FRAME_SIZE"/>
773
 
                <reg32 offset="0x010" name="CON_CTRL_0"/>
774
 
                <reg32 offset="0x014" name="CON_CTRL_1"/>
775
 
                <reg32 offset="0x018" name="STR_MAN"/>
776
 
                <reg32 offset="0x01c" name="VAR"/>
777
 
                <reg32 offset="0x020" name="DITH"/>
778
 
                <reg32 offset="0x024" name="DITH_CTRL"/>
779
 
                <reg32 offset="0x028" name="AMP_LIM"/>
780
 
                <reg32 offset="0x02c" name="SLOPE"/>
781
 
                <reg32 offset="0x030" name="BW_LVL"/>
782
 
                <reg32 offset="0x034" name="LOGO_POS"/>
783
 
                <reg32 offset="0x038" name="LUT_FI"/>
784
 
                <reg32 offset="0x07c" name="LUT_CC"/>
785
 
                <reg32 offset="0x0c8" name="STR_LIM"/>
786
 
                <reg32 offset="0x0cc" name="CALIB_AB"/>
787
 
                <reg32 offset="0x0d0" name="CALIB_CD"/>
788
 
                <reg32 offset="0x0d4" name="MODE_SEL"/>
789
 
                <reg32 offset="0x0d8" name="TFILT_CTRL"/>
790
 
                <reg32 offset="0x0dc" name="BL_MINMAX"/>
791
 
                <reg32 offset="0x0e0" name="BL"/>
792
 
                <reg32 offset="0x0e8" name="BL_MAX"/>
793
 
                <reg32 offset="0x0ec" name="AL"/>
794
 
                <reg32 offset="0x0f0" name="AL_MIN"/>
795
 
                <reg32 offset="0x0f4" name="AL_FILT"/>
796
 
                <reg32 offset="0x0f8" name="CFG_BUF"/>
797
 
                <reg32 offset="0x100" name="LUT_AL"/>
798
 
                <reg32 offset="0x144" name="TARG_STR"/>
799
 
                <reg32 offset="0x148" name="START_CALC"/>
800
 
                <reg32 offset="0x14c" name="STR_OUT"/>
801
 
                <reg32 offset="0x154" name="BL_OUT"/>
802
 
                <reg32 offset="0x158" name="CALC_DONE"/>
803
 
        </array>
804
 
</domain>
805
 
 
806
 
</database>