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* Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* Rob Clark <robclark@freedesktop.org>
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#include "pipe/p_state.h"
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#include "util/format/u_format.h"
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#include "util/u_inlines.h"
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#include "util/u_memory.h"
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#include "util/u_string.h"
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#include "freedreno_draw.h"
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#include "freedreno_resource.h"
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#include "freedreno_state.h"
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#include "fd5_context.h"
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#include "fd5_format.h"
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#include "fd5_program.h"
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emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
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struct pipe_surface **bufs, const struct fd_gmem_stateobj *gmem)
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enum a5xx_tile_mode tile_mode;
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for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
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enum a5xx_color_fmt format = 0;
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enum a3xx_color_swap swap = WZYX;
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bool srgb = false, sint = false, uint = false;
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struct fd_resource *rsc = NULL;
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tile_mode = TILE5_LINEAR;
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if ((i < nr_bufs) && bufs[i]) {
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struct pipe_surface *psurf = bufs[i];
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enum pipe_format pformat = psurf->format;
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rsc = fd_resource(psurf->texture);
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format = fd5_pipe2color(pformat);
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swap = fd5_pipe2swap(pformat);
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srgb = util_format_is_srgb(pformat);
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sint = util_format_is_pure_sint(pformat);
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uint = util_format_is_pure_uint(pformat);
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debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
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offset = fd_resource_offset(rsc, psurf->u.tex.level,
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psurf->u.tex.first_layer);
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stride = gmem->bin_w * gmem->cbuf_cpp[i];
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size = stride * gmem->bin_h;
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base = gmem->cbuf_base[i];
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stride = fd_resource_pitch(rsc, psurf->u.tex.level);
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size = fd_resource_layer_stride(rsc, psurf->u.tex.level);
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fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
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OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5);
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A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
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A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
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A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
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0x800) | /* XXX 0x1000 for RECTLIST clear, 0x0 for BLIT.. */
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COND(srgb, A5XX_RB_MRT_BUF_INFO_COLOR_SRGB));
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OUT_RING(ring, A5XX_RB_MRT_PITCH(stride));
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OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(size));
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if (gmem || (i >= nr_bufs) || !bufs[i]) {
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OUT_RING(ring, base); /* RB_MRT[i].BASE_LO */
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OUT_RING(ring, 0x00000000); /* RB_MRT[i].BASE_HI */
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OUT_RELOC(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
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OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
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OUT_RING(ring, A5XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
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COND(sint, A5XX_SP_FS_MRT_REG_COLOR_SINT) |
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COND(uint, A5XX_SP_FS_MRT_REG_COLOR_UINT) |
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COND(srgb, A5XX_SP_FS_MRT_REG_COLOR_SRGB));
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/* when we support UBWC, these would be the system memory
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OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4);
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OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
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OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
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OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_PITCH(0));
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OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
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emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
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const struct fd_gmem_stateobj *gmem)
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struct fd_resource *rsc = fd_resource(zsbuf->texture);
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enum a5xx_depth_format fmt = fd5_pipe2depth(zsbuf->format);
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uint32_t cpp = rsc->layout.cpp;
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stride = cpp * gmem->bin_w;
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size = stride * gmem->bin_h;
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stride = fd_resource_pitch(rsc, zsbuf->u.tex.level);
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size = fd_resource_layer_stride(rsc, zsbuf->u.tex.level);
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OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
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OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
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OUT_RING(ring, gmem->zsbuf_base[0]); /* RB_DEPTH_BUFFER_BASE_LO */
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
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OUT_RELOC(ring, rsc->bo,
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fd_resource_offset(rsc, zsbuf->u.tex.level, zsbuf->u.tex.first_layer),
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0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
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OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_PITCH(stride));
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OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
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OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
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OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
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OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
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OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
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OUT_RELOC(ring, rsc->lrz, 0x1000, 0, 0);
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OUT_RING(ring, A5XX_GRAS_LRZ_BUFFER_PITCH(rsc->lrz_pitch));
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OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2);
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OUT_RELOC(ring, rsc->lrz, 0, 0, 0);
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OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
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OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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stride = 1 * gmem->bin_w;
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size = stride * gmem->bin_h;
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stride = fd_resource_pitch(rsc->stencil, zsbuf->u.tex.level);
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size = fd_resource_layer_stride(rsc, zsbuf->u.tex.level);
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OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 5);
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OUT_RING(ring, A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
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OUT_RING(ring, gmem->zsbuf_base[1]); /* RB_STENCIL_BASE_LO */
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OUT_RING(ring, 0x00000000); /* RB_STENCIL_BASE_HI */
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OUT_RELOC(ring, rsc->stencil->bo,
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fd_resource_offset(rsc->stencil, zsbuf->u.tex.level, zsbuf->u.tex.first_layer),
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0, 0); /* RB_STENCIL_BASE_LO/HI */
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OUT_RING(ring, A5XX_RB_STENCIL_PITCH(stride));
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OUT_RING(ring, A5XX_RB_STENCIL_ARRAY_PITCH(size));
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OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
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OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
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OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
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OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE));
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
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OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
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OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE));
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OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
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OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
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OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
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OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
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emit_msaa(struct fd_ringbuffer *ring, uint32_t nr_samples)
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enum a3xx_msaa_samples samples = fd_msaa_samples(nr_samples);
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OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
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OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(samples));
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OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
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COND(samples == MSAA_ONE,
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A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
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OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
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OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
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A5XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
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COND(samples == MSAA_ONE, A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
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OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
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OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(samples));
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OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(samples) |
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COND(samples == MSAA_ONE,
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A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE));
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use_hw_binning(struct fd_batch *batch)
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const struct fd_gmem_stateobj *gmem = batch->gmem_state;
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if ((gmem->maxpw * gmem->maxph) > 32)
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if ((gmem->maxpw > 15) || (gmem->maxph > 15))
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return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
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(batch->num_draws > 0);
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patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
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for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
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struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
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*patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
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util_dynarray_clear(&batch->draw_patches);
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update_vsc_pipe(struct fd_batch *batch) assert_dt
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struct fd_context *ctx = batch->ctx;
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struct fd5_context *fd5_ctx = fd5_context(ctx);
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const struct fd_gmem_stateobj *gmem = batch->gmem_state;
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struct fd_ringbuffer *ring = batch->gmem;
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OUT_PKT4(ring, REG_A5XX_VSC_BIN_SIZE, 3);
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OUT_RING(ring, A5XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
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A5XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
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OUT_RELOC(ring, fd5_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
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OUT_PKT4(ring, REG_A5XX_UNKNOWN_0BC5, 2);
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OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC5 */
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OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC6 */
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OUT_PKT4(ring, REG_A5XX_VSC_PIPE_CONFIG_REG(0), 16);
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for (i = 0; i < 16; i++) {
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const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
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OUT_RING(ring, A5XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
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A5XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
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A5XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
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A5XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
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OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(0), 32);
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for (i = 0; i < 16; i++) {
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if (!ctx->vsc_pipe_bo[i]) {
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ctx->vsc_pipe_bo[i] = fd_bo_new(
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ctx->dev, 0x20000, 0, "vsc_pipe[%u]", i);
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OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0,
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0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
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OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(0), 16);
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for (i = 0; i < 16; i++) {
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OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) -
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32); /* VSC_PIPE_DATA_LENGTH[i] */
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emit_binning_pass(struct fd_batch *batch) assert_dt
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struct fd_ringbuffer *ring = batch->gmem;
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const struct fd_gmem_stateobj *gmem = batch->gmem_state;
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uint32_t x1 = gmem->minx;
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uint32_t y1 = gmem->miny;
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uint32_t x2 = gmem->minx + gmem->width - 1;
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uint32_t y2 = gmem->miny + gmem->height - 1;
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fd5_set_render_mode(batch->ctx, ring, BINNING);
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OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
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A5XX_RB_CNTL_WIDTH(gmem->bin_w) | A5XX_RB_CNTL_HEIGHT(gmem->bin_h));
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OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
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OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
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A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
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OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
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A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
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OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
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OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) | A5XX_RB_RESOLVE_CNTL_1_Y(y1));
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OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) | A5XX_RB_RESOLVE_CNTL_2_Y(y2));
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update_vsc_pipe(batch);
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OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
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OUT_RING(ring, A5XX_VPC_MODE_CNTL_BINNING_PASS);
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fd5_event_write(batch, ring, UNK_2C, false);
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OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
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OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) | A5XX_RB_WINDOW_OFFSET_Y(0));
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/* emit IB to binning drawcmds: */
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fd5_emit_ib(ring, batch->binning);
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fd5_event_write(batch, ring, UNK_2D, false);
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fd5_event_write(batch, ring, CACHE_FLUSH_TS, true);
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// TODO CP_COND_WRITE's for all the vsc buffers (check for overflow??)
381
OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
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/* before first tile */
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fd5_emit_tile_init(struct fd_batch *batch) assert_dt
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struct fd_ringbuffer *ring = batch->gmem;
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struct pipe_framebuffer_state *pfb = &batch->framebuffer;
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fd5_emit_restore(batch, ring);
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fd5_emit_ib(ring, batch->prologue);
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fd5_emit_lrz_flush(batch, ring);
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OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
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OUT_RING(ring, 0x00000080); /* GRAS_CL_CNTL */
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OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
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OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
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OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
408
OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
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OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
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/* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
413
OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
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OUT_RING(ring, 0x7c13c080); /* RB_CCU_CNTL */
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emit_zs(ring, pfb->zsbuf, batch->gmem_state);
417
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, batch->gmem_state);
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/* Enable stream output for the first pass (likely the binning). */
420
OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
423
if (use_hw_binning(batch)) {
424
emit_binning_pass(batch);
426
/* Disable stream output after binning, since each VS output should get
429
OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
430
OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
432
fd5_emit_lrz_flush(batch, ring);
433
patch_draws(batch, USE_VISIBILITY);
435
patch_draws(batch, IGNORE_VISIBILITY);
438
fd5_set_render_mode(batch->ctx, ring, GMEM);
440
/* XXX If we're in gmem mode but not doing HW binning, then after the first
441
* tile we should disable stream output (fd6_gmem.c doesn't do that either).
445
/* before mem2gmem */
447
fd5_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile) assert_dt
449
struct fd_context *ctx = batch->ctx;
450
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
451
struct fd5_context *fd5_ctx = fd5_context(ctx);
452
struct fd_ringbuffer *ring = batch->gmem;
454
uint32_t x1 = tile->xoff;
455
uint32_t y1 = tile->yoff;
456
uint32_t x2 = tile->xoff + tile->bin_w - 1;
457
uint32_t y2 = tile->yoff + tile->bin_h - 1;
459
OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
460
OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
461
A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
462
OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
463
A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
465
OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
466
OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) | A5XX_RB_RESOLVE_CNTL_1_Y(y1));
467
OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) | A5XX_RB_RESOLVE_CNTL_2_Y(y2));
469
if (use_hw_binning(batch)) {
470
const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
471
struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
473
OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
475
OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
478
OUT_PKT7(ring, CP_SET_BIN_DATA5, 5);
479
OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
480
CP_SET_BIN_DATA5_0_VSC_N(tile->n));
481
OUT_RELOC(ring, pipe_bo, 0, 0, 0); /* VSC_PIPE[p].DATA_ADDRESS */
482
OUT_RELOC(ring, fd5_ctx->vsc_size_mem, /* VSC_SIZE_ADDRESS + (p * 4) */
483
(tile->p * 4), 0, 0);
485
OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
489
OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
490
OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(x1) | A5XX_RB_WINDOW_OFFSET_Y(y1));
494
* transfer from system memory to gmem
498
emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
499
struct pipe_surface *psurf, enum a5xx_blit_buf buf)
501
struct fd_ringbuffer *ring = batch->gmem;
502
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
503
struct fd_resource *rsc = fd_resource(psurf->texture);
504
uint32_t stride, size;
506
debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
511
if ((buf == BLIT_ZS) || (buf == BLIT_S)) {
512
// XXX hack import via BLIT_MRT0 instead of BLIT_ZS, since I don't
513
// know otherwise how to go from linear in sysmem to tiled in gmem.
514
// possibly we want to flip this around gmem2mem and keep depth
515
// tiled in sysmem (and fixup sampler state to assume tiled).. this
516
// might be required for doing depth/stencil in bypass mode?
517
enum a5xx_color_fmt format =
518
fd5_pipe2color(fd_gmem_restore_format(rsc->b.b.format));
520
OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
522
A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
523
A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(rsc->layout.tile_mode) |
524
A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
525
OUT_RING(ring, A5XX_RB_MRT_PITCH(fd_resource_pitch(rsc, psurf->u.tex.level)));
526
OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_resource_layer_stride(rsc, psurf->u.tex.level)));
527
OUT_RELOC(ring, rsc->bo,
528
fd_resource_offset(rsc, psurf->u.tex.level, psurf->u.tex.first_layer),
529
0, 0); /* BASE_LO/HI */
534
stride = gmem->bin_w << fdl_cpp_shift(&rsc->layout);
535
size = stride * gmem->bin_h;
537
OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
538
OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
539
OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
540
OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
541
OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
543
OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
544
OUT_RING(ring, 0x00000000); /* RB_RESOLVE_CNTL_3 */
545
OUT_RING(ring, base); /* RB_BLIT_DST_LO */
546
OUT_RING(ring, 0x00000000); /* RB_BLIT_DST_HI */
547
OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(stride));
548
OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(size));
550
OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
551
OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
553
fd5_emit_blit(batch, ring);
557
fd5_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
559
struct fd_ringbuffer *ring = batch->gmem;
560
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
561
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
564
* setup mrt and zs with system memory base addresses:
567
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
568
// emit_zs(ring, pfb->zsbuf, NULL);
570
OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
571
OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) |
572
A5XX_RB_CNTL_HEIGHT(gmem->bin_h) | A5XX_RB_CNTL_BYPASS);
574
if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
576
for (i = 0; i < pfb->nr_cbufs; i++) {
579
if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
581
emit_mem2gmem_surf(batch, gmem->cbuf_base[i], pfb->cbufs[i],
586
if (fd_gmem_needs_restore(batch, tile,
587
FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
588
struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
590
if (!rsc->stencil || fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH))
591
emit_mem2gmem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf, BLIT_ZS);
592
if (rsc->stencil && fd_gmem_needs_restore(batch, tile, FD_BUFFER_STENCIL))
593
emit_mem2gmem_surf(batch, gmem->zsbuf_base[1], pfb->zsbuf, BLIT_S);
597
/* before IB to rendering cmds: */
599
fd5_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
601
struct fd_ringbuffer *ring = batch->gmem;
602
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
603
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
605
OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
607
A5XX_RB_CNTL_WIDTH(gmem->bin_w) | A5XX_RB_CNTL_HEIGHT(gmem->bin_h));
609
emit_zs(ring, pfb->zsbuf, gmem);
610
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem);
611
emit_msaa(ring, pfb->samples);
615
* transfer from gmem to system memory (ie. normal RAM)
619
emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
620
struct pipe_surface *psurf, enum a5xx_blit_buf buf)
622
struct fd_ringbuffer *ring = batch->gmem;
623
struct fd_resource *rsc = fd_resource(psurf->texture);
625
uint32_t offset, pitch;
634
fd_resource_offset(rsc, psurf->u.tex.level, psurf->u.tex.first_layer);
635
pitch = fd_resource_pitch(rsc, psurf->u.tex.level);
637
debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
639
OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
640
OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */
641
OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */
642
OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */
643
OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
645
tiled = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
647
OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
648
OUT_RING(ring, 0x00000004 | /* XXX RB_RESOLVE_CNTL_3 */
649
COND(tiled, A5XX_RB_RESOLVE_CNTL_3_TILED));
650
OUT_RELOC(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
651
OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(pitch));
652
OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(fd_resource_layer_stride(rsc, psurf->u.tex.level)));
654
OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
655
OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
657
// bool msaa_resolve = pfb->samples > 1;
658
bool msaa_resolve = false;
659
OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
660
OUT_RING(ring, COND(msaa_resolve, A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE));
662
fd5_emit_blit(batch, ring);
666
fd5_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
668
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
669
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
671
if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
672
struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
674
if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
675
emit_gmem2mem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf, BLIT_ZS);
676
if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
677
emit_gmem2mem_surf(batch, gmem->zsbuf_base[1], pfb->zsbuf, BLIT_S);
680
if (batch->resolve & FD_BUFFER_COLOR) {
682
for (i = 0; i < pfb->nr_cbufs; i++) {
685
if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
687
emit_gmem2mem_surf(batch, gmem->cbuf_base[i], pfb->cbufs[i],
694
fd5_emit_tile_fini(struct fd_batch *batch) assert_dt
696
struct fd_ringbuffer *ring = batch->gmem;
698
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
701
fd5_emit_lrz_flush(batch, ring);
703
fd5_cache_flush(batch, ring);
704
fd5_set_render_mode(batch->ctx, ring, BYPASS);
708
fd5_emit_sysmem_prep(struct fd_batch *batch) assert_dt
710
struct fd_ringbuffer *ring = batch->gmem;
712
fd5_emit_restore(batch, ring);
714
fd5_emit_lrz_flush(batch, ring);
717
fd5_emit_ib(ring, batch->prologue);
719
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
722
fd5_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
724
OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
725
OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
727
OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
728
OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
730
/* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
732
OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
733
OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
735
OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
736
OUT_RING(ring, A5XX_RB_CNTL_WIDTH(0) | A5XX_RB_CNTL_HEIGHT(0) |
737
A5XX_RB_CNTL_BYPASS);
739
/* remaining setup below here does not apply to blit/compute: */
743
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
745
OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
746
OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
747
A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
748
OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
749
A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
751
OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
752
OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) | A5XX_RB_RESOLVE_CNTL_1_Y(0));
753
OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(pfb->width - 1) |
754
A5XX_RB_RESOLVE_CNTL_2_Y(pfb->height - 1));
756
OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
757
OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) | A5XX_RB_WINDOW_OFFSET_Y(0));
759
/* Enable stream output, since there's no binning pass to put it in. */
760
OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
763
OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
766
patch_draws(batch, IGNORE_VISIBILITY);
768
emit_zs(ring, pfb->zsbuf, NULL);
769
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
770
emit_msaa(ring, pfb->samples);
774
fd5_emit_sysmem_fini(struct fd_batch *batch)
776
struct fd_ringbuffer *ring = batch->gmem;
778
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
781
fd5_emit_lrz_flush(batch, ring);
783
fd5_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
784
fd5_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
788
fd5_gmem_init(struct pipe_context *pctx) disable_thread_safety_analysis
790
struct fd_context *ctx = fd_context(pctx);
792
ctx->emit_tile_init = fd5_emit_tile_init;
793
ctx->emit_tile_prep = fd5_emit_tile_prep;
794
ctx->emit_tile_mem2gmem = fd5_emit_tile_mem2gmem;
795
ctx->emit_tile_renderprep = fd5_emit_tile_renderprep;
796
ctx->emit_tile_gmem2mem = fd5_emit_tile_gmem2mem;
797
ctx->emit_tile_fini = fd5_emit_tile_fini;
798
ctx->emit_sysmem_prep = fd5_emit_sysmem_prep;
799
ctx->emit_sysmem_fini = fd5_emit_sysmem_fini;
added
removed
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
