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Viewing changes to src/imagination/vulkan/pds/pvr_rogue_pds_encode.h

  • Committer: mmach
  • Date: 2022-09-22 19:56:13 UTC
  • Revision ID: netbit73@gmail.com-20220922195613-wtik9mmy20tmor0i
2022-09-22 21:17:09

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src/imagination/vulkan/pds/pvr_rogue_pds_encode.h
1
 
/*
2
 
 * Copyright © 2022 Imagination Technologies Ltd.
3
 
 *
4
 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
5
 
 * of this software and associated documentation files (the "Software"), to deal
6
 
 * in the Software without restriction, including without limitation the rights
7
 
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8
 
 * copies of the Software, and to permit persons to whom the Software is
9
 
 * furnished to do so, subject to the following conditions:
10
 
 *
11
 
 * The above copyright notice and this permission notice (including the next
12
 
 * paragraph) shall be included in all copies or substantial portions of the
13
 
 * Software.
14
 
 *
15
 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18
 
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
 
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20
 
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21
 
 * SOFTWARE.
22
 
 */
23
 
 
24
 
#ifndef PVR_ROGUE_PDS_ENCODE_H
25
 
#define PVR_ROGUE_PDS_ENCODE_H
26
 
 
27
 
#include <stdint.h>
28
 
 
29
 
#include "pvr_rogue_pds_defs.h"
30
 
#include "pvr_rogue_pds_disasm.h"
31
 
#include "util/macros.h"
32
 
 
33
 
static ALWAYS_INLINE uint32_t
34
 
pvr_pds_inst_decode_field_range_regs64tp(uint32_t value)
35
 
{
36
 
   if (value <= PVR_ROGUE_PDSINST_REGS64TP_TEMP64_UPPER)
37
 
      return PVR_ROGUE_PDSINST_REGS64TP_TEMP64;
38
 
 
39
 
   if ((value >= PVR_ROGUE_PDSINST_REGS64TP_PTEMP64_LOWER) &&
40
 
       (value <= PVR_ROGUE_PDSINST_REGS64TP_PTEMP64_UPPER)) {
41
 
      return PVR_ROGUE_PDSINST_REGS64TP_PTEMP64;
42
 
   }
43
 
   return 2;
44
 
}
45
 
 
46
 
static ALWAYS_INLINE uint32_t
47
 
pvr_pds_inst_decode_field_range_regs32(uint32_t value)
48
 
{
49
 
   if (value <= PVR_ROGUE_PDSINST_REGS32_CONST32_UPPER)
50
 
      return PVR_ROGUE_PDSINST_REGS32_CONST32;
51
 
 
52
 
   if ((value >= PVR_ROGUE_PDSINST_REGS32_TEMP32_LOWER) &&
53
 
       (value <= PVR_ROGUE_PDSINST_REGS32_TEMP32_UPPER)) {
54
 
      return PVR_ROGUE_PDSINST_REGS32_TEMP32;
55
 
   }
56
 
   if ((value >= PVR_ROGUE_PDSINST_REGS32_PTEMP32_LOWER) &&
57
 
       (value <= PVR_ROGUE_PDSINST_REGS32_PTEMP32_UPPER)) {
58
 
      return PVR_ROGUE_PDSINST_REGS32_PTEMP32;
59
 
   }
60
 
   return 3;
61
 
}
62
 
 
63
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_stflp64(uint32_t cc,
64
 
                                                          uint32_t lop,
65
 
                                                          uint32_t im,
66
 
                                                          uint32_t src0,
67
 
                                                          uint32_t src1,
68
 
                                                          uint32_t src2,
69
 
                                                          uint32_t dst)
70
 
{
71
 
   uint32_t encoded = 0;
72
 
 
73
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_SFTLP64
74
 
              << PVR_ROGUE_PDSINST_SFTLP64_OPCODE_SHIFT;
75
 
   encoded |= ((dst & PVR_ROGUE_PDSINST_REGS64TP_MASK)
76
 
               << PVR_ROGUE_PDSINST_SFTLP64_DST_SHIFT);
77
 
   encoded |= ((src2 & PVR_ROGUE_PDSINST_REGS32_MASK)
78
 
               << PVR_ROGUE_PDSINST_SFTLP64_SRC2_SHIFT);
79
 
   encoded |= ((src1 & PVR_ROGUE_PDSINST_REGS64TP_MASK)
80
 
               << PVR_ROGUE_PDSINST_SFTLP64_SRC1_SHIFT);
81
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS64TP_MASK)
82
 
               << PVR_ROGUE_PDSINST_SFTLP64_SRC0_SHIFT);
83
 
   encoded |= ((im & 1U) << PVR_ROGUE_PDSINST_SFTLP64_IM_SHIFT);
84
 
   encoded |= ((lop & PVR_ROGUE_PDSINST_LOP_MASK)
85
 
               << PVR_ROGUE_PDSINST_SFTLP64_LOP_SHIFT);
86
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_SFTLP64_CC_SHIFT);
87
 
 
88
 
   PVR_PDS_PRINT_INST(encoded);
89
 
 
90
 
   return encoded;
91
 
}
92
 
 
93
 
static ALWAYS_INLINE uint32_t
94
 
pvr_pds_inst_decode_field_range_regs32t(uint32_t value)
95
 
{
96
 
   if (value <= PVR_ROGUE_PDSINST_REGS32T_TEMP32_UPPER)
97
 
      return PVR_ROGUE_PDSINST_REGS32T_TEMP32;
98
 
 
99
 
   return 1;
100
 
}
101
 
 
102
 
static ALWAYS_INLINE uint32_t
103
 
pvr_pds_inst_decode_field_range_regs32tp(uint32_t value)
104
 
{
105
 
   if (value <= PVR_ROGUE_PDSINST_REGS32TP_TEMP32_UPPER)
106
 
      return PVR_ROGUE_PDSINST_REGS32TP_TEMP32;
107
 
 
108
 
   if ((value >= PVR_ROGUE_PDSINST_REGS32TP_PTEMP32_LOWER) &&
109
 
       (value <= PVR_ROGUE_PDSINST_REGS32TP_PTEMP32_UPPER)) {
110
 
      return PVR_ROGUE_PDSINST_REGS32TP_PTEMP32;
111
 
   }
112
 
   return 2;
113
 
}
114
 
 
115
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_stflp32(uint32_t im,
116
 
                                                          uint32_t cc,
117
 
                                                          uint32_t lop,
118
 
                                                          uint32_t src0,
119
 
                                                          uint32_t src1,
120
 
                                                          uint32_t src2,
121
 
                                                          uint32_t dst)
122
 
{
123
 
   uint32_t encoded = 0;
124
 
 
125
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEB_SFTLP32
126
 
              << PVR_ROGUE_PDSINST_SFTLP32_OPCODE_SHIFT;
127
 
   encoded |= ((dst & PVR_ROGUE_PDSINST_REGS32T_MASK)
128
 
               << PVR_ROGUE_PDSINST_SFTLP32_DST_SHIFT);
129
 
   encoded |= ((src2 & PVR_ROGUE_PDSINST_REGS32TP_MASK)
130
 
               << PVR_ROGUE_PDSINST_SFTLP32_SRC2_SHIFT);
131
 
   encoded |= ((src1 & PVR_ROGUE_PDSINST_REGS32_MASK)
132
 
               << PVR_ROGUE_PDSINST_SFTLP32_SRC1_SHIFT);
133
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS32T_MASK)
134
 
               << PVR_ROGUE_PDSINST_SFTLP32_SRC0_SHIFT);
135
 
   encoded |= ((lop & PVR_ROGUE_PDSINST_LOP_MASK)
136
 
               << PVR_ROGUE_PDSINST_SFTLP32_LOP_SHIFT);
137
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_SFTLP32_CC_SHIFT);
138
 
   encoded |= ((im & 1U) << PVR_ROGUE_PDSINST_SFTLP32_IM_SHIFT);
139
 
 
140
 
   PVR_PDS_PRINT_INST(encoded);
141
 
 
142
 
   return encoded;
143
 
}
144
 
 
145
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_stm(uint32_t CCS_CCS_GLOBAL,
146
 
                                                      uint32_t CCS_CCS_SO,
147
 
                                                      uint32_t CCS_CCS_CC,
148
 
                                                      uint32_t SO_TST,
149
 
                                                      uint32_t SO,
150
 
                                                      uint32_t SO_SRC0,
151
 
                                                      uint32_t SO_SRC1,
152
 
                                                      uint32_t SO_SRC2,
153
 
                                                      uint32_t SO_SRC3)
154
 
{
155
 
   uint32_t encoded = 0;
156
 
 
157
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEB_STM
158
 
              << PVR_ROGUE_PDSINST_STM_OPCODE_SHIFT;
159
 
   encoded |= ((SO_SRC3 & PVR_ROGUE_PDSINST_REGS64TP_MASK)
160
 
               << PVR_ROGUE_PDSINST_STM_SO_SRC3_SHIFT);
161
 
   encoded |= ((SO_SRC2 & PVR_ROGUE_PDSINST_REGS32_MASK)
162
 
               << PVR_ROGUE_PDSINST_STM_SO_SRC2_SHIFT);
163
 
   encoded |= ((SO_SRC1 & PVR_ROGUE_PDSINST_REGS64TP_MASK)
164
 
               << PVR_ROGUE_PDSINST_STM_SO_SRC1_SHIFT);
165
 
   encoded |= ((SO_SRC0 & PVR_ROGUE_PDSINST_REGS64TP_MASK)
166
 
               << PVR_ROGUE_PDSINST_STM_SO_SRC0_SHIFT);
167
 
   encoded |=
168
 
      ((SO & PVR_ROGUE_PDSINST_SO_MASK) << PVR_ROGUE_PDSINST_STM_SO_SHIFT);
169
 
   encoded |= ((SO_TST & 1U) << PVR_ROGUE_PDSINST_STM_SO_TST_SHIFT);
170
 
   encoded |= ((CCS_CCS_CC & 1U) << PVR_ROGUE_PDSINST_STM_CCS_CCS_CC_SHIFT);
171
 
   encoded |= ((CCS_CCS_SO & 1U) << PVR_ROGUE_PDSINST_STM_CCS_CCS_SO_SHIFT);
172
 
   encoded |=
173
 
      ((CCS_CCS_GLOBAL & 1U) << PVR_ROGUE_PDSINST_STM_CCS_CCS_GLOBAL_SHIFT);
174
 
 
175
 
   PVR_PDS_PRINT_INST(encoded);
176
 
 
177
 
   return encoded;
178
 
}
179
 
 
180
 
static ALWAYS_INLINE uint32_t
181
 
pvr_pds_inst_decode_field_range_regs64(uint32_t value)
182
 
{
183
 
   if (value <= PVR_ROGUE_PDSINST_REGS64_CONST64_UPPER)
184
 
      return PVR_ROGUE_PDSINST_REGS64_CONST64;
185
 
 
186
 
   if ((value >= PVR_ROGUE_PDSINST_REGS64_TEMP64_LOWER) &&
187
 
       (value <= PVR_ROGUE_PDSINST_REGS64_TEMP64_UPPER)) {
188
 
      return PVR_ROGUE_PDSINST_REGS64_TEMP64;
189
 
   }
190
 
   if ((value >= PVR_ROGUE_PDSINST_REGS64_PTEMP64_LOWER) &&
191
 
       (value <= PVR_ROGUE_PDSINST_REGS64_PTEMP64_UPPER)) {
192
 
      return PVR_ROGUE_PDSINST_REGS64_PTEMP64;
193
 
   }
194
 
   return 3;
195
 
}
196
 
 
197
 
static ALWAYS_INLINE uint32_t pvr_rogue_inst_encode_mad(uint32_t sna,
198
 
                                                        uint32_t alum,
199
 
                                                        uint32_t cc,
200
 
                                                        uint32_t src0,
201
 
                                                        uint32_t src1,
202
 
                                                        uint32_t src2,
203
 
                                                        uint32_t dst)
204
 
{
205
 
   uint32_t encoded = 0;
206
 
 
207
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEA_MAD
208
 
              << PVR_ROGUE_PDSINST_MAD_OPCODE_SHIFT;
209
 
   encoded |= ((dst & PVR_ROGUE_PDSINST_REGS64T_MASK)
210
 
               << PVR_ROGUE_PDSINST_MAD_DST_SHIFT);
211
 
   encoded |= ((src2 & PVR_ROGUE_PDSINST_REGS64_MASK)
212
 
               << PVR_ROGUE_PDSINST_MAD_SRC2_SHIFT);
213
 
   encoded |= ((src1 & PVR_ROGUE_PDSINST_REGS32_MASK)
214
 
               << PVR_ROGUE_PDSINST_MAD_SRC1_SHIFT);
215
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS32_MASK)
216
 
               << PVR_ROGUE_PDSINST_MAD_SRC0_SHIFT);
217
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_MAD_CC_SHIFT);
218
 
   encoded |= ((alum & 1U) << PVR_ROGUE_PDSINST_MAD_ALUM_SHIFT);
219
 
   encoded |= ((sna & 1U) << PVR_ROGUE_PDSINST_MAD_SNA_SHIFT);
220
 
 
221
 
   PVR_PDS_PRINT_INST(encoded);
222
 
 
223
 
   return encoded;
224
 
}
225
 
 
226
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_add64(uint32_t cc,
227
 
                                                        uint32_t alum,
228
 
                                                        uint32_t sna,
229
 
                                                        uint32_t src0,
230
 
                                                        uint32_t src1,
231
 
                                                        uint32_t dst)
232
 
{
233
 
   uint32_t encoded = 0;
234
 
 
235
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_ADD64
236
 
              << PVR_ROGUE_PDSINST_ADD64_OPCODE_SHIFT;
237
 
   encoded |= ((dst & PVR_ROGUE_PDSINST_REGS64TP_MASK)
238
 
               << PVR_ROGUE_PDSINST_ADD64_DST_SHIFT);
239
 
   encoded |= ((src1 & PVR_ROGUE_PDSINST_REGS64_MASK)
240
 
               << PVR_ROGUE_PDSINST_ADD64_SRC1_SHIFT);
241
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS64_MASK)
242
 
               << PVR_ROGUE_PDSINST_ADD64_SRC0_SHIFT);
243
 
   encoded |= ((sna & 1U) << PVR_ROGUE_PDSINST_ADD64_SNA_SHIFT);
244
 
   encoded |= ((alum & 1U) << PVR_ROGUE_PDSINST_ADD64_ALUM_SHIFT);
245
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_ADD64_CC_SHIFT);
246
 
 
247
 
   PVR_PDS_PRINT_INST(encoded);
248
 
 
249
 
   return encoded;
250
 
}
251
 
 
252
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_add32(uint32_t cc,
253
 
                                                        uint32_t alum,
254
 
                                                        uint32_t sna,
255
 
                                                        uint32_t src0,
256
 
                                                        uint32_t src1,
257
 
                                                        uint32_t dst)
258
 
{
259
 
   uint32_t encoded = 0;
260
 
 
261
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_ADD32
262
 
              << PVR_ROGUE_PDSINST_ADD32_OPCODE_SHIFT;
263
 
   encoded |= ((dst & PVR_ROGUE_PDSINST_REGS32TP_MASK)
264
 
               << PVR_ROGUE_PDSINST_ADD32_DST_SHIFT);
265
 
   encoded |= ((src1 & PVR_ROGUE_PDSINST_REGS32_MASK)
266
 
               << PVR_ROGUE_PDSINST_ADD32_SRC1_SHIFT);
267
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS32_MASK)
268
 
               << PVR_ROGUE_PDSINST_ADD32_SRC0_SHIFT);
269
 
   encoded |= ((sna & 1U) << PVR_ROGUE_PDSINST_ADD32_SNA_SHIFT);
270
 
   encoded |= ((alum & 1U) << PVR_ROGUE_PDSINST_ADD32_ALUM_SHIFT);
271
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_ADD32_CC_SHIFT);
272
 
 
273
 
   PVR_PDS_PRINT_INST(encoded);
274
 
 
275
 
   return encoded;
276
 
}
277
 
 
278
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_cmp(uint32_t cc,
279
 
                                                      uint32_t cop,
280
 
                                                      uint32_t src0,
281
 
                                                      uint32_t src1)
282
 
{
283
 
   uint32_t encoded = 0;
284
 
 
285
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_CMP
286
 
              << PVR_ROGUE_PDSINST_CMP_OPCODE_SHIFT;
287
 
   encoded |= ((src1 & PVR_ROGUE_PDSINST_REGS64_MASK)
288
 
               << PVR_ROGUE_PDSINST_CMP_SRC1_SHIFT);
289
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS64TP_MASK)
290
 
               << PVR_ROGUE_PDSINST_CMP_SRC0_SHIFT);
291
 
   encoded |= UINT32_C(0x0) << PVR_ROGUE_PDSINST_CMP_IM_SHIFT;
292
 
   encoded |= UINT32_C(0x1) << PVR_ROGUE_PDSINST_CMP_SETCP_SHIFT;
293
 
   encoded |=
294
 
      ((cop & PVR_ROGUE_PDSINST_COP_MASK) << PVR_ROGUE_PDSINST_CMP_COP_SHIFT);
295
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_CMP_CC_SHIFT);
296
 
 
297
 
   PVR_PDS_PRINT_INST(encoded);
298
 
 
299
 
   return encoded;
300
 
}
301
 
 
302
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_cmpi(uint32_t cc,
303
 
                                                       uint32_t cop,
304
 
                                                       uint32_t src0,
305
 
                                                       uint32_t im16)
306
 
{
307
 
   uint32_t encoded = 0;
308
 
 
309
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_CMP
310
 
              << PVR_ROGUE_PDSINST_CMPI_OPCODE_SHIFT;
311
 
   encoded |= ((im16 & PVR_ROGUE_PDSINST_IMM16_MASK)
312
 
               << PVR_ROGUE_PDSINST_CMPI_IM16_SHIFT);
313
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS64TP_MASK)
314
 
               << PVR_ROGUE_PDSINST_CMPI_SRC0_SHIFT);
315
 
   encoded |= UINT32_C(0x1) << PVR_ROGUE_PDSINST_CMPI_IM_SHIFT;
316
 
   encoded |= UINT32_C(0x1) << PVR_ROGUE_PDSINST_CMPI_SETCP_SHIFT;
317
 
   encoded |=
318
 
      ((cop & PVR_ROGUE_PDSINST_COP_MASK) << PVR_ROGUE_PDSINST_CMPI_COP_SHIFT);
319
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_CMPI_CC_SHIFT);
320
 
 
321
 
   PVR_PDS_PRINT_INST(encoded);
322
 
 
323
 
   return encoded;
324
 
}
325
 
 
326
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_bra(uint32_t srcc,
327
 
                                                      uint32_t neg,
328
 
                                                      uint32_t setc,
329
 
                                                      uint32_t addr)
330
 
{
331
 
   uint32_t encoded = 0;
332
 
 
333
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_BRA
334
 
              << PVR_ROGUE_PDSINST_BRA_OPCODE_SHIFT;
335
 
   encoded |= ((addr & PVR_ROGUE_PDSINST_BRAADDR_MASK)
336
 
               << PVR_ROGUE_PDSINST_BRA_ADDR_SHIFT);
337
 
   encoded |= ((setc & PVR_ROGUE_PDSINST_PREDICATE_MASK)
338
 
               << PVR_ROGUE_PDSINST_BRA_SETC_SHIFT);
339
 
   encoded |= ((neg & 1U) << PVR_ROGUE_PDSINST_BRA_NEG_SHIFT);
340
 
   encoded |= ((srcc & PVR_ROGUE_PDSINST_PREDICATE_MASK)
341
 
               << PVR_ROGUE_PDSINST_BRA_SRCC_SHIFT);
342
 
 
343
 
   PVR_PDS_PRINT_INST(encoded);
344
 
 
345
 
   return encoded;
346
 
}
347
 
 
348
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_ld(uint32_t cc, uint32_t src0)
349
 
{
350
 
   uint32_t encoded = 0;
351
 
 
352
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_SP << PVR_ROGUE_PDSINST_LD_OPCODE_SHIFT;
353
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS64_MASK)
354
 
               << PVR_ROGUE_PDSINST_LD_SRC0_SHIFT);
355
 
   encoded |= PVR_ROGUE_PDSINST_OPCODESP_LD << PVR_ROGUE_PDSINST_LD_OP_SHIFT;
356
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_LD_CC_SHIFT);
357
 
 
358
 
   PVR_PDS_PRINT_INST(encoded);
359
 
 
360
 
   return encoded;
361
 
}
362
 
 
363
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_st(uint32_t cc, uint32_t src0)
364
 
{
365
 
   uint32_t encoded = 0;
366
 
 
367
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_SP << PVR_ROGUE_PDSINST_ST_OPCODE_SHIFT;
368
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS64_MASK)
369
 
               << PVR_ROGUE_PDSINST_ST_SRC0_SHIFT);
370
 
   encoded |= PVR_ROGUE_PDSINST_OPCODESP_ST << PVR_ROGUE_PDSINST_ST_OP_SHIFT;
371
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_ST_CC_SHIFT);
372
 
 
373
 
   PVR_PDS_PRINT_INST(encoded);
374
 
 
375
 
   return encoded;
376
 
}
377
 
 
378
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_wdf(uint32_t cc)
379
 
{
380
 
   uint32_t encoded = 0;
381
 
 
382
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_SP
383
 
              << PVR_ROGUE_PDSINST_WDF_OPCODE_SHIFT;
384
 
   encoded |= PVR_ROGUE_PDSINST_OPCODESP_WDF << PVR_ROGUE_PDSINST_WDF_OP_SHIFT;
385
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_WDF_CC_SHIFT);
386
 
 
387
 
   PVR_PDS_PRINT_INST(encoded);
388
 
 
389
 
   return encoded;
390
 
}
391
 
 
392
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_limm(uint32_t cc,
393
 
                                                       uint32_t src1,
394
 
                                                       uint32_t src0,
395
 
                                                       uint32_t gr)
396
 
{
397
 
   uint32_t encoded = 0;
398
 
 
399
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_SP
400
 
              << PVR_ROGUE_PDSINST_LIMM_OPCODE_SHIFT;
401
 
   encoded |= ((gr & 1U) << PVR_ROGUE_PDSINST_LIMM_GR_SHIFT);
402
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_IMM16_MASK)
403
 
               << PVR_ROGUE_PDSINST_LIMM_SRC0_SHIFT);
404
 
   encoded |= ((src1 & PVR_ROGUE_PDSINST_REGS32T_MASK)
405
 
               << PVR_ROGUE_PDSINST_LIMM_SRC1_SHIFT);
406
 
   encoded |= PVR_ROGUE_PDSINST_OPCODESP_LIMM
407
 
              << PVR_ROGUE_PDSINST_LIMM_OP_SHIFT;
408
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_LIMM_CC_SHIFT);
409
 
 
410
 
   PVR_PDS_PRINT_INST(encoded);
411
 
 
412
 
   return encoded;
413
 
}
414
 
 
415
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_lock(uint32_t cc)
416
 
{
417
 
   uint32_t encoded = 0;
418
 
 
419
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_SP
420
 
              << PVR_ROGUE_PDSINST_LOCK_OPCODE_SHIFT;
421
 
   encoded |= PVR_ROGUE_PDSINST_OPCODESP_LOCK
422
 
              << PVR_ROGUE_PDSINST_LOCK_OP_SHIFT;
423
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_LOCK_CC_SHIFT);
424
 
 
425
 
   PVR_PDS_PRINT_INST(encoded);
426
 
 
427
 
   return encoded;
428
 
}
429
 
 
430
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_release(uint32_t cc)
431
 
{
432
 
   uint32_t encoded = 0;
433
 
 
434
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_SP
435
 
              << PVR_ROGUE_PDSINST_RELEASE_OPCODE_SHIFT;
436
 
   encoded |= PVR_ROGUE_PDSINST_OPCODESP_RELEASE
437
 
              << PVR_ROGUE_PDSINST_RELEASE_OP_SHIFT;
438
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_RELEASE_CC_SHIFT);
439
 
 
440
 
   PVR_PDS_PRINT_INST(encoded);
441
 
 
442
 
   return encoded;
443
 
}
444
 
 
445
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_halt(uint32_t cc)
446
 
{
447
 
   uint32_t encoded = 0;
448
 
 
449
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_SP
450
 
              << PVR_ROGUE_PDSINST_HALT_OPCODE_SHIFT;
451
 
   encoded |= PVR_ROGUE_PDSINST_OPCODESP_HALT
452
 
              << PVR_ROGUE_PDSINST_HALT_OP_SHIFT;
453
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_HALT_CC_SHIFT);
454
 
 
455
 
   PVR_PDS_PRINT_INST(encoded);
456
 
 
457
 
   return encoded;
458
 
}
459
 
 
460
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_stmc(uint32_t cc,
461
 
                                                       uint32_t so_mask)
462
 
{
463
 
   uint32_t encoded = 0;
464
 
 
465
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_SP
466
 
              << PVR_ROGUE_PDSINST_STMC_OPCODE_SHIFT;
467
 
   encoded |= ((so_mask & PVR_ROGUE_PDSINST_SOMASK_MASK)
468
 
               << PVR_ROGUE_PDSINST_STMC_SOMASK_SHIFT);
469
 
   encoded |= PVR_ROGUE_PDSINST_OPCODESP_STMC
470
 
              << PVR_ROGUE_PDSINST_STMC_OP_SHIFT;
471
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_STMC_CC_SHIFT);
472
 
 
473
 
   PVR_PDS_PRINT_INST(encoded);
474
 
 
475
 
   return encoded;
476
 
}
477
 
 
478
 
static ALWAYS_INLINE uint32_t
479
 
pvr_rogue_pds_inst_decode_field_range_regs64c(uint32_t value)
480
 
{
481
 
   if (value <= PVR_ROGUE_PDSINST_REGS64C_CONST64_UPPER)
482
 
      return PVR_ROGUE_PDSINST_REGS64C_CONST64;
483
 
 
484
 
   return 1;
485
 
}
486
 
 
487
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_ddmad(uint32_t cc,
488
 
                                                        uint32_t end,
489
 
                                                        uint32_t src0,
490
 
                                                        uint32_t src1,
491
 
                                                        uint32_t src2,
492
 
                                                        uint32_t src3)
493
 
{
494
 
   uint32_t encoded = 0;
495
 
 
496
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_DDMAD
497
 
              << PVR_ROGUE_PDSINST_DDMAD_OPCODE_SHIFT;
498
 
   encoded |= ((src3 & PVR_ROGUE_PDSINST_REGS64C_MASK)
499
 
               << PVR_ROGUE_PDSINST_DDMAD_SRC3_SHIFT);
500
 
   encoded |= ((src2 & PVR_ROGUE_PDSINST_REGS64_MASK)
501
 
               << PVR_ROGUE_PDSINST_DDMAD_SRC2_SHIFT);
502
 
   encoded |= ((src1 & PVR_ROGUE_PDSINST_REGS32T_MASK)
503
 
               << PVR_ROGUE_PDSINST_DDMAD_SRC1_SHIFT);
504
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS32_MASK)
505
 
               << PVR_ROGUE_PDSINST_DDMAD_SRC0_SHIFT);
506
 
   encoded |= ((end & 1U) << PVR_ROGUE_PDSINST_DDMAD_END_SHIFT);
507
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_DDMAD_CC_SHIFT);
508
 
 
509
 
   PVR_PDS_PRINT_INST(encoded);
510
 
 
511
 
   return encoded;
512
 
}
513
 
 
514
 
static ALWAYS_INLINE uint32_t pvr_pds_inst_encode_dout(uint32_t cc,
515
 
                                                       uint32_t end,
516
 
                                                       uint32_t src1,
517
 
                                                       uint32_t src0,
518
 
                                                       uint32_t dst)
519
 
{
520
 
   uint32_t encoded = 0;
521
 
 
522
 
   encoded |= PVR_ROGUE_PDSINST_OPCODEC_DOUT
523
 
              << PVR_ROGUE_PDSINST_DOUT_OPCODE_SHIFT;
524
 
   encoded |= ((dst & PVR_ROGUE_PDSINST_DSTDOUT_MASK)
525
 
               << PVR_ROGUE_PDSINST_DOUT_DST_SHIFT);
526
 
   encoded |= ((src0 & PVR_ROGUE_PDSINST_REGS64_MASK)
527
 
               << PVR_ROGUE_PDSINST_DOUT_SRC0_SHIFT);
528
 
   encoded |= ((src1 & PVR_ROGUE_PDSINST_REGS32_MASK)
529
 
               << PVR_ROGUE_PDSINST_DOUT_SRC1_SHIFT);
530
 
   encoded |= ((end & 1U) << PVR_ROGUE_PDSINST_DOUT_END_SHIFT);
531
 
   encoded |= ((cc & 1U) << PVR_ROGUE_PDSINST_DOUT_CC_SHIFT);
532
 
 
533
 
   PVR_PDS_PRINT_INST(encoded);
534
 
 
535
 
   return encoded;
536
 
}
537
 
 
538
 
#endif /* PVR_ROGUE_PDS_ENCODE_H */