2
* Copyright © 2017 Intel Corporation
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
* copy of this software and associated documentation files (the "Software"),
6
* to deal in the Software without restriction, including without limitation
7
* on the rights to use, copy, modify, merge, publish, distribute, sub
8
* license, and/or sell copies of the Software, and to permit persons to whom
9
* the Software is furnished to do so, subject to the following conditions:
11
* The above copyright notice and this permission notice (including the next
12
* paragraph) shall be included in all copies or substantial portions of the
15
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21
* USE OR OTHER DEALINGS IN THE SOFTWARE.
23
#ifndef IRIS_CONTEXT_H
24
#define IRIS_CONTEXT_H
26
#include "pipe/p_context.h"
27
#include "pipe/p_state.h"
28
#include "util/perf/u_trace.h"
30
#include "util/slab.h"
31
#include "util/u_debug.h"
32
#include "util/u_threaded_context.h"
33
#include "intel/blorp/blorp.h"
34
#include "intel/dev/intel_debug.h"
35
#include "intel/common/intel_l3_config.h"
36
#include "intel/compiler/brw_compiler.h"
37
#include "intel/ds/intel_driver_ds.h"
38
#include "iris_batch.h"
39
#include "iris_binder.h"
40
#include "iris_fence.h"
41
#include "iris_resource.h"
42
#include "iris_screen.h"
49
#define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
50
#define IRIS_MAX_TEXTURE_SAMPLERS 32
51
/* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
52
#define IRIS_MAX_ABOS 16
53
#define IRIS_MAX_SSBOS 16
54
#define IRIS_MAX_VIEWPORTS 16
55
#define IRIS_MAX_CLIP_PLANES 8
56
#define IRIS_MAX_GLOBAL_BINDINGS 32
58
enum iris_param_domain {
59
BRW_PARAM_DOMAIN_BUILTIN = 0,
60
BRW_PARAM_DOMAIN_IMAGE,
64
DRI_CONF_BO_REUSE_DISABLED,
68
#define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
69
#define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
70
#define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
71
#define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
72
#define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8)
73
#define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
76
* Dirty flags. When state changes, we flag some combination of these
77
* to indicate that particular GPU commands need to be re-emitted.
79
* Each bit typically corresponds to a single 3DSTATE_* command packet, but
80
* in rare cases they map to a group of related packets that need to be
83
* See iris_upload_render_state().
85
#define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0)
86
#define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1)
87
#define IRIS_DIRTY_SCISSOR_RECT (1ull << 2)
88
#define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3)
89
#define IRIS_DIRTY_CC_VIEWPORT (1ull << 4)
90
#define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5)
91
#define IRIS_DIRTY_PS_BLEND (1ull << 6)
92
#define IRIS_DIRTY_BLEND_STATE (1ull << 7)
93
#define IRIS_DIRTY_RASTER (1ull << 8)
94
#define IRIS_DIRTY_CLIP (1ull << 9)
95
#define IRIS_DIRTY_SBE (1ull << 10)
96
#define IRIS_DIRTY_LINE_STIPPLE (1ull << 11)
97
#define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12)
98
#define IRIS_DIRTY_MULTISAMPLE (1ull << 13)
99
#define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14)
100
#define IRIS_DIRTY_SAMPLE_MASK (1ull << 15)
101
#define IRIS_DIRTY_URB (1ull << 16)
102
#define IRIS_DIRTY_DEPTH_BUFFER (1ull << 17)
103
#define IRIS_DIRTY_WM (1ull << 18)
104
#define IRIS_DIRTY_SO_BUFFERS (1ull << 19)
105
#define IRIS_DIRTY_SO_DECL_LIST (1ull << 20)
106
#define IRIS_DIRTY_STREAMOUT (1ull << 21)
107
#define IRIS_DIRTY_VF_SGVS (1ull << 22)
108
#define IRIS_DIRTY_VF (1ull << 23)
109
#define IRIS_DIRTY_VF_TOPOLOGY (1ull << 24)
110
#define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 25)
111
#define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 26)
112
#define IRIS_DIRTY_VF_STATISTICS (1ull << 27)
113
#define IRIS_DIRTY_PMA_FIX (1ull << 28)
114
#define IRIS_DIRTY_DEPTH_BOUNDS (1ull << 29)
115
#define IRIS_DIRTY_RENDER_BUFFER (1ull << 30)
116
#define IRIS_DIRTY_STENCIL_REF (1ull << 31)
117
#define IRIS_DIRTY_VERTEX_BUFFER_FLUSHES (1ull << 32)
118
#define IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES (1ull << 33)
119
#define IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES (1ull << 34)
120
#define IRIS_DIRTY_VFG (1ull << 35)
122
#define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES | \
123
IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES)
125
#define IRIS_ALL_DIRTY_FOR_RENDER (~IRIS_ALL_DIRTY_FOR_COMPUTE)
128
* Per-stage dirty flags. When state changes, we flag some combination of
129
* these to indicate that particular GPU commands need to be re-emitted.
130
* Unlike the IRIS_DIRTY_* flags these are shader stage-specific and can be
131
* indexed by shifting the mask by the shader stage index.
133
* See iris_upload_render_state().
135
#define IRIS_STAGE_DIRTY_SAMPLER_STATES_VS (1ull << 0)
136
#define IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS (1ull << 1)
137
#define IRIS_STAGE_DIRTY_SAMPLER_STATES_TES (1ull << 2)
138
#define IRIS_STAGE_DIRTY_SAMPLER_STATES_GS (1ull << 3)
139
#define IRIS_STAGE_DIRTY_SAMPLER_STATES_PS (1ull << 4)
140
#define IRIS_STAGE_DIRTY_SAMPLER_STATES_CS (1ull << 5)
141
#define IRIS_STAGE_DIRTY_UNCOMPILED_VS (1ull << 6)
142
#define IRIS_STAGE_DIRTY_UNCOMPILED_TCS (1ull << 7)
143
#define IRIS_STAGE_DIRTY_UNCOMPILED_TES (1ull << 8)
144
#define IRIS_STAGE_DIRTY_UNCOMPILED_GS (1ull << 9)
145
#define IRIS_STAGE_DIRTY_UNCOMPILED_FS (1ull << 10)
146
#define IRIS_STAGE_DIRTY_UNCOMPILED_CS (1ull << 11)
147
#define IRIS_STAGE_DIRTY_VS (1ull << 12)
148
#define IRIS_STAGE_DIRTY_TCS (1ull << 13)
149
#define IRIS_STAGE_DIRTY_TES (1ull << 14)
150
#define IRIS_STAGE_DIRTY_GS (1ull << 15)
151
#define IRIS_STAGE_DIRTY_FS (1ull << 16)
152
#define IRIS_STAGE_DIRTY_CS (1ull << 17)
153
#define IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS 18
154
#define IRIS_STAGE_DIRTY_CONSTANTS_VS (1ull << 18)
155
#define IRIS_STAGE_DIRTY_CONSTANTS_TCS (1ull << 19)
156
#define IRIS_STAGE_DIRTY_CONSTANTS_TES (1ull << 20)
157
#define IRIS_STAGE_DIRTY_CONSTANTS_GS (1ull << 21)
158
#define IRIS_STAGE_DIRTY_CONSTANTS_FS (1ull << 22)
159
#define IRIS_STAGE_DIRTY_CONSTANTS_CS (1ull << 23)
160
#define IRIS_SHIFT_FOR_STAGE_DIRTY_BINDINGS 24
161
#define IRIS_STAGE_DIRTY_BINDINGS_VS (1ull << 24)
162
#define IRIS_STAGE_DIRTY_BINDINGS_TCS (1ull << 25)
163
#define IRIS_STAGE_DIRTY_BINDINGS_TES (1ull << 26)
164
#define IRIS_STAGE_DIRTY_BINDINGS_GS (1ull << 27)
165
#define IRIS_STAGE_DIRTY_BINDINGS_FS (1ull << 28)
166
#define IRIS_STAGE_DIRTY_BINDINGS_CS (1ull << 29)
168
#define IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE (IRIS_STAGE_DIRTY_CS | \
169
IRIS_STAGE_DIRTY_SAMPLER_STATES_CS | \
170
IRIS_STAGE_DIRTY_UNCOMPILED_CS | \
171
IRIS_STAGE_DIRTY_CONSTANTS_CS | \
172
IRIS_STAGE_DIRTY_BINDINGS_CS)
174
#define IRIS_ALL_STAGE_DIRTY_FOR_RENDER (~IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE)
176
#define IRIS_ALL_STAGE_DIRTY_BINDINGS_FOR_RENDER (IRIS_STAGE_DIRTY_BINDINGS_VS | \
177
IRIS_STAGE_DIRTY_BINDINGS_TCS | \
178
IRIS_STAGE_DIRTY_BINDINGS_TES | \
179
IRIS_STAGE_DIRTY_BINDINGS_GS | \
180
IRIS_STAGE_DIRTY_BINDINGS_FS)
182
#define IRIS_ALL_STAGE_DIRTY_BINDINGS (IRIS_ALL_STAGE_DIRTY_BINDINGS_FOR_RENDER | \
183
IRIS_STAGE_DIRTY_BINDINGS_CS)
186
* Non-orthogonal state (NOS) dependency flags.
188
* Shader programs may depend on non-orthogonal state. These flags are
189
* used to indicate that a shader's key depends on the state provided by
190
* a certain Gallium CSO. Changing any CSOs marked as a dependency will
191
* cause the driver to re-compute the shader key, possibly triggering a
195
IRIS_NOS_FRAMEBUFFER,
196
IRIS_NOS_DEPTH_STENCIL_ALPHA,
199
IRIS_NOS_LAST_VUE_MAP,
206
* Program cache keys for state based recompiles.
209
struct iris_base_prog_key {
210
unsigned program_string_id;
214
* Note, we need to take care to have padding explicitly declared
215
* for key since we will directly memcmp the whole struct.
217
struct iris_vue_prog_key {
218
struct iris_base_prog_key base;
220
unsigned nr_userclip_plane_consts:4;
224
struct iris_vs_prog_key {
225
struct iris_vue_prog_key vue;
228
struct iris_tcs_prog_key {
229
struct iris_vue_prog_key vue;
231
enum tess_primitive_mode _tes_primitive_mode;
233
uint8_t input_vertices;
235
bool quads_workaround;
237
/** A bitfield of per-patch outputs written. */
238
uint32_t patch_outputs_written;
240
/** A bitfield of per-vertex outputs written. */
241
uint64_t outputs_written;
244
struct iris_tes_prog_key {
245
struct iris_vue_prog_key vue;
247
/** A bitfield of per-patch inputs read. */
248
uint32_t patch_inputs_read;
250
/** A bitfield of per-vertex inputs read. */
251
uint64_t inputs_read;
254
struct iris_gs_prog_key {
255
struct iris_vue_prog_key vue;
258
struct iris_fs_prog_key {
259
struct iris_base_prog_key base;
261
unsigned nr_color_regions:5;
263
bool alpha_test_replicate_alpha:1;
264
bool alpha_to_coverage:1;
265
bool clamp_fragment_color:1;
266
bool persample_interp:1;
267
bool multisample_fbo:1;
268
bool force_dual_color_blend:1;
269
bool coherent_fb_fetch:1;
271
uint8_t color_outputs_valid;
272
uint64_t input_slots_valid;
275
struct iris_cs_prog_key {
276
struct iris_base_prog_key base;
279
union iris_any_prog_key {
280
struct iris_base_prog_key base;
281
struct iris_vue_prog_key vue;
282
struct iris_vs_prog_key vs;
283
struct iris_tcs_prog_key tcs;
284
struct iris_tes_prog_key tes;
285
struct iris_gs_prog_key gs;
286
struct iris_fs_prog_key fs;
287
struct iris_cs_prog_key cs;
292
struct iris_depth_stencil_alpha_state;
295
* Cache IDs for the in-memory program cache (ice->shaders.cache).
297
enum iris_program_cache_id {
298
IRIS_CACHE_VS = MESA_SHADER_VERTEX,
299
IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
300
IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
301
IRIS_CACHE_GS = MESA_SHADER_GEOMETRY,
302
IRIS_CACHE_FS = MESA_SHADER_FRAGMENT,
303
IRIS_CACHE_CS = MESA_SHADER_COMPUTE,
309
* Defines for PIPE_CONTROL operations, which trigger cache flushes,
310
* synchronization, pipelined memory writes, and so on.
312
* The bits here are not the actual hardware values. The actual fields
313
* move between various generations, so we just have flags for each
314
* potential operation, and use genxml to encode the actual packet.
316
enum pipe_control_flags
318
PIPE_CONTROL_FLUSH_LLC = (1 << 1),
319
PIPE_CONTROL_LRI_POST_SYNC_OP = (1 << 2),
320
PIPE_CONTROL_STORE_DATA_INDEX = (1 << 3),
321
PIPE_CONTROL_CS_STALL = (1 << 4),
322
PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET = (1 << 5),
323
PIPE_CONTROL_SYNC_GFDT = (1 << 6),
324
PIPE_CONTROL_TLB_INVALIDATE = (1 << 7),
325
PIPE_CONTROL_MEDIA_STATE_CLEAR = (1 << 8),
326
PIPE_CONTROL_WRITE_IMMEDIATE = (1 << 9),
327
PIPE_CONTROL_WRITE_DEPTH_COUNT = (1 << 10),
328
PIPE_CONTROL_WRITE_TIMESTAMP = (1 << 11),
329
PIPE_CONTROL_DEPTH_STALL = (1 << 12),
330
PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13),
331
PIPE_CONTROL_INSTRUCTION_INVALIDATE = (1 << 14),
332
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE = (1 << 15),
333
PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
334
PIPE_CONTROL_NOTIFY_ENABLE = (1 << 17),
335
PIPE_CONTROL_FLUSH_ENABLE = (1 << 18),
336
PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19),
337
PIPE_CONTROL_VF_CACHE_INVALIDATE = (1 << 20),
338
PIPE_CONTROL_CONST_CACHE_INVALIDATE = (1 << 21),
339
PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22),
340
PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23),
341
PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24),
342
PIPE_CONTROL_TILE_CACHE_FLUSH = (1 << 25),
343
PIPE_CONTROL_FLUSH_HDC = (1 << 26),
344
PIPE_CONTROL_PSS_STALL_SYNC = (1 << 27),
345
PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE = (1 << 28),
348
#define PIPE_CONTROL_CACHE_FLUSH_BITS \
349
(PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
350
PIPE_CONTROL_DATA_CACHE_FLUSH | \
351
PIPE_CONTROL_TILE_CACHE_FLUSH | \
352
PIPE_CONTROL_FLUSH_HDC | \
353
PIPE_CONTROL_RENDER_TARGET_FLUSH)
355
#define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
356
(PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
357
PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
358
PIPE_CONTROL_VF_CACHE_INVALIDATE | \
359
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
360
PIPE_CONTROL_INSTRUCTION_INVALIDATE)
362
#define PIPE_CONTROL_L3_RO_INVALIDATE_BITS \
363
(PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE | \
364
PIPE_CONTROL_CONST_CACHE_INVALIDATE)
366
enum iris_predicate_state {
367
/* The first two states are used if we can determine whether to draw
368
* without having to look at the values in the query object buffer. This
369
* will happen if there is no conditional render in progress, if the query
370
* object is already completed or if something else has already added
371
* samples to the preliminary result.
373
IRIS_PREDICATE_STATE_RENDER,
374
IRIS_PREDICATE_STATE_DONT_RENDER,
376
/* In this case whether to draw or not depends on the result of an
377
* MI_PREDICATE command so the predicate enable bit needs to be checked.
379
IRIS_PREDICATE_STATE_USE_BIT,
385
* An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
386
* It primarily contains the NIR for the shader.
388
* Each API-facing shader can be compiled into multiple shader variants,
389
* based on non-orthogonal state dependencies, recorded in the shader key.
391
* See iris_compiled_shader, which represents a compiled shader variant.
393
struct iris_uncompiled_shader {
394
struct pipe_reference ref;
397
* NIR for the shader.
399
* Even for shaders that originate as TGSI, this pointer will be non-NULL.
401
struct nir_shader *nir;
403
struct pipe_stream_output_info stream_output;
405
/* A SHA1 of the serialized NIR for the disk cache. */
406
unsigned char nir_sha1[20];
410
/** Bitfield of (1 << IRIS_NOS_*) flags. */
413
/** Have any shader variants been compiled yet? */
416
/* Whether shader uses atomic operations. */
417
bool uses_atomic_load_store;
419
/** Size (in bytes) of the kernel input data */
420
unsigned kernel_input_size;
422
/** Size (in bytes) of the local (shared) data passed as kernel inputs */
423
unsigned kernel_shared_size;
425
/** List of iris_compiled_shader variants */
426
struct list_head variants;
428
/** Lock for the variants list */
431
/** For parallel shader compiles */
432
struct util_queue_fence ready;
435
enum iris_surface_group {
436
IRIS_SURFACE_GROUP_RENDER_TARGET,
437
IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
438
IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
439
IRIS_SURFACE_GROUP_TEXTURE,
440
IRIS_SURFACE_GROUP_IMAGE,
441
IRIS_SURFACE_GROUP_UBO,
442
IRIS_SURFACE_GROUP_SSBO,
444
IRIS_SURFACE_GROUP_COUNT,
448
/* Invalid value for a binding table index. */
449
IRIS_SURFACE_NOT_USED = 0xa0a0a0a0,
452
struct iris_binding_table {
455
/** Number of surfaces in each group, before compacting. */
456
uint32_t sizes[IRIS_SURFACE_GROUP_COUNT];
458
/** Initial offset of each group. */
459
uint32_t offsets[IRIS_SURFACE_GROUP_COUNT];
461
/** Mask of surfaces used in each group. */
462
uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT];
466
* A compiled shader variant, containing a pointer to the GPU assembly,
467
* as well as program data and other packets needed by state upload.
469
* There can be several iris_compiled_shader variants per API-level shader
470
* (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
472
struct iris_compiled_shader {
473
struct pipe_reference ref;
475
/** Link in the iris_uncompiled_shader::variants list */
476
struct list_head link;
478
/** Key for this variant (but not for BLORP programs) */
479
union iris_any_prog_key key;
482
* Is the variant fully compiled and ready?
484
* Variants are added to \c iris_uncompiled_shader::variants before
485
* compilation actually occurs. This signals that compilation has
488
struct util_queue_fence ready;
490
/** Variant is ready, but compilation failed. */
491
bool compilation_failed;
493
/** Reference to the uploaded assembly. */
494
struct iris_state_ref assembly;
496
/** Pointer to the assembly in the BO's map. */
499
/** The program data (owned by the program cache hash table) */
500
struct brw_stage_prog_data *prog_data;
502
/** A list of system values to be uploaded as uniforms. */
503
enum brw_param_builtin *system_values;
504
unsigned num_system_values;
506
/** Size (in bytes) of the kernel input data */
507
unsigned kernel_input_size;
509
/** Number of constbufs expected by the shader. */
513
* Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
514
* (the VUE-based information for transform feedback outputs).
518
struct iris_binding_table bt;
521
* Shader packets and other data derived from prog_data. These must be
522
* completely determined from prog_data.
524
uint8_t derived_data[0];
528
* API context state that is replicated per shader stage.
530
struct iris_shader_state {
531
/** Uniform Buffers */
532
struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
533
struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
535
bool sysvals_need_upload;
537
/** Shader Storage Buffers */
538
struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
539
struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
541
/** Shader Storage Images (image load store) */
542
struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
544
struct iris_state_ref sampler_table;
545
struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
546
struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
548
/** Bitfield of which constant buffers are bound (non-null). */
549
uint32_t bound_cbufs;
550
uint32_t dirty_cbufs;
552
/** Bitfield of which image views are bound (non-null). */
553
uint32_t bound_image_views;
555
/** Bitfield of which sampler views are bound (non-null). */
556
uint32_t bound_sampler_views;
558
/** Bitfield of which shader storage buffers are bound (non-null). */
559
uint32_t bound_ssbos;
561
/** Bitfield of which shader storage buffers are writable. */
562
uint32_t writable_ssbos;
566
* Gallium CSO for stream output (transform feedback) targets.
568
struct iris_stream_output_target {
569
struct pipe_stream_output_target base;
571
/** Storage holding the offset where we're writing in the buffer */
572
struct iris_state_ref offset;
574
/** Stride (bytes-per-vertex) during this transform feedback operation */
577
/** Does the next 3DSTATE_SO_BUFFER need to zero the offsets? */
582
* The API context (derived from pipe_context).
584
* Most driver state is tracked here.
586
struct iris_context {
587
struct pipe_context ctx;
588
struct threaded_context *thrctx;
590
/** A debug callback for KHR_debug output. */
591
struct util_debug_callback dbg;
593
/** A device reset status callback for notifying that the GPU is hosed. */
594
struct pipe_device_reset_callback reset;
596
/** A set of dmabuf resources dirtied beyond their default aux-states. */
597
struct set *dirty_dmabufs;
599
/** Slab allocator for iris_transfer_map objects. */
600
struct slab_child_pool transfer_pool;
602
/** Slab allocator for threaded_context's iris_transfer_map objects */
603
struct slab_child_pool transfer_pool_unsync;
605
struct blorp_context blorp;
607
struct iris_batch batches[IRIS_BATCH_COUNT];
609
struct u_upload_mgr *query_buffer_uploader;
611
struct intel_ds_device ds;
616
* Either the value of BaseVertex for indexed draw calls or the value
617
* of the argument <first> for non-indexed draw calls.
624
* Are the above values the ones stored in the draw_params buffer?
625
* If so, we can compare them against new values to see if anything
626
* changed. If not, we need to assume they changed.
631
* Resource and offset that stores draw_parameters from the indirect
632
* buffer or to the buffer that stures the previous values for non
635
struct iris_state_ref draw_params;
639
* The value of DrawID. This always comes in from it's own vertex
640
* buffer since it's not part of the indirect draw parameters.
645
* Stores if an indexed or non-indexed draw (~0/0). Useful to
646
* calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
652
* Resource and offset used for GL_ARB_shader_draw_parameters which
653
* contains parameters that are not present in the indirect buffer as
654
* drawid and is_indexed_draw. They will go in their own vertex element.
656
struct iris_state_ref derived_draw_params;
660
struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
661
struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
662
struct iris_compiled_shader *last_vue_shader;
670
/** Uploader for shader assembly from the driver thread */
671
struct u_upload_mgr *uploader_driver;
672
/** Uploader for shader assembly from the threaded context */
673
struct u_upload_mgr *uploader_unsync;
674
struct hash_table *cache;
676
/** Is a GS or TES outputting points or lines? */
677
bool output_topology_is_points_or_lines;
680
* Scratch buffers for various sizes and stages.
682
* Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
685
struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
688
* Scratch buffer surface states on Gfx12.5+
690
struct iris_state_ref scratch_surfs[1 << 4];
693
struct intel_perf_context *perf_ctx;
695
/** Frame number for debug prints */
700
uint64_t stage_dirty;
701
uint64_t stage_dirty_for_nos[IRIS_NOS_COUNT];
703
unsigned num_viewports;
704
unsigned sample_mask;
705
struct iris_blend_state *cso_blend;
706
struct iris_rasterizer_state *cso_rast;
707
struct iris_depth_stencil_alpha_state *cso_zsa;
708
struct iris_vertex_element_state *cso_vertex_elements;
709
struct pipe_blend_color blend_color;
710
struct pipe_poly_stipple poly_stipple;
711
struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
712
struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
713
struct pipe_stencil_ref stencil_ref;
714
struct pipe_framebuffer_state framebuffer;
715
struct pipe_clip_state clip_planes;
717
float default_outer_level[4];
718
float default_inner_level[2];
720
/** Bitfield of which vertex buffers are bound (non-null). */
721
uint64_t bound_vertex_buffers;
723
uint8_t patch_vertices;
724
bool primitive_restart;
726
enum pipe_prim_type prim_mode:8;
727
bool prim_is_points_or_lines;
728
uint8_t vertices_per_patch;
730
bool window_space_position;
732
/** The last compute group size */
733
uint32_t last_block[3];
735
/** The last compute grid size */
736
uint32_t last_grid[3];
737
/** Reference to the BO containing the compute grid size */
738
struct iris_state_ref grid_size;
739
/** Reference to the SURFACE_STATE for the compute grid resource */
740
struct iris_state_ref grid_surf_state;
743
* Array of aux usages for drawing, altered to account for any
744
* self-dependencies from resources bound for sampling and rendering.
746
enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
748
/** Aux usage of the fb's depth buffer (which may or may not exist). */
749
enum isl_aux_usage hiz_usage;
751
enum intel_urb_deref_block_size urb_deref_block_size;
753
/** Are depth writes enabled? (Depth buffer may or may not exist.) */
754
bool depth_writes_enabled;
756
/** Are stencil writes enabled? (Stencil buffer may or may not exist.) */
757
bool stencil_writes_enabled;
759
/** GenX-specific current state */
760
struct iris_genx_state *genx;
762
struct iris_shader_state shaders[MESA_SHADER_STAGES];
764
/** Do vertex shader uses shader draw parameters ? */
765
bool vs_uses_draw_params;
766
bool vs_uses_derived_draw_params;
767
bool vs_needs_sgvs_element;
769
/** Do vertex shader uses edge flag ? */
770
bool vs_needs_edge_flag;
772
/** Do any samplers need border color? One bit per shader stage. */
773
uint8_t need_border_colors;
775
/** Global resource bindings */
776
struct pipe_resource *global_bindings[IRIS_MAX_GLOBAL_BINDINGS];
778
struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
779
bool streamout_active;
781
bool statistics_counters_enabled;
783
/** Current conditional rendering mode */
784
enum iris_predicate_state predicate;
787
* Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
788
* render context that needs to be uploaded to the compute context.
790
struct iris_bo *compute_predicate;
792
/** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
793
bool prims_generated_query_active;
795
/** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
798
/** The SURFACE_STATE for a 1x1x1 null surface. */
799
struct iris_state_ref unbound_tex;
801
/** The SURFACE_STATE for a framebuffer-sized null surface. */
802
struct iris_state_ref null_fb;
804
struct u_upload_mgr *surface_uploader;
805
struct u_upload_mgr *bindless_uploader;
806
struct u_upload_mgr *dynamic_uploader;
808
struct iris_binder binder;
810
/** The high 16-bits of the last VBO/index buffer addresses */
811
uint16_t last_vbo_high_bits[33];
812
uint16_t last_index_bo_high_bits;
815
* Resources containing streamed state which our render context
816
* currently points to. Used to re-add these to the validation
817
* list when we start a new batch and haven't resubmitted commands.
820
struct pipe_resource *cc_vp;
821
struct pipe_resource *sf_cl_vp;
822
struct pipe_resource *color_calc;
823
struct pipe_resource *scissor;
824
struct pipe_resource *blend;
825
struct pipe_resource *index_buffer;
826
struct pipe_resource *cs_thread_ids;
827
struct pipe_resource *cs_desc;
830
/** Records the size of variable-length state for INTEL_DEBUG=bat */
831
struct hash_table_u64 *sizes;
833
/** Last rendering scale argument provided to genX(emit_hashing_mode). */
834
unsigned current_hash_scale;
836
/** Resource holding the pixel pipe hashing tables. */
837
struct pipe_resource *pixel_hashing_tables;
841
#define perf_debug(dbg, ...) do { \
842
if (INTEL_DEBUG(DEBUG_PERF)) \
843
dbg_printf(__VA_ARGS__); \
845
util_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
848
struct pipe_context *
849
iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
850
void iris_destroy_context(struct pipe_context *ctx);
852
void iris_lost_context_state(struct iris_batch *batch);
854
void iris_mark_dirty_dmabuf(struct iris_context *ice,
855
struct pipe_resource *res);
856
void iris_flush_dirty_dmabufs(struct iris_context *ice);
858
void iris_init_blit_functions(struct pipe_context *ctx);
859
void iris_init_clear_functions(struct pipe_context *ctx);
860
void iris_init_program_functions(struct pipe_context *ctx);
861
void iris_init_screen_program_functions(struct pipe_screen *pscreen);
862
void iris_init_resource_functions(struct pipe_context *ctx);
863
void iris_init_perfquery_functions(struct pipe_context *ctx);
864
void iris_update_compiled_shaders(struct iris_context *ice);
865
void iris_update_compiled_compute_shader(struct iris_context *ice);
866
void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
872
void iris_blorp_surf_for_resource(struct isl_device *isl_dev,
873
struct blorp_surf *surf,
874
struct pipe_resource *p_res,
875
enum isl_aux_usage aux_usage,
877
bool is_render_target);
878
void iris_copy_region(struct blorp_context *blorp,
879
struct iris_batch *batch,
880
struct pipe_resource *dst,
882
unsigned dstx, unsigned dsty, unsigned dstz,
883
struct pipe_resource *src,
885
const struct pipe_box *src_box);
887
static inline enum blorp_batch_flags
888
iris_blorp_flags_for_batch(struct iris_batch *batch)
890
if (batch->name == IRIS_BATCH_COMPUTE)
891
return BLORP_BATCH_USE_COMPUTE;
893
if (batch->name == IRIS_BATCH_BLITTER)
894
return BLORP_BATCH_USE_BLITTER;
901
void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,
902
unsigned drawid_offset,
903
const struct pipe_draw_indirect_info *indirect,
904
const struct pipe_draw_start_count_bias *draws,
906
void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
908
/* iris_pipe_control.c */
910
void iris_emit_pipe_control_flush(struct iris_batch *batch,
911
const char *reason, uint32_t flags);
912
void iris_emit_pipe_control_write(struct iris_batch *batch,
913
const char *reason, uint32_t flags,
914
struct iris_bo *bo, uint32_t offset,
916
void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
917
const char *reason, uint32_t flags);
918
void iris_emit_buffer_barrier_for(struct iris_batch *batch,
920
enum iris_domain access);
921
void iris_flush_all_caches(struct iris_batch *batch);
923
#define iris_handle_always_flush_cache(batch) \
924
if (unlikely(batch->screen->driconf.always_flush_cache)) \
925
iris_flush_all_caches(batch);
927
void iris_init_flush_functions(struct pipe_context *ctx);
930
void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
931
struct pipe_shader_buffer *buf,
932
struct iris_state_ref *surf_state,
933
isl_surf_usage_flags_t usage);
934
const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
935
gl_shader_stage stage);
936
struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
937
unsigned per_thread_scratch,
938
gl_shader_stage stage);
939
const struct iris_state_ref *iris_get_scratch_surf(struct iris_context *ice,
940
unsigned per_thread_scratch);
941
uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt,
942
enum iris_surface_group group,
944
uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt,
945
enum iris_surface_group group,
948
/* iris_disk_cache.c */
950
void iris_disk_cache_store(struct disk_cache *cache,
951
const struct iris_uncompiled_shader *ish,
952
const struct iris_compiled_shader *shader,
953
const void *prog_key,
954
uint32_t prog_key_size);
956
iris_disk_cache_retrieve(struct iris_screen *screen,
957
struct u_upload_mgr *uploader,
958
struct iris_uncompiled_shader *ish,
959
struct iris_compiled_shader *shader,
960
const void *prog_key,
961
uint32_t prog_key_size);
963
/* iris_program_cache.c */
965
void iris_init_program_cache(struct iris_context *ice);
966
void iris_destroy_program_cache(struct iris_context *ice);
967
struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
968
enum iris_program_cache_id,
972
struct iris_compiled_shader *iris_create_shader_variant(const struct iris_screen *,
974
enum iris_program_cache_id cache_id,
978
void iris_finalize_program(struct iris_compiled_shader *shader,
979
struct brw_stage_prog_data *prog_data,
981
enum brw_param_builtin *system_values,
982
unsigned num_system_values,
983
unsigned kernel_input_size,
985
const struct iris_binding_table *bt);
987
void iris_upload_shader(struct iris_screen *screen,
988
struct iris_uncompiled_shader *,
989
struct iris_compiled_shader *,
990
struct hash_table *driver_ht,
991
struct u_upload_mgr *uploader,
992
enum iris_program_cache_id,
995
const void *assembly);
996
void iris_delete_shader_variant(struct iris_compiled_shader *shader);
998
void iris_destroy_shader_state(struct pipe_context *ctx, void *state);
1001
iris_uncompiled_shader_reference(struct pipe_context *ctx,
1002
struct iris_uncompiled_shader **dst,
1003
struct iris_uncompiled_shader *src)
1008
struct iris_uncompiled_shader *old_dst = *dst;
1010
if (pipe_reference(old_dst != NULL ? &old_dst->ref : NULL,
1011
src != NULL ? &src->ref : NULL)) {
1012
iris_destroy_shader_state(ctx, *dst);
1019
iris_shader_variant_reference(struct iris_compiled_shader **dst,
1020
struct iris_compiled_shader *src)
1022
struct iris_compiled_shader *old_dst = *dst;
1024
if (pipe_reference(old_dst ? &old_dst->ref: NULL, src ? &src->ref : NULL))
1025
iris_delete_shader_variant(old_dst);
1030
bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
1033
uint32_t *kernel_out,
1034
void *prog_data_out);
1035
bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch, uint32_t stage,
1036
const void *key, uint32_t key_size,
1037
const void *kernel, uint32_t kernel_size,
1038
const struct brw_stage_prog_data *prog_data,
1039
uint32_t prog_data_size,
1040
uint32_t *kernel_out,
1041
void *prog_data_out);
1043
/* iris_resolve.c */
1045
void iris_predraw_resolve_inputs(struct iris_context *ice,
1046
struct iris_batch *batch,
1047
bool *draw_aux_buffer_disabled,
1048
gl_shader_stage stage,
1049
bool consider_framebuffer);
1050
void iris_predraw_resolve_framebuffer(struct iris_context *ice,
1051
struct iris_batch *batch,
1052
bool *draw_aux_buffer_disabled);
1053
void iris_predraw_flush_buffers(struct iris_context *ice,
1054
struct iris_batch *batch,
1055
gl_shader_stage stage);
1056
void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
1057
struct iris_batch *batch);
1058
void iris_cache_flush_for_render(struct iris_batch *batch,
1060
enum isl_aux_usage aux_usage);
1061
int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
1062
struct pipe_driver_query_info *info);
1063
int iris_get_driver_query_group_info(struct pipe_screen *pscreen,
1065
struct pipe_driver_query_group_info *info);
1068
void gfx9_toggle_preemption(struct iris_context *ice,
1069
struct iris_batch *batch,
1070
const struct pipe_draw_info *draw);
1075
# include "iris_genx_protos.h"
1077
# define genX(x) gfx4_##x
1078
# include "iris_genx_protos.h"
1080
# define genX(x) gfx5_##x
1081
# include "iris_genx_protos.h"
1083
# define genX(x) gfx6_##x
1084
# include "iris_genx_protos.h"
1086
# define genX(x) gfx7_##x
1087
# include "iris_genx_protos.h"
1089
# define genX(x) gfx75_##x
1090
# include "iris_genx_protos.h"
1092
# define genX(x) gfx8_##x
1093
# include "iris_genx_protos.h"
1095
# define genX(x) gfx9_##x
1096
# include "iris_genx_protos.h"
1098
# define genX(x) gfx11_##x
1099
# include "iris_genx_protos.h"
1101
# define genX(x) gfx12_##x
1102
# include "iris_genx_protos.h"
1104
# define genX(x) gfx125_##x
1105
# include "iris_genx_protos.h"
added
removed
src/gallium/drivers/iris/iris_context.h
