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* Copyright © 2015 Intel Corporation
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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#include "anv_private.h"
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#include "common/intel_aux_map.h"
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#include "common/intel_sample_positions.h"
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#include "common/intel_pixel_hash.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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genX(emit_slice_hashing_state)(struct anv_device *device,
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struct anv_batch *batch)
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/* Gfx11 hardware has two pixel pipes at most. */
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for (unsigned i = 2; i < ARRAY_SIZE(device->info.ppipe_subslices); i++)
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assert(device->info.ppipe_subslices[i] == 0);
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if (device->info.ppipe_subslices[0] == device->info.ppipe_subslices[1])
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if (!device->slice_hash.alloc_size) {
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unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;
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anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
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const bool flip = device->info.ppipe_subslices[0] <
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device->info.ppipe_subslices[1];
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struct GENX(SLICE_HASH_TABLE) table;
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intel_compute_pixel_hash_table_3way(16, 16, 3, 3, flip, table.Entry[0]);
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GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, &table);
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anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
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ptr.SliceHashStatePointerValid = true;
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ptr.SliceHashTableStatePointer = device->slice_hash.offset;
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anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
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mode.SliceHashingTableEnable = true;
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#elif GFX_VERx10 == 120
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/* For each n calculate ppipes_of[n], equal to the number of pixel pipes
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* present with n active dual subslices.
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unsigned ppipes_of[3] = {};
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for (unsigned n = 0; n < ARRAY_SIZE(ppipes_of); n++) {
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for (unsigned p = 0; p < 3; p++)
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ppipes_of[n] += (device->info.ppipe_subslices[p] == n);
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/* Gfx12 has three pixel pipes. */
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for (unsigned p = 3; p < ARRAY_SIZE(device->info.ppipe_subslices); p++)
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assert(device->info.ppipe_subslices[p] == 0);
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if (ppipes_of[2] == 3 || ppipes_of[0] == 2) {
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/* All three pixel pipes have the maximum number of active dual
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* subslices, or there is only one active pixel pipe: Nothing to do.
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anv_batch_emit(batch, GENX(3DSTATE_SUBSLICE_HASH_TABLE), p) {
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p.SliceHashControl[0] = TABLE_0;
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if (ppipes_of[2] == 2 && ppipes_of[0] == 1)
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intel_compute_pixel_hash_table_3way(8, 16, 2, 2, 0, p.TwoWayTableEntry[0]);
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else if (ppipes_of[2] == 1 && ppipes_of[1] == 1 && ppipes_of[0] == 1)
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intel_compute_pixel_hash_table_3way(8, 16, 3, 3, 0, p.TwoWayTableEntry[0]);
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if (ppipes_of[2] == 2 && ppipes_of[1] == 1)
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intel_compute_pixel_hash_table_3way(8, 16, 5, 4, 0, p.ThreeWayTableEntry[0]);
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else if (ppipes_of[2] == 2 && ppipes_of[0] == 1)
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intel_compute_pixel_hash_table_3way(8, 16, 2, 2, 0, p.ThreeWayTableEntry[0]);
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else if (ppipes_of[2] == 1 && ppipes_of[1] == 1 && ppipes_of[0] == 1)
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intel_compute_pixel_hash_table_3way(8, 16, 3, 3, 0, p.ThreeWayTableEntry[0]);
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unreachable("Illegal fusing.");
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anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), p) {
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p.SubsliceHashingTableEnable = true;
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p.SubsliceHashingTableEnableMask = true;
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#elif GFX_VERx10 == 125
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uint32_t ppipe_mask = 0;
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for (unsigned p = 0; p < ARRAY_SIZE(device->info.ppipe_subslices); p++) {
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if (device->info.ppipe_subslices[p])
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ppipe_mask |= (1u << p);
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if (!device->slice_hash.alloc_size) {
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unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;
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anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
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struct GENX(SLICE_HASH_TABLE) table;
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/* Note that the hardware expects an array with 7 tables, each
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* table is intended to specify the pixel pipe hashing behavior
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* for every possible slice count between 2 and 8, however that
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* doesn't actually work, among other reasons due to hardware
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* bugs that will cause the GPU to erroneously access the table
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* at the wrong index in some cases, so in practice all 7 tables
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* need to be initialized to the same value.
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for (unsigned i = 0; i < 7; i++)
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intel_compute_pixel_hash_table_nway(16, 16, ppipe_mask, table.Entry[i][0]);
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GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, &table);
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anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
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ptr.SliceHashStatePointerValid = true;
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ptr.SliceHashTableStatePointer = device->slice_hash.offset;
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anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
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mode.SliceHashingTableEnable = true;
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mode.SliceHashingTableEnableMask = true;
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mode.CrossSliceHashingMode = (util_bitcount(ppipe_mask) > 1 ?
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hashing32x32 : NormalMode);
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mode.CrossSliceHashingModeMask = -1;
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init_render_queue_state(struct anv_queue *queue)
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struct anv_device *device = queue->device;
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struct anv_batch batch = {
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.end = (void *) cmds + sizeof(cmds),
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anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
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ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
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ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
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ps.PipelineSelection = _3D;
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anv_batch_write_reg(&batch, GENX(CACHE_MODE_1), cm1) {
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cm1.FloatBlendOptimizationEnable = true;
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cm1.FloatBlendOptimizationEnableMask = true;
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cm1.MSCRAWHazardAvoidanceBit = true;
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cm1.MSCRAWHazardAvoidanceBitMask = true;
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cm1.PartialResolveDisableInVC = true;
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cm1.PartialResolveDisableInVCMask = true;
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#if GFX_VERx10 >= 125
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/* GEN:BUG:1607854226:
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* Non-pipelined state has issues with not applying in MEDIA/GPGPU mode.
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* Fortunately, we always start the context off in 3D mode.
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uint32_t mocs = device->isl_dev.mocs.internal;
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anv_batch_emit(&batch, GENX(STATE_BASE_ADDRESS), sba) {
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sba.GeneralStateBaseAddress = (struct anv_address) { NULL, 0 };
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sba.GeneralStateBufferSize = 0xfffff;
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sba.GeneralStateMOCS = mocs;
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sba.GeneralStateBaseAddressModifyEnable = true;
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sba.GeneralStateBufferSizeModifyEnable = true;
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sba.StatelessDataPortAccessMOCS = mocs;
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sba.SurfaceStateBaseAddress =
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(struct anv_address) { .offset = SURFACE_STATE_POOL_MIN_ADDRESS };
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sba.SurfaceStateMOCS = mocs;
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sba.SurfaceStateBaseAddressModifyEnable = true;
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sba.DynamicStateBaseAddress =
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(struct anv_address) { .offset = DYNAMIC_STATE_POOL_MIN_ADDRESS };
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sba.DynamicStateBufferSize = DYNAMIC_STATE_POOL_SIZE / 4096;
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sba.DynamicStateMOCS = mocs;
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sba.DynamicStateBaseAddressModifyEnable = true;
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sba.DynamicStateBufferSizeModifyEnable = true;
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sba.IndirectObjectBaseAddress = (struct anv_address) { NULL, 0 };
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sba.IndirectObjectBufferSize = 0xfffff;
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sba.IndirectObjectMOCS = mocs;
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sba.IndirectObjectBaseAddressModifyEnable = true;
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sba.IndirectObjectBufferSizeModifyEnable = true;
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sba.InstructionBaseAddress =
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(struct anv_address) { .offset = INSTRUCTION_STATE_POOL_MIN_ADDRESS };
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sba.InstructionBufferSize = INSTRUCTION_STATE_POOL_SIZE / 4096;
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sba.InstructionMOCS = mocs;
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sba.InstructionBaseAddressModifyEnable = true;
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sba.InstructionBuffersizeModifyEnable = true;
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sba.BindlessSurfaceStateBaseAddress =
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(struct anv_address) { .offset = SURFACE_STATE_POOL_MIN_ADDRESS };
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sba.BindlessSurfaceStateSize = (1 << 20) - 1;
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sba.BindlessSurfaceStateMOCS = mocs;
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sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
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sba.BindlessSamplerStateBaseAddress = (struct anv_address) { NULL, 0 };
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sba.BindlessSamplerStateMOCS = mocs;
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sba.BindlessSamplerStateBaseAddressModifyEnable = true;
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sba.BindlessSamplerStateBufferSize = 0;
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anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
247
anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
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rect.ClippedDrawingRectangleYMin = 0;
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rect.ClippedDrawingRectangleXMin = 0;
250
rect.ClippedDrawingRectangleYMax = UINT16_MAX;
251
rect.ClippedDrawingRectangleXMax = UINT16_MAX;
252
rect.DrawingRectangleOriginY = 0;
253
rect.DrawingRectangleOriginX = 0;
257
anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
259
genX(emit_sample_pattern)(&batch, NULL);
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/* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
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* section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
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* Clear." It mentions that the packet overrides GPU state for the clear
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* operation and needs to be reset to 0s to clear the overrides. Depending
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* on the kernel, we may not get a context with the state for this packet
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* zeroed. Do it ourselves just in case. We've observed this to prevent a
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* number of GPU hangs on ICL.
269
anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
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/* The default behavior of bit 5 "Headerless Message for Pre-emptable
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* Contexts" in SAMPLER MODE register is set to 0, which means
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* headerless sampler messages are not allowed for pre-emptable
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* contexts. Set the bit 5 to 1 to allow them.
278
anv_batch_write_reg(&batch, GENX(SAMPLER_MODE), sm) {
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sm.HeaderlessMessageforPreemptableContexts = true;
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sm.HeaderlessMessageforPreemptableContextsMask = true;
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/* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
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* HALF_SLICE_CHICKEN7 register.
286
anv_batch_write_reg(&batch, GENX(HALF_SLICE_CHICKEN7), hsc7) {
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hsc7.EnabledTexelOffsetPrecisionFix = true;
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hsc7.EnabledTexelOffsetPrecisionFixMask = true;
291
anv_batch_write_reg(&batch, GENX(TCCNTLREG), tcc) {
292
tcc.L3DataPartialWriteMergingEnable = true;
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tcc.ColorZPartialWriteMergingEnable = true;
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tcc.URBPartialWriteMergingEnable = true;
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tcc.TCDisable = true;
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genX(emit_slice_hashing_state)(device, &batch);
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/* hardware specification recommends disabling repacking for
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* the compatibility with decompression mechanism in display controller.
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if (device->info.disable_ccs_repack) {
305
anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) {
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cm0.DisableRepackingforCompression = true;
307
cm0.DisableRepackingforCompressionMask = true;
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/* an unknown issue is causing vs push constants to become
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* corrupted during object-level preemption. For now, restrict
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* to command buffer level preemption to avoid rendering
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anv_batch_write_reg(&batch, GENX(CS_CHICKEN1), cc1) {
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cc1.ReplayMode = MidcmdbufferPreemption;
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cc1.ReplayModeMask = true;
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#if GFX_VERx10 == 120
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cc1.DisablePreemptionandHighPriorityPausingdueto3DPRIMITIVECommand = true;
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cc1.DisablePreemptionandHighPriorityPausingdueto3DPRIMITIVECommandMask = true;
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#define AA_LINE_QUALITY_REG GENX(3D_CHICKEN3)
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#define AA_LINE_QUALITY_REG GENX(CHICKEN_RASTER_1)
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/* Enable the new line drawing algorithm that produces higher quality
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anv_batch_write_reg(&batch, AA_LINE_QUALITY_REG, c3) {
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c3.AALineQualityFix = true;
337
c3.AALineQualityFixMask = true;
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if (device->info.has_aux_map) {
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uint64_t aux_base_addr = intel_aux_map_get_base(device->aux_map_ctx);
344
assert(aux_base_addr % (32 * 1024) == 0);
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anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
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lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
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lri.DataDWord = aux_base_addr & 0xffffffff;
349
anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
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lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;
351
lri.DataDWord = aux_base_addr >> 32;
356
/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
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* 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
359
* This is only safe on kernels with context isolation support.
361
if (GFX_VER >= 8 && device->physical->has_context_isolation) {
363
anv_batch_write_reg(&batch, GENX(CS_DEBUG_MODE2), csdm2) {
364
csdm2.CONSTANT_BUFFERAddressOffsetDisable = true;
365
csdm2.CONSTANT_BUFFERAddressOffsetDisableMask = true;
368
anv_batch_write_reg(&batch, GENX(INSTPM), instpm) {
369
instpm.CONSTANT_BUFFERAddressOffsetDisable = true;
370
instpm.CONSTANT_BUFFERAddressOffsetDisableMask = true;
376
/* Starting with GFX version 11, SLM is no longer part of the L3$ config
377
* so it never changes throughout the lifetime of the VkDevice.
379
const struct intel_l3_config *cfg = intel_get_default_l3_config(&device->info);
380
genX(emit_l3_config)(&batch, device, cfg);
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device->l3_config = cfg;
384
anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
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assert(batch.next <= batch.end);
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return anv_queue_submit_simple_batch(queue, &batch);
392
genX(init_physical_device_state)(ASSERTED struct anv_physical_device *device)
394
assert(device->info.verx10 == GFX_VERx10);
398
genX(init_device_state)(struct anv_device *device)
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device->slice_hash = (struct anv_state) { 0 };
403
for (uint32_t i = 0; i < device->queue_count; i++) {
404
struct anv_queue *queue = &device->queues[i];
405
switch (queue->family->engine_class) {
406
case I915_ENGINE_CLASS_RENDER:
407
res = init_render_queue_state(queue);
410
res = vk_error(device, VK_ERROR_INITIALIZATION_FAILED);
413
if (res != VK_SUCCESS)
420
#if GFX_VERx10 >= 125
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#define maybe_for_each_shading_rate_op(name) \
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for (VkFragmentShadingRateCombinerOpKHR name = VK_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP_KHR; \
423
name <= VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MUL_KHR; \
426
#define maybe_for_each_shading_rate_op(name)
429
/* Rather than reemitting the CPS_STATE structure everything those changes and
430
* for as many viewports as needed, we can just prepare all possible cases and
431
* just pick the right offset from the prepacked states when needed.
434
genX(init_cps_device_state)(struct anv_device *device)
437
void *cps_state_ptr = device->cps_states.map;
439
/* Disabled CPS mode */
440
for (uint32_t __v = 0; __v < MAX_VIEWPORTS; __v++) {
441
struct GENX(CPS_STATE) cps_state = {
442
.CoarsePixelShadingMode = CPS_MODE_CONSTANT,
445
#if GFX_VERx10 >= 125
446
.Combiner0OpcodeforCPsize = PASSTHROUGH,
447
.Combiner1OpcodeforCPsize = PASSTHROUGH,
448
#endif /* GFX_VERx10 >= 125 */
452
GENX(CPS_STATE_pack)(NULL, cps_state_ptr, &cps_state);
453
cps_state_ptr += GENX(CPS_STATE_length) * 4;
456
maybe_for_each_shading_rate_op(op0) {
457
maybe_for_each_shading_rate_op(op1) {
458
for (uint32_t x = 1; x <= 4; x *= 2) {
459
for (uint32_t y = 1; y <= 4; y *= 2) {
460
struct GENX(CPS_STATE) cps_state = {
461
.CoarsePixelShadingMode = CPS_MODE_CONSTANT,
466
#if GFX_VERx10 >= 125
467
static const uint32_t combiner_ops[] = {
468
[VK_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP_KHR] = PASSTHROUGH,
469
[VK_FRAGMENT_SHADING_RATE_COMBINER_OP_REPLACE_KHR] = OVERRIDE,
470
[VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MIN_KHR] = HIGH_QUALITY,
471
[VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MAX_KHR] = LOW_QUALITY,
472
[VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MUL_KHR] = RELATIVE,
475
cps_state.Combiner0OpcodeforCPsize = combiner_ops[op0];
476
cps_state.Combiner1OpcodeforCPsize = combiner_ops[op1];
477
#endif /* GFX_VERx10 >= 125 */
479
for (uint32_t __v = 0; __v < MAX_VIEWPORTS; __v++) {
480
GENX(CPS_STATE_pack)(NULL, cps_state_ptr, &cps_state);
481
cps_state_ptr += GENX(CPS_STATE_length) * 4;
487
#endif /* GFX_VER >= 12 */
492
get_cps_state_offset(struct anv_device *device, bool cps_enabled,
493
const struct anv_dynamic_state *d)
496
return device->cps_states.offset;
499
static const uint32_t size_index[] = {
505
#if GFX_VERx10 >= 125
507
1 + /* skip disabled */
508
d->fragment_shading_rate.ops[0] * 5 * 3 * 3 +
509
d->fragment_shading_rate.ops[1] * 3 * 3 +
510
size_index[d->fragment_shading_rate.rate.width] * 3 +
511
size_index[d->fragment_shading_rate.rate.height];
514
1 + /* skip disabled */
515
size_index[d->fragment_shading_rate.rate.width] * 3 +
516
size_index[d->fragment_shading_rate.rate.height];
519
offset *= MAX_VIEWPORTS * GENX(CPS_STATE_length) * 4;
521
return device->cps_states.offset + offset;
523
#endif /* GFX_VER >= 12 */
526
genX(emit_l3_config)(struct anv_batch *batch,
527
const struct anv_device *device,
528
const struct intel_l3_config *cfg)
530
UNUSED const struct intel_device_info *devinfo = &device->info;
535
#define L3_ALLOCATION_REG GENX(L3ALLOC)
536
#define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
538
#define L3_ALLOCATION_REG GENX(L3CNTLREG)
539
#define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
542
anv_batch_write_reg(batch, L3_ALLOCATION_REG, l3cr) {
545
l3cr.L3FullWayAllocationEnable = true;
547
unreachable("Invalid L3$ config");
551
l3cr.SLMEnable = cfg->n[INTEL_L3P_SLM];
554
/* Wa_1406697149: Bit 9 "Error Detection Behavior Control" must be
555
* set in L3CNTLREG register. The default setting of the bit is not
556
* the desirable behavior.
558
l3cr.ErrorDetectionBehaviorControl = true;
559
l3cr.UseFullWays = true;
560
#endif /* GFX_VER == 11 */
561
assert(cfg->n[INTEL_L3P_IS] == 0);
562
assert(cfg->n[INTEL_L3P_C] == 0);
563
assert(cfg->n[INTEL_L3P_T] == 0);
564
l3cr.URBAllocation = cfg->n[INTEL_L3P_URB];
565
l3cr.ROAllocation = cfg->n[INTEL_L3P_RO];
566
l3cr.DCAllocation = cfg->n[INTEL_L3P_DC];
567
l3cr.AllAllocation = cfg->n[INTEL_L3P_ALL];
571
#else /* GFX_VER < 8 */
573
const bool has_dc = cfg->n[INTEL_L3P_DC] || cfg->n[INTEL_L3P_ALL];
574
const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] ||
575
cfg->n[INTEL_L3P_ALL];
576
const bool has_c = cfg->n[INTEL_L3P_C] || cfg->n[INTEL_L3P_RO] ||
577
cfg->n[INTEL_L3P_ALL];
578
const bool has_t = cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_RO] ||
579
cfg->n[INTEL_L3P_ALL];
581
assert(!cfg->n[INTEL_L3P_ALL]);
583
/* When enabled SLM only uses a portion of the L3 on half of the banks,
584
* the matching space on the remaining banks has to be allocated to a
585
* client (URB for all validated configurations) set to the
586
* lower-bandwidth 2-bank address hashing mode.
588
const bool urb_low_bw = cfg->n[INTEL_L3P_SLM] && devinfo->platform != INTEL_PLATFORM_BYT;
589
assert(!urb_low_bw || cfg->n[INTEL_L3P_URB] == cfg->n[INTEL_L3P_SLM]);
591
/* Minimum number of ways that can be allocated to the URB. */
592
const unsigned n0_urb = devinfo->platform == INTEL_PLATFORM_BYT ? 32 : 0;
593
assert(cfg->n[INTEL_L3P_URB] >= n0_urb);
595
anv_batch_write_reg(batch, GENX(L3SQCREG1), l3sqc) {
596
l3sqc.ConvertDC_UC = !has_dc;
597
l3sqc.ConvertIS_UC = !has_is;
598
l3sqc.ConvertC_UC = !has_c;
599
l3sqc.ConvertT_UC = !has_t;
601
l3sqc.L3SQGeneralPriorityCreditInitialization = SQGPCI_DEFAULT;
603
l3sqc.L3SQGeneralPriorityCreditInitialization =
604
devinfo->platform == INTEL_PLATFORM_BYT ? BYT_SQGPCI_DEFAULT : SQGPCI_DEFAULT;
606
l3sqc.L3SQHighPriorityCreditInitialization = SQHPCI_DEFAULT;
609
anv_batch_write_reg(batch, GENX(L3CNTLREG2), l3cr2) {
610
l3cr2.SLMEnable = cfg->n[INTEL_L3P_SLM];
611
l3cr2.URBLowBandwidth = urb_low_bw;
612
l3cr2.URBAllocation = cfg->n[INTEL_L3P_URB] - n0_urb;
613
#if !GFX_VERx10 == 75
614
l3cr2.ALLAllocation = cfg->n[INTEL_L3P_ALL];
616
l3cr2.ROAllocation = cfg->n[INTEL_L3P_RO];
617
l3cr2.DCAllocation = cfg->n[INTEL_L3P_DC];
620
anv_batch_write_reg(batch, GENX(L3CNTLREG3), l3cr3) {
621
l3cr3.ISAllocation = cfg->n[INTEL_L3P_IS];
622
l3cr3.ISLowBandwidth = 0;
623
l3cr3.CAllocation = cfg->n[INTEL_L3P_C];
624
l3cr3.CLowBandwidth = 0;
625
l3cr3.TAllocation = cfg->n[INTEL_L3P_T];
626
l3cr3.TLowBandwidth = 0;
630
if (device->physical->cmd_parser_version >= 4) {
631
/* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
632
* them disabled to avoid crashing the system hard.
634
anv_batch_write_reg(batch, GENX(SCRATCH1), s1) {
635
s1.L3AtomicDisable = !has_dc;
637
anv_batch_write_reg(batch, GENX(CHICKEN3), c3) {
638
c3.L3AtomicDisableMask = true;
639
c3.L3AtomicDisable = !has_dc;
642
#endif /* GFX_VERx10 == 75 */
644
#endif /* GFX_VER < 8 */
648
genX(emit_multisample)(struct anv_batch *batch, uint32_t samples,
649
const struct intel_sample_position *positions)
651
anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
652
ms.NumberofMultisamples = __builtin_ffs(samples) - 1;
654
ms.PixelLocation = CENTER;
656
/* The PRM says that this bit is valid only for DX9:
658
* SW can choose to set this bit only for DX9 API. DX10/OGL API's
659
* should not have any effect by setting or not setting this bit.
661
ms.PixelPositionOffsetEnable = false;
665
INTEL_SAMPLE_POS_1X_ARRAY(ms.Sample, positions);
668
INTEL_SAMPLE_POS_2X_ARRAY(ms.Sample, positions);
671
INTEL_SAMPLE_POS_4X_ARRAY(ms.Sample, positions);
674
INTEL_SAMPLE_POS_8X_ARRAY(ms.Sample, positions);
685
genX(emit_sample_pattern)(struct anv_batch *batch,
686
const struct anv_dynamic_state *d)
688
/* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
689
* VkPhysicalDeviceFeatures::standardSampleLocations.
691
anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
692
/* The Skylake PRM Vol. 2a "3DSTATE_SAMPLE_PATTERN" says:
694
* "When programming the sample offsets (for NUMSAMPLES_4 or _8
695
* and MSRASTMODE_xxx_PATTERN), the order of the samples 0 to 3
696
* (or 7 for 8X, or 15 for 16X) must have monotonically increasing
697
* distance from the pixel center. This is required to get the
698
* correct centroid computation in the device."
700
* However, the Vulkan spec seems to require that the the samples occur
701
* in the order provided through the API. The standard sample patterns
702
* have the above property that they have monotonically increasing
703
* distances from the center but client-provided ones do not. As long as
704
* this only affects centroid calculations as the docs say, we should be
705
* ok because OpenGL and Vulkan only require that the centroid be some
706
* lit sample and that it's the same for all samples in a pixel; they
707
* have no requirement that it be the one closest to center.
710
INTEL_SAMPLE_POS_1X_ARRAY(sp._1xSample, d->sample_locations.locations_1);
711
INTEL_SAMPLE_POS_2X_ARRAY(sp._2xSample, d->sample_locations.locations_2);
712
INTEL_SAMPLE_POS_4X_ARRAY(sp._4xSample, d->sample_locations.locations_4);
713
INTEL_SAMPLE_POS_8X_ARRAY(sp._8xSample, d->sample_locations.locations_8);
715
INTEL_SAMPLE_POS_16X_ARRAY(sp._16xSample, d->sample_locations.locations_16);
718
INTEL_SAMPLE_POS_1X(sp._1xSample);
719
INTEL_SAMPLE_POS_2X(sp._2xSample);
720
INTEL_SAMPLE_POS_4X(sp._4xSample);
721
INTEL_SAMPLE_POS_8X(sp._8xSample);
723
INTEL_SAMPLE_POS_16X(sp._16xSample);
732
genX(emit_shading_rate)(struct anv_batch *batch,
733
const struct anv_graphics_pipeline *pipeline,
734
struct anv_dynamic_state *dynamic_state)
736
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
737
const bool cps_enable = wm_prog_data && wm_prog_data->per_coarse_pixel_dispatch;
740
anv_batch_emit(batch, GENX(3DSTATE_CPS), cps) {
741
cps.CoarsePixelShadingMode = cps_enable ? CPS_MODE_CONSTANT : CPS_MODE_NONE;
743
cps.MinCPSizeX = dynamic_state->fragment_shading_rate.rate.width;
744
cps.MinCPSizeY = dynamic_state->fragment_shading_rate.rate.height;
748
/* TODO: we can optimize this flush in the following cases:
750
* In the case where the last geometry shader emits a value that is not
751
* constant, we can avoid this stall because we can synchronize the
752
* pixel shader internally with
753
* 3DSTATE_PS::EnablePSDependencyOnCPsizeChange.
755
* If we know that the previous pipeline and the current one are using
756
* the same fragment shading rate.
758
anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
759
#if GFX_VERx10 >= 125
760
pc.PSSStallSyncEnable = true;
762
pc.PSDSyncEnable = true;
766
anv_batch_emit(batch, GENX(3DSTATE_CPS_POINTERS), cps) {
767
struct anv_device *device = pipeline->base.device;
769
cps.CoarsePixelShadingStateArrayPointer =
770
get_cps_state_offset(device, cps_enable, dynamic_state);
774
#endif /* GFX_VER >= 11 */
777
vk_to_intel_tex_filter(VkFilter filter, bool anisotropyEnable)
781
assert(!"Invalid filter");
782
case VK_FILTER_NEAREST:
783
return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_NEAREST;
784
case VK_FILTER_LINEAR:
785
return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_LINEAR;
790
vk_to_intel_max_anisotropy(float ratio)
792
return (anv_clamp_f(ratio, 2, 16) - 2) / 2;
795
static const uint32_t vk_to_intel_mipmap_mode[] = {
796
[VK_SAMPLER_MIPMAP_MODE_NEAREST] = MIPFILTER_NEAREST,
797
[VK_SAMPLER_MIPMAP_MODE_LINEAR] = MIPFILTER_LINEAR
800
static const uint32_t vk_to_intel_tex_address[] = {
801
[VK_SAMPLER_ADDRESS_MODE_REPEAT] = TCM_WRAP,
802
[VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR,
803
[VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE] = TCM_CLAMP,
804
[VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
805
[VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
808
/* Vulkan specifies the result of shadow comparisons as:
809
* 1 if ref <op> texel,
813
* 0 if texel <op> ref,
816
* So, these look a bit strange because there's both a negation
817
* and swapping of the arguments involved.
819
static const uint32_t vk_to_intel_shadow_compare_op[] = {
820
[VK_COMPARE_OP_NEVER] = PREFILTEROP_ALWAYS,
821
[VK_COMPARE_OP_LESS] = PREFILTEROP_LEQUAL,
822
[VK_COMPARE_OP_EQUAL] = PREFILTEROP_NOTEQUAL,
823
[VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROP_LESS,
824
[VK_COMPARE_OP_GREATER] = PREFILTEROP_GEQUAL,
825
[VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROP_EQUAL,
826
[VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROP_GREATER,
827
[VK_COMPARE_OP_ALWAYS] = PREFILTEROP_NEVER,
831
static const uint32_t vk_to_intel_sampler_reduction_mode[] = {
832
[VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
833
[VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM,
834
[VK_SAMPLER_REDUCTION_MODE_MAX_EXT] = MAXIMUM,
838
VkResult genX(CreateSampler)(
840
const VkSamplerCreateInfo* pCreateInfo,
841
const VkAllocationCallbacks* pAllocator,
844
ANV_FROM_HANDLE(anv_device, device, _device);
845
struct anv_sampler *sampler;
847
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
849
sampler = vk_object_zalloc(&device->vk, pAllocator, sizeof(*sampler),
850
VK_OBJECT_TYPE_SAMPLER);
852
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
854
sampler->n_planes = 1;
856
uint32_t border_color_stride = GFX_VERx10 == 75 ? 512 : 64;
857
uint32_t border_color_offset;
858
ASSERTED bool has_custom_color = false;
859
if (pCreateInfo->borderColor <= VK_BORDER_COLOR_INT_OPAQUE_WHITE) {
860
border_color_offset = device->border_colors.offset +
861
pCreateInfo->borderColor *
864
assert(GFX_VER >= 8);
865
sampler->custom_border_color =
866
anv_state_reserved_pool_alloc(&device->custom_border_colors);
867
border_color_offset = sampler->custom_border_color.offset;
871
unsigned sampler_reduction_mode = STD_FILTER;
872
bool enable_sampler_reduction = false;
875
vk_foreach_struct(ext, pCreateInfo->pNext) {
876
switch (ext->sType) {
877
case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
878
VkSamplerYcbcrConversionInfo *pSamplerConversion =
879
(VkSamplerYcbcrConversionInfo *) ext;
880
ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion,
881
pSamplerConversion->conversion);
883
/* Ignore conversion for non-YUV formats. This fulfills a requirement
884
* for clients that want to utilize same code path for images with
885
* external formats (VK_FORMAT_UNDEFINED) and "regular" RGBA images
886
* where format is known.
888
if (conversion == NULL || !conversion->format->can_ycbcr)
891
sampler->n_planes = conversion->format->n_planes;
892
sampler->conversion = conversion;
896
case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO: {
897
VkSamplerReductionModeCreateInfo *sampler_reduction =
898
(VkSamplerReductionModeCreateInfo *) ext;
899
sampler_reduction_mode =
900
vk_to_intel_sampler_reduction_mode[sampler_reduction->reductionMode];
901
enable_sampler_reduction = true;
905
case VK_STRUCTURE_TYPE_SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT: {
906
VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
907
(VkSamplerCustomBorderColorCreateInfoEXT *) ext;
908
if (sampler->custom_border_color.map == NULL)
911
union isl_color_value color = { .u32 = {
912
custom_border_color->customBorderColor.uint32[0],
913
custom_border_color->customBorderColor.uint32[1],
914
custom_border_color->customBorderColor.uint32[2],
915
custom_border_color->customBorderColor.uint32[3],
918
const struct anv_format *format_desc =
919
custom_border_color->format != VK_FORMAT_UNDEFINED ?
920
anv_get_format(custom_border_color->format) : NULL;
922
/* For formats with a swizzle, it does not carry over to the sampler
923
* for border colors, so we need to do the swizzle ourselves here.
925
if (format_desc && format_desc->n_planes == 1 &&
926
!isl_swizzle_is_identity(format_desc->planes[0].swizzle)) {
927
const struct anv_format_plane *fmt_plane = &format_desc->planes[0];
929
assert(!isl_format_has_int_channel(fmt_plane->isl_format));
930
color = isl_color_value_swizzle(color, fmt_plane->swizzle, true);
933
memcpy(sampler->custom_border_color.map, color.u32, sizeof(color));
934
has_custom_color = true;
938
anv_debug_ignored_stype(ext->sType);
943
assert((sampler->custom_border_color.map == NULL) || has_custom_color);
945
if (device->physical->has_bindless_samplers) {
946
/* If we have bindless, allocate enough samplers. We allocate 32 bytes
947
* for each sampler instead of 16 bytes because we want all bindless
948
* samplers to be 32-byte aligned so we don't have to use indirect
949
* sampler messages on them.
951
sampler->bindless_state =
952
anv_state_pool_alloc(&device->dynamic_state_pool,
953
sampler->n_planes * 32, 32);
956
for (unsigned p = 0; p < sampler->n_planes; p++) {
957
const bool plane_has_chroma =
958
sampler->conversion && sampler->conversion->format->planes[p].has_chroma;
959
const VkFilter min_filter =
960
plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->minFilter;
961
const VkFilter mag_filter =
962
plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->magFilter;
963
const bool enable_min_filter_addr_rounding = min_filter != VK_FILTER_NEAREST;
964
const bool enable_mag_filter_addr_rounding = mag_filter != VK_FILTER_NEAREST;
965
/* From Broadwell PRM, SAMPLER_STATE:
966
* "Mip Mode Filter must be set to MIPFILTER_NONE for Planar YUV surfaces."
968
const bool isl_format_is_planar_yuv = sampler->conversion &&
969
isl_format_is_yuv(sampler->conversion->format->planes[0].isl_format) &&
970
isl_format_is_planar(sampler->conversion->format->planes[0].isl_format);
972
const uint32_t mip_filter_mode =
973
isl_format_is_planar_yuv ?
974
MIPFILTER_NONE : vk_to_intel_mipmap_mode[pCreateInfo->mipmapMode];
976
struct GENX(SAMPLER_STATE) sampler_state = {
977
.SamplerDisable = false,
978
.TextureBorderColorMode = DX10OGL,
981
.CPSLODCompensationEnable = true,
985
.LODPreClampMode = CLAMP_MODE_OGL,
987
.LODPreClampEnable = CLAMP_ENABLE_OGL,
993
.MipModeFilter = mip_filter_mode,
994
.MagModeFilter = vk_to_intel_tex_filter(mag_filter, pCreateInfo->anisotropyEnable),
995
.MinModeFilter = vk_to_intel_tex_filter(min_filter, pCreateInfo->anisotropyEnable),
996
.TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
997
.AnisotropicAlgorithm =
998
pCreateInfo->anisotropyEnable ? EWAApproximation : LEGACY,
999
.MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
1000
.MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
1001
.ChromaKeyEnable = 0,
1002
.ChromaKeyIndex = 0,
1005
vk_to_intel_shadow_compare_op[pCreateInfo->compareEnable ?
1006
pCreateInfo->compareOp : VK_COMPARE_OP_NEVER],
1007
.CubeSurfaceControlMode = OVERRIDE,
1009
.BorderColorPointer = border_color_offset,
1012
.LODClampMagnificationMode = MIPNONE,
1015
.MaximumAnisotropy = vk_to_intel_max_anisotropy(pCreateInfo->maxAnisotropy),
1016
.RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
1017
.RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
1018
.VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
1019
.VAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
1020
.UAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
1021
.UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
1022
.TrilinearFilterQuality = 0,
1023
.NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
1024
.TCXAddressControlMode = vk_to_intel_tex_address[pCreateInfo->addressModeU],
1025
.TCYAddressControlMode = vk_to_intel_tex_address[pCreateInfo->addressModeV],
1026
.TCZAddressControlMode = vk_to_intel_tex_address[pCreateInfo->addressModeW],
1029
.ReductionType = sampler_reduction_mode,
1030
.ReductionTypeEnable = enable_sampler_reduction,
1034
GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
1036
if (sampler->bindless_state.map) {
1037
memcpy(sampler->bindless_state.map + p * 32,
1038
sampler->state[p], GENX(SAMPLER_STATE_length) * 4);
1042
*pSampler = anv_sampler_to_handle(sampler);
added
removed
src/intel/vulkan/genX_state.c
