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* Copyright © 2010 - 2015 Intel Corporation
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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#ifndef BRW_COMPILER_H
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#define BRW_COMPILER_H
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#include "c11/threads.h"
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#include "dev/intel_device_info.h"
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#include "main/config.h"
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#include "util/ralloc.h"
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#include "util/u_math.h"
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struct nir_shader_compiler_options;
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typedef struct nir_shader nir_shader;
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const struct intel_device_info *devinfo;
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/* This lock must be taken if the compiler is to be modified in any way,
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* including adding something to the ralloc child list.
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* Array of the ra classes for the unaligned contiguous register
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struct ra_class **classes;
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* Array of the ra classes for the unaligned contiguous register
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* block sizes used, indexed by register size.
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struct ra_class *classes[16];
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* ra class for the aligned barycentrics we use for PLN, which doesn't
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struct ra_class *aligned_bary_class;
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void (*shader_debug_log)(void *, unsigned *id, const char *str, ...) PRINTFLIKE(3, 4);
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void (*shader_perf_log)(void *, unsigned *id, const char *str, ...) PRINTFLIKE(3, 4);
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bool scalar_stage[MESA_ALL_SHADER_STAGES];
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struct nir_shader_compiler_options *nir_options[MESA_ALL_SHADER_STAGES];
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* Apply workarounds for SIN and COS output range problems.
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* This can negatively impact performance.
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* Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
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* Base Address? (If not, it's a normal GPU address.)
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bool constant_buffer_0_is_relative;
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* Whether or not the driver supports NIR shader constants. This controls
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* whether nir_opt_large_constants will be run.
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bool supports_shader_constants;
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* Whether or not the driver wants variable group size to be lowered by the
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bool lower_variable_group_size;
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* Whether indirect UBO loads should use the sampler or go through the
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* data/constant cache. For the sampler, UBO surface states have to be set
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* up with VK_FORMAT_R32G32B32A32_FLOAT whereas if it's going through the
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* constant or data cache, UBOs must use VK_FORMAT_RAW.
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bool indirect_ubos_use_sampler;
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struct nir_shader *clc_shader;
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#define brw_shader_debug_log(compiler, data, fmt, ... ) do { \
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static unsigned id = 0; \
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compiler->shader_debug_log(data, &id, fmt, ##__VA_ARGS__); \
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#define brw_shader_perf_log(compiler, data, fmt, ... ) do { \
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static unsigned id = 0; \
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compiler->shader_perf_log(data, &id, fmt, ##__VA_ARGS__); \
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* We use a constant subgroup size of 32. It really only needs to be a
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* maximum and, since we do SIMD32 for compute shaders in some cases, it
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* needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
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* subgroup size of 32 but will act as if 16 or 24 of those channels are
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#define BRW_SUBGROUP_SIZE 32
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brw_shader_stage_is_bindless(gl_shader_stage stage)
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return stage >= MESA_SHADER_RAYGEN &&
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stage <= MESA_SHADER_CALLABLE;
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brw_shader_stage_requires_bindless_resources(gl_shader_stage stage)
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return brw_shader_stage_is_bindless(stage) || gl_shader_stage_is_mesh(stage);
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* Program key structures.
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* When drawing, we look for the currently bound shaders in the program
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* cache. This is essentially a hash table lookup, and these are the keys.
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* Sometimes OpenGL features specified as state need to be simulated via
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* shader code, due to a mismatch between the API and the hardware. This
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* is often referred to as "non-orthagonal state" or "NOS". We store NOS
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* in the program key so it's considered when searching for a program. If
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* we haven't seen a particular combination before, we have to recompile a
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* new specialized version.
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* Shader compilation should not look up state in gl_context directly, but
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* instead use the copy in the program key. This guarantees recompiles will
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enum PACKED gfx6_gather_sampler_wa {
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WA_SIGN = 1, /* whether we need to sign extend */
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WA_8BIT = 2, /* if we have an 8bit format needing wa */
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WA_16BIT = 4, /* if we have a 16bit format needing wa */
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* Sampler information needed by VS, WM, and GS program cache keys.
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struct brw_sampler_prog_key_data {
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* EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
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uint16_t swizzles[MAX_SAMPLERS];
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uint32_t gl_clamp_mask[3];
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* For RG32F, gather4's channel select is broken.
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uint32_t gather_channel_quirk_mask;
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* Whether this sampler uses the compressed multisample surface layout.
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uint32_t compressed_multisample_layout_mask;
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* Whether this sampler is using 16x multisampling. If so fetching from
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* this sampler will be handled with a different instruction, ld2dms_w
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* For Sandybridge, which shader w/a we need for gather quirks.
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enum gfx6_gather_sampler_wa gfx6_gather_wa[MAX_SAMPLERS];
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* Texture units that have a YUV image bound.
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uint32_t y_u_v_image_mask;
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uint32_t y_uv_image_mask;
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uint32_t yx_xuxv_image_mask;
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uint32_t xy_uxvx_image_mask;
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uint32_t ayuv_image_mask;
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uint32_t xyuv_image_mask;
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uint32_t bt2020_mask;
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/* Scale factor for each texture. */
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float scale_factors[32];
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/** An enum representing what kind of input gl_SubgroupSize is. */
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enum PACKED brw_subgroup_size_type
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BRW_SUBGROUP_SIZE_API_CONSTANT, /**< Default Vulkan behavior */
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BRW_SUBGROUP_SIZE_UNIFORM, /**< OpenGL behavior */
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BRW_SUBGROUP_SIZE_VARYING, /**< VK_EXT_subgroup_size_control */
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/* These enums are specifically chosen so that the value of the enum is
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* also the subgroup size. If any new values are added, they must respect
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BRW_SUBGROUP_SIZE_REQUIRE_8 = 8, /**< VK_EXT_subgroup_size_control */
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BRW_SUBGROUP_SIZE_REQUIRE_16 = 16, /**< VK_EXT_subgroup_size_control */
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BRW_SUBGROUP_SIZE_REQUIRE_32 = 32, /**< VK_EXT_subgroup_size_control */
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struct brw_base_prog_key {
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unsigned program_string_id;
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enum brw_subgroup_size_type subgroup_size_type;
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bool robust_buffer_access;
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struct brw_sampler_prog_key_data tex;
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* The VF can't natively handle certain types of attributes, such as GL_FIXED
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* or most 10_10_10_2 types. These flags enable various VS workarounds to
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* "fix" attributes at the beginning of shaders.
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#define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
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#define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
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#define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
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#define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
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#define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
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* OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
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* [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
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* input vertex attributes. In Vulkan, we expose up to 28 user vertex input
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* attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
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#define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
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#define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
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* Max number of binding table entries used for stream output.
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* From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
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* minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
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* On Gfx6, the size of transform feedback data is limited not by the number
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* of components but by the number of binding table entries we set aside. We
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* use one binding table entry for a float, one entry for a vector, and one
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* entry per matrix column. Since the only way we can communicate our
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* transform feedback capabilities to the client is via
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* MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
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* worst case, in which all the varyings are floats, so we use up one binding
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* table entry per component. Therefore we need to set aside at least 64
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* binding table entries for use by transform feedback.
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* Note: since we don't currently pack varyings, it is currently impossible
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* for the client to actually use up all of these binding table entries--if
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* all of their varyings were floats, they would run out of varying slots and
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* fail to link. But that's a bug, so it seems prudent to go ahead and
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* allocate the number of binding table entries we will need once the bug is
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#define BRW_MAX_SOL_BINDINGS 64
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/** The program key for Vertex Shaders. */
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struct brw_vs_prog_key {
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struct brw_base_prog_key base;
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* Per-attribute workaround flags
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* For each attribute, a combination of BRW_ATTRIB_WA_*.
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* For OpenGL, where we expose a maximum of 16 user input atttributes
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* we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
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* slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
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* expose up to 28 user input vertex attributes that are mapped to slots
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* starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
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* enough to hold this many slots.
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uint8_t gl_attrib_wa_flags[MAX2(MAX_GL_VERT_ATTRIB, MAX_VK_VERT_ATTRIB)];
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bool copy_edgeflag:1;
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bool clamp_vertex_color:1;
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* How many user clipping planes are being uploaded to the vertex shader as
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* These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
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unsigned nr_userclip_plane_consts:4;
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* For pre-Gfx6 hardware, a bitfield indicating which texture coordinates
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* are going to be replaced with point coordinates (as a consequence of a
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* call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
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* our SF thread requires exact matching between VS outputs and FS inputs,
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* these texture coordinates will need to be unconditionally included in
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* the VUE, even if they aren't written by the vertex shader.
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uint8_t point_coord_replace;
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unsigned clamp_pointsize:1;
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/** The program key for Tessellation Control Shaders. */
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struct brw_tcs_prog_key
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struct brw_base_prog_key base;
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enum tess_primitive_mode _tes_primitive_mode;
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unsigned input_vertices;
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/** A bitfield of per-patch outputs written. */
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uint32_t patch_outputs_written;
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/** A bitfield of per-vertex outputs written. */
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uint64_t outputs_written;
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bool quads_workaround;
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/** The program key for Tessellation Evaluation Shaders. */
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struct brw_tes_prog_key
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struct brw_base_prog_key base;
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/** A bitfield of per-patch inputs read. */
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uint32_t patch_inputs_read;
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/** A bitfield of per-vertex inputs read. */
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uint64_t inputs_read;
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* How many user clipping planes are being uploaded to the tessellation
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* evaluation shader as push constants.
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* These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
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unsigned nr_userclip_plane_consts:4;
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unsigned clamp_pointsize:1;
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/** The program key for Geometry Shaders. */
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struct brw_gs_prog_key
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struct brw_base_prog_key base;
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* How many user clipping planes are being uploaded to the geometry shader
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* These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
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unsigned nr_userclip_plane_consts:4;
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unsigned clamp_pointsize:1;
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struct brw_task_prog_key
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struct brw_base_prog_key base;
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struct brw_mesh_prog_key
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struct brw_base_prog_key base;
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enum brw_sf_primitive {
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BRW_SF_PRIM_POINTS = 0,
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BRW_SF_PRIM_LINES = 1,
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BRW_SF_PRIM_TRIANGLES = 2,
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BRW_SF_PRIM_UNFILLED_TRIS = 3,
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struct brw_sf_prog_key {
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bool contains_flat_varying;
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unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
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uint8_t point_sprite_coord_replace;
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enum brw_sf_primitive primitive:2;
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bool do_twoside_color:1;
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bool frontface_ccw:1;
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bool do_point_sprite:1;
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bool do_point_coord:1;
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bool sprite_origin_lower_left:1;
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bool userclip_active:1;
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BRW_CLIP_MODE_NORMAL = 0,
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BRW_CLIP_MODE_CLIP_ALL = 1,
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BRW_CLIP_MODE_CLIP_NON_REJECTED = 2,
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BRW_CLIP_MODE_REJECT_ALL = 3,
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BRW_CLIP_MODE_ACCEPT_ALL = 4,
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BRW_CLIP_MODE_KERNEL_CLIP = 5,
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enum brw_clip_fill_mode {
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BRW_CLIP_FILL_MODE_LINE = 0,
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BRW_CLIP_FILL_MODE_POINT = 1,
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BRW_CLIP_FILL_MODE_FILL = 2,
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BRW_CLIP_FILL_MODE_CULL = 3,
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/* Note that if unfilled primitives are being emitted, we have to fix
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* up polygon offset and flatshading at this point:
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struct brw_clip_prog_key {
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bool contains_flat_varying;
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bool contains_noperspective_varying;
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unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
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unsigned primitive:4;
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unsigned nr_userclip:4;
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enum brw_clip_fill_mode fill_cw:2; /* includes cull information */
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enum brw_clip_fill_mode fill_ccw:2; /* includes cull information */
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enum brw_clip_mode clip_mode:3;
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/* A big lookup table is used to figure out which and how many
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* additional regs will inserted before the main payload in the WM
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* program execution. These mainly relate to depth and stencil
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* processing and the early-depth-test optimization.
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enum brw_wm_iz_bits {
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BRW_WM_IZ_PS_KILL_ALPHATEST_BIT = 0x1,
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BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT = 0x2,
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BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT = 0x4,
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BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT = 0x8,
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BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT = 0x10,
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BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT = 0x20,
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BRW_WM_IZ_BIT_MAX = 0x40
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enum brw_wm_aa_enable {
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/** The program key for Fragment/Pixel Shaders. */
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struct brw_wm_prog_key {
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struct brw_base_prog_key base;
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/* Some collection of BRW_WM_IZ_* */
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unsigned nr_color_regions:5;
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bool emit_alpha_test:1;
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enum compare_func alpha_test_func:3; /* < For Gfx4/5 MRT alpha test */
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bool alpha_test_replicate_alpha:1;
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bool alpha_to_coverage:1;
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bool clamp_fragment_color:1;
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bool persample_interp:1;
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bool multisample_fbo:1;
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enum brw_wm_aa_enable line_aa:2;
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bool force_dual_color_blend:1;
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bool coherent_fb_fetch:1;
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bool ignore_sample_mask_out:1;
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uint8_t color_outputs_valid;
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uint64_t input_slots_valid;
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float alpha_test_ref;
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struct brw_cs_prog_key {
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struct brw_base_prog_key base;
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struct brw_bs_prog_key {
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struct brw_base_prog_key base;
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struct brw_ff_gs_prog_key {
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* Hardware primitive type being drawn, e.g. _3DPRIM_TRILIST.
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unsigned primitive:8;
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unsigned need_gs_prog:1;
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* Number of varyings that are output to transform feedback.
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unsigned num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
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* Map from the index of a transform feedback binding table entry to the
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* gl_varying_slot that should be streamed out through that binding table
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unsigned char transform_feedback_bindings[BRW_MAX_SOL_BINDINGS];
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* Map from the index of a transform feedback binding table entry to the
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* swizzles that should be used when streaming out data through that
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* binding table entry.
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unsigned char transform_feedback_swizzles[BRW_MAX_SOL_BINDINGS];
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/* brw_any_prog_key is any of the keys that map to an API stage */
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union brw_any_prog_key {
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struct brw_base_prog_key base;
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struct brw_vs_prog_key vs;
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struct brw_tcs_prog_key tcs;
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struct brw_tes_prog_key tes;
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struct brw_gs_prog_key gs;
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struct brw_wm_prog_key wm;
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struct brw_cs_prog_key cs;
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struct brw_bs_prog_key bs;
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struct brw_task_prog_key task;
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struct brw_mesh_prog_key mesh;
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* Image metadata structure as laid out in the shader parameter
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* buffer. Entries have to be 16B-aligned for the vec4 back-end to be
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* able to use them. That's okay because the padding and any unused
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* entries [most of them except when we're doing untyped surface
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* access] will be removed by the uniform packing pass.
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#define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
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#define BRW_IMAGE_PARAM_SIZE_OFFSET 4
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#define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
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#define BRW_IMAGE_PARAM_TILING_OFFSET 12
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#define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
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#define BRW_IMAGE_PARAM_SIZE 20
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struct brw_image_param {
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/** Offset applied to the X and Y surface coordinates. */
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/** Surface X, Y and Z dimensions. */
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/** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
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* pixels, vertical slice stride in pixels.
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/** Log2 of the tiling modulus in the X, Y and Z dimension. */
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* Right shift to apply for bit 6 address swizzling. Two different
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* swizzles can be specified and will be applied one after the other. The
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* resulting address will be:
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* addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
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* (addr >> swizzling[1])))
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* Use \c 0xff if any of the swizzles is not required.
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uint32_t swizzling[2];
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/** Max number of render targets in a shader */
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#define BRW_MAX_DRAW_BUFFERS 8
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* Binding table index for the first gfx6 SOL binding.
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#define BRW_GFX6_SOL_BINDING_START 0
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/* We reserve the first 2^16 values for builtins */
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#define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
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enum brw_param_builtin {
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BRW_PARAM_BUILTIN_ZERO,
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BRW_PARAM_BUILTIN_CLIP_PLANE_0_X,
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BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y,
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BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z,
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BRW_PARAM_BUILTIN_CLIP_PLANE_0_W,
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BRW_PARAM_BUILTIN_CLIP_PLANE_1_X,
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BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y,
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BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z,
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BRW_PARAM_BUILTIN_CLIP_PLANE_1_W,
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BRW_PARAM_BUILTIN_CLIP_PLANE_2_X,
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BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y,
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BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z,
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BRW_PARAM_BUILTIN_CLIP_PLANE_2_W,
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BRW_PARAM_BUILTIN_CLIP_PLANE_3_X,
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BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y,
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BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z,
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BRW_PARAM_BUILTIN_CLIP_PLANE_3_W,
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BRW_PARAM_BUILTIN_CLIP_PLANE_4_X,
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BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y,
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BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z,
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BRW_PARAM_BUILTIN_CLIP_PLANE_4_W,
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BRW_PARAM_BUILTIN_CLIP_PLANE_5_X,
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BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y,
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BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z,
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BRW_PARAM_BUILTIN_CLIP_PLANE_5_W,
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BRW_PARAM_BUILTIN_CLIP_PLANE_6_X,
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BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y,
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BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z,
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BRW_PARAM_BUILTIN_CLIP_PLANE_6_W,
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BRW_PARAM_BUILTIN_CLIP_PLANE_7_X,
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BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y,
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BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z,
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BRW_PARAM_BUILTIN_CLIP_PLANE_7_W,
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BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X,
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BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y,
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BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z,
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BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W,
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BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X,
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BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y,
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BRW_PARAM_BUILTIN_PATCH_VERTICES_IN,
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BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X,
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BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y,
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BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z,
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BRW_PARAM_BUILTIN_SUBGROUP_ID,
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BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X,
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BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Y,
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BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z,
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BRW_PARAM_BUILTIN_WORK_DIM,
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#define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
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(BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
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#define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
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((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
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(param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
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#define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
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(((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
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#define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
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(((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
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enum brw_shader_reloc_id {
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BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW,
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BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH,
701
BRW_SHADER_RELOC_SHADER_START_OFFSET,
702
BRW_SHADER_RELOC_RESUME_SBT_ADDR_LOW,
703
BRW_SHADER_RELOC_RESUME_SBT_ADDR_HIGH,
706
enum brw_shader_reloc_type {
707
/** An arbitrary 32-bit value */
708
BRW_SHADER_RELOC_TYPE_U32,
709
/** A MOV instruction with an immediate source */
710
BRW_SHADER_RELOC_TYPE_MOV_IMM,
713
/** Represents a code relocation
715
* Relocatable constants are immediates in the code which we want to be able
716
* to replace post-compile with the actual value.
718
struct brw_shader_reloc {
719
/** The 32-bit ID of the relocatable constant */
722
/** Type of this relocation */
723
enum brw_shader_reloc_type type;
725
/** The offset in the shader to the relocated value
727
* For MOV_IMM relocs, this is an offset to the MOV instruction. This
728
* allows us to do some sanity checking while we update the value.
732
/** Value to be added to the relocated value before it is written */
736
/** A value to write to a relocation */
737
struct brw_shader_reloc_value {
738
/** The 32-bit ID of the relocatable constant */
741
/** The value with which to replace the relocated immediate */
745
struct brw_stage_prog_data {
746
struct brw_ubo_range ubo_ranges[4];
748
unsigned nr_params; /**< number of float params/constants */
750
gl_shader_stage stage;
752
/* zero_push_reg is a bitfield which indicates what push registers (if any)
753
* should be zeroed by SW at the start of the shader. The corresponding
754
* push_reg_mask_param specifies the param index (in 32-bit units) where
755
* the actual runtime 64-bit mask will be pushed. The shader will zero
758
* reg_used & zero_push_reg & ~*push_reg_mask_param & (1ull << i)
760
* If this field is set, brw_compiler::compact_params must be false.
762
uint64_t zero_push_reg;
763
unsigned push_reg_mask_param;
765
unsigned curb_read_length;
766
unsigned total_scratch;
767
unsigned total_shared;
769
unsigned program_size;
771
unsigned const_data_size;
772
unsigned const_data_offset;
775
const struct brw_shader_reloc *relocs;
777
/** Does this program pull from any UBO or other constant buffers? */
780
/** How many ray queries objects in this shader. */
781
unsigned ray_queries;
784
* Register where the thread expects to find input data from the URB
785
* (typically uniforms, followed by vertex or fragment attributes).
787
unsigned dispatch_grf_start_reg;
789
bool use_alt_mode; /**< Use ALT floating point mode? Otherwise, IEEE. */
791
/* 32-bit identifiers for all push/pull parameters. These can be anything
792
* the driver wishes them to be; the core of the back-end compiler simply
793
* re-arranges them. The one restriction is that the bottom 2^16 values
794
* are reserved for builtins defined in the brw_param_builtin enum defined
799
/* Whether shader uses atomic operations. */
800
bool uses_atomic_load_store;
803
static inline uint32_t *
804
brw_stage_prog_data_add_params(struct brw_stage_prog_data *prog_data,
805
unsigned nr_new_params)
807
unsigned old_nr_params = prog_data->nr_params;
808
prog_data->nr_params += nr_new_params;
809
prog_data->param = reralloc(ralloc_parent(prog_data->param),
810
prog_data->param, uint32_t,
811
prog_data->nr_params);
812
return prog_data->param + old_nr_params;
815
enum brw_barycentric_mode {
816
BRW_BARYCENTRIC_PERSPECTIVE_PIXEL = 0,
817
BRW_BARYCENTRIC_PERSPECTIVE_CENTROID = 1,
818
BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE = 2,
819
BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL = 3,
820
BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
821
BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE = 5,
822
BRW_BARYCENTRIC_MODE_COUNT = 6
824
#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
825
((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
826
(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
827
(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
829
enum brw_pixel_shader_computed_depth_mode {
830
BRW_PSCDEPTH_OFF = 0, /* PS does not compute depth */
831
BRW_PSCDEPTH_ON = 1, /* PS computes depth; no guarantee about value */
832
BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
833
BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
836
/* Data about a particular attempt to compile a program. Note that
837
* there can be many of these, each in a different GL state
838
* corresponding to a different brw_wm_prog_key struct, with different
841
struct brw_wm_prog_data {
842
struct brw_stage_prog_data base;
844
unsigned num_per_primitive_inputs;
845
unsigned num_varying_inputs;
847
uint8_t reg_blocks_8;
848
uint8_t reg_blocks_16;
849
uint8_t reg_blocks_32;
851
uint8_t dispatch_grf_start_reg_16;
852
uint8_t dispatch_grf_start_reg_32;
853
uint32_t prog_offset_16;
854
uint32_t prog_offset_32;
858
* surface indices the WM-specific surfaces
860
uint32_t render_target_read_start;
864
uint8_t color_outputs_written;
865
uint8_t computed_depth_mode;
866
bool computed_stencil;
868
bool early_fragment_tests;
869
bool post_depth_coverage;
875
bool persample_dispatch;
876
bool uses_pos_offset;
881
bool uses_depth_w_coefficients;
882
bool uses_sample_mask;
883
bool has_render_target_reads;
884
bool has_side_effects;
887
bool contains_flat_varying;
888
bool contains_noperspective_varying;
891
* Shader is ran at the coarse pixel shading dispatch rate (3DSTATE_CPS).
893
bool per_coarse_pixel_dispatch;
896
* Mask of which interpolation modes are required by the fragment shader.
897
* Used in hardware setup on gfx6+.
899
uint32_t barycentric_interp_modes;
902
* Mask of which FS inputs are marked flat by the shader source. This is
903
* needed for setting up 3DSTATE_SF/SBE.
905
uint32_t flat_inputs;
912
/* Mapping of VUE slots to interpolation modes.
913
* Used by the Gfx4-5 clip/sf/wm stages.
915
unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
918
* Map from gl_varying_slot to the position within the FS setup data
919
* payload where the varying's attribute vertex deltas should be delivered.
920
* For varying slots that are not used by the FS, the value is -1.
922
int urb_setup[VARYING_SLOT_MAX];
925
* Cache structure into the urb_setup array above that contains the
926
* attribute numbers of active varyings out of urb_setup.
927
* The actual count is stored in urb_setup_attribs_count.
929
uint8_t urb_setup_attribs[VARYING_SLOT_MAX];
930
uint8_t urb_setup_attribs_count;
933
/** Returns the SIMD width corresponding to a given KSP index
935
* The "Variable Pixel Dispatch" table in the PRM (which can be found, for
936
* example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
937
* kernel start pointer (KSP) indices that is based on what dispatch widths
938
* are enabled. This function provides, effectively, the reverse mapping.
940
* If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
941
* width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
943
static inline unsigned
944
brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled,
945
bool simd16_enabled, bool simd32_enabled)
947
/* This function strictly ignores contiguous dispatch */
950
return simd8_enabled ? 8 :
951
(simd16_enabled && !simd32_enabled) ? 16 :
952
(simd32_enabled && !simd16_enabled) ? 32 : 0;
954
return (simd32_enabled && (simd16_enabled || simd8_enabled)) ? 32 : 0;
956
return (simd16_enabled && (simd32_enabled || simd8_enabled)) ? 16 : 0;
958
unreachable("Invalid KSP index");
962
#define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
963
brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
964
(wm_state)._16PixelDispatchEnable, \
965
(wm_state)._32PixelDispatchEnable)
967
#define brw_wm_state_has_ksp(wm_state, ksp_idx) \
968
(brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
970
static inline uint32_t
971
_brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data *prog_data,
974
switch (simd_width) {
976
case 16: return prog_data->prog_offset_16;
977
case 32: return prog_data->prog_offset_32;
982
#define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
983
_brw_wm_prog_data_prog_offset(prog_data, \
984
brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
986
static inline uint8_t
987
_brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_data,
990
switch (simd_width) {
991
case 8: return prog_data->base.dispatch_grf_start_reg;
992
case 16: return prog_data->dispatch_grf_start_reg_16;
993
case 32: return prog_data->dispatch_grf_start_reg_32;
998
#define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
999
_brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
1000
brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
1002
static inline uint8_t
1003
_brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data,
1004
unsigned simd_width)
1006
switch (simd_width) {
1007
case 8: return prog_data->reg_blocks_8;
1008
case 16: return prog_data->reg_blocks_16;
1009
case 32: return prog_data->reg_blocks_32;
1014
#define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
1015
_brw_wm_prog_data_reg_blocks(prog_data, \
1016
brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
1018
struct brw_push_const_block {
1019
unsigned dwords; /* Dword count, not reg aligned */
1021
unsigned size; /* Bytes, register aligned */
1024
struct brw_cs_prog_data {
1025
struct brw_stage_prog_data base;
1027
unsigned local_size[3];
1029
/* Program offsets for the 8/16/32 SIMD variants. Multiple variants are
1030
* kept when using variable group size, and the right one can only be
1031
* decided at dispatch time.
1033
unsigned prog_offset[3];
1035
/* Bitmask indicating which program offsets are valid. */
1038
/* Bitmask indicating which programs have spilled. */
1039
unsigned prog_spilled;
1042
bool uses_num_work_groups;
1043
bool uses_inline_data;
1044
bool uses_btd_stack_ids;
1047
struct brw_push_const_block cross_thread;
1048
struct brw_push_const_block per_thread;
1053
* surface indices the CS-specific surfaces
1055
uint32_t work_groups_start;
1060
static inline uint32_t
1061
brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data *prog_data,
1062
unsigned dispatch_width)
1064
assert(dispatch_width == 8 ||
1065
dispatch_width == 16 ||
1066
dispatch_width == 32);
1067
const unsigned index = dispatch_width / 16;
1068
assert(prog_data->prog_mask & (1 << index));
1069
return prog_data->prog_offset[index];
1072
struct brw_bs_prog_data {
1073
struct brw_stage_prog_data base;
1075
/** SIMD size of the root shader */
1078
/** Maximum stack size of all shaders */
1079
uint32_t max_stack_size;
1081
/** Offset into the shader where the resume SBT is located */
1082
uint32_t resume_sbt_offset;
1085
struct brw_ff_gs_prog_data {
1086
unsigned urb_read_length;
1090
* Gfx6 transform feedback: Amount by which the streaming vertex buffer
1091
* indices should be incremented each time the GS is invoked.
1093
unsigned svbi_postincrement_value;
1097
* Enum representing the i965-specific vertex results that don't correspond
1098
* exactly to any element of gl_varying_slot. The values of this enum are
1099
* assigned such that they don't conflict with gl_varying_slot.
1103
BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
1104
BRW_VARYING_SLOT_PAD,
1106
* Technically this is not a varying but just a placeholder that
1107
* compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
1108
* builtin variable to be compiled correctly. see compile_sf_prog() for
1111
BRW_VARYING_SLOT_PNTC,
1112
BRW_VARYING_SLOT_COUNT
1116
* We always program SF to start reading at an offset of 1 (2 varying slots)
1117
* from the start of the vertex URB entry. This causes it to skip:
1118
* - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gfx4-5
1119
* - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gfx6+
1121
#define BRW_SF_URB_ENTRY_READ_OFFSET 1
1124
* Bitmask indicating which fragment shader inputs represent varyings (and
1125
* hence have to be delivered to the fragment shader by the SF/SBE stage).
1127
#define BRW_FS_VARYING_INPUT_MASK \
1128
(BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
1129
~VARYING_BIT_POS & ~VARYING_BIT_FACE)
1132
* Data structure recording the relationship between the gl_varying_slot enum
1133
* and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
1134
* single octaword within the VUE (128 bits).
1136
* Note that each BRW register contains 256 bits (2 octawords), so when
1137
* accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
1138
* consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
1139
* in a vertex shader), each register corresponds to a single VUE slot, since
1140
* it contains data for two separate vertices.
1142
struct brw_vue_map {
1144
* Bitfield representing all varying slots that are (a) stored in this VUE
1145
* map, and (b) actually written by the shader. Does not include any of
1146
* the additional varying slots defined in brw_varying_slot.
1148
uint64_t slots_valid;
1151
* Is this VUE map for a separate shader pipeline?
1153
* Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
1154
* without the linker having a chance to dead code eliminate unused varyings.
1156
* This means that we have to use a fixed slot layout, based on the output's
1157
* location field, rather than assigning slots in a compact contiguous block.
1162
* Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
1163
* not stored in a slot (because they are not written, or because
1164
* additional processing is applied before storing them in the VUE), the
1167
signed char varying_to_slot[VARYING_SLOT_TESS_MAX];
1170
* Map from VUE slot to gl_varying_slot value. For slots that do not
1171
* directly correspond to a gl_varying_slot, the value comes from
1174
* For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
1176
signed char slot_to_varying[VARYING_SLOT_TESS_MAX];
1179
* Total number of VUE slots in use
1184
* Number of per-patch VUE slots. Only valid for tessellation control
1185
* shader outputs and tessellation evaluation shader inputs.
1187
int num_per_patch_slots;
1190
* Number of per-vertex VUE slots. Only valid for tessellation control
1191
* shader outputs and tessellation evaluation shader inputs.
1193
int num_per_vertex_slots;
1196
void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map,
1197
gl_shader_stage stage);
1200
* Convert a VUE slot number into a byte offset within the VUE.
1202
static inline unsigned brw_vue_slot_to_offset(unsigned slot)
1208
* Convert a vertex output (brw_varying_slot) into a byte offset within the
1211
static inline unsigned
1212
brw_varying_to_offset(const struct brw_vue_map *vue_map, unsigned varying)
1214
return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
1217
void brw_compute_vue_map(const struct intel_device_info *devinfo,
1218
struct brw_vue_map *vue_map,
1219
uint64_t slots_valid,
1220
bool separate_shader,
1221
uint32_t pos_slots);
1223
void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
1224
uint64_t slots_valid,
1227
/* brw_interpolation_map.c */
1228
void brw_setup_vue_interpolation(const struct brw_vue_map *vue_map,
1229
struct nir_shader *nir,
1230
struct brw_wm_prog_data *prog_data);
1232
enum shader_dispatch_mode {
1233
DISPATCH_MODE_4X1_SINGLE = 0,
1234
DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
1235
DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
1236
DISPATCH_MODE_SIMD8 = 3,
1238
DISPATCH_MODE_TCS_SINGLE_PATCH = 0,
1239
DISPATCH_MODE_TCS_8_PATCH = 2,
1243
* @defgroup Tessellator parameter enumerations.
1245
* These correspond to the hardware values in 3DSTATE_TE, and are provided
1246
* as part of the tessellation evaluation shader.
1250
enum brw_tess_partitioning {
1251
BRW_TESS_PARTITIONING_INTEGER = 0,
1252
BRW_TESS_PARTITIONING_ODD_FRACTIONAL = 1,
1253
BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2,
1256
enum brw_tess_output_topology {
1257
BRW_TESS_OUTPUT_TOPOLOGY_POINT = 0,
1258
BRW_TESS_OUTPUT_TOPOLOGY_LINE = 1,
1259
BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW = 2,
1260
BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3,
1263
enum brw_tess_domain {
1264
BRW_TESS_DOMAIN_QUAD = 0,
1265
BRW_TESS_DOMAIN_TRI = 1,
1266
BRW_TESS_DOMAIN_ISOLINE = 2,
1270
struct brw_vue_prog_data {
1271
struct brw_stage_prog_data base;
1272
struct brw_vue_map vue_map;
1274
/** Should the hardware deliver input VUE handles for URB pull loads? */
1275
bool include_vue_handles;
1277
unsigned urb_read_length;
1280
uint32_t clip_distance_mask;
1281
uint32_t cull_distance_mask;
1283
/* Used for calculating urb partitions. In the VS, this is the size of the
1284
* URB entry used for both input and output to the thread. In the GS, this
1285
* is the size of the URB entry used for output.
1287
unsigned urb_entry_size;
1289
enum shader_dispatch_mode dispatch_mode;
1292
struct brw_vs_prog_data {
1293
struct brw_vue_prog_data base;
1295
uint64_t inputs_read;
1296
uint64_t double_inputs_read;
1298
unsigned nr_attribute_slots;
1301
bool uses_instanceid;
1302
bool uses_is_indexed_draw;
1303
bool uses_firstvertex;
1304
bool uses_baseinstance;
1308
struct brw_tcs_prog_data
1310
struct brw_vue_prog_data base;
1312
/** Should the non-SINGLE_PATCH payload provide primitive ID? */
1313
bool include_primitive_id;
1315
/** Number vertices in output patch */
1318
/** Track patch count threshold */
1319
int patch_count_threshold;
1323
struct brw_tes_prog_data
1325
struct brw_vue_prog_data base;
1327
enum brw_tess_partitioning partitioning;
1328
enum brw_tess_output_topology output_topology;
1329
enum brw_tess_domain domain;
1330
bool include_primitive_id;
1333
struct brw_gs_prog_data
1335
struct brw_vue_prog_data base;
1337
unsigned vertices_in;
1340
* Size of an output vertex, measured in HWORDS (32 bytes).
1342
unsigned output_vertex_size_hwords;
1344
unsigned output_topology;
1347
* Size of the control data (cut bits or StreamID bits), in hwords (32
1348
* bytes). 0 if there is no control data.
1350
unsigned control_data_header_size_hwords;
1353
* Format of the control data (either GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1354
* if the control data is StreamID bits, or
1355
* GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1356
* Ignored if control_data_header_size is 0.
1358
unsigned control_data_format;
1360
bool include_primitive_id;
1363
* The number of vertices emitted, if constant - otherwise -1.
1365
int static_vertex_count;
1370
* Gfx6: Provoking vertex convention for odd-numbered triangles
1373
unsigned pv_first:1;
1376
* Gfx6: Number of varyings that are output to transform feedback.
1378
unsigned num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
1381
* Gfx6: Map from the index of a transform feedback binding table entry to the
1382
* gl_varying_slot that should be streamed out through that binding table
1385
unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */];
1388
* Gfx6: Map from the index of a transform feedback binding table entry to the
1389
* swizzles that should be used when streaming out data through that
1390
* binding table entry.
1392
unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
1395
struct brw_sf_prog_data {
1396
uint32_t urb_read_length;
1399
/* Each vertex may have upto 12 attributes, 4 components each,
1400
* except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1403
* Actually we use 4 for each, so call it 12 rows.
1405
unsigned urb_entry_size;
1408
struct brw_clip_prog_data {
1409
uint32_t curb_read_length; /* user planes? */
1411
uint32_t urb_read_length;
1415
struct brw_tue_map {
1418
uint32_t per_task_data_start_dw;
1421
struct brw_mue_map {
1422
int32_t start_dw[VARYING_SLOT_MAX];
1426
uint32_t max_primitives;
1427
uint32_t per_primitive_start_dw;
1428
uint32_t per_primitive_header_size_dw;
1429
uint32_t per_primitive_data_size_dw;
1430
uint32_t per_primitive_pitch_dw;
1432
uint32_t max_vertices;
1433
uint32_t per_vertex_start_dw;
1434
uint32_t per_vertex_header_size_dw;
1435
uint32_t per_vertex_data_size_dw;
1436
uint32_t per_vertex_pitch_dw;
1439
struct brw_task_prog_data {
1440
struct brw_cs_prog_data base;
1441
struct brw_tue_map map;
1445
enum brw_mesh_index_format {
1446
BRW_INDEX_FORMAT_U32,
1449
struct brw_mesh_prog_data {
1450
struct brw_cs_prog_data base;
1451
struct brw_mue_map map;
1453
uint32_t clip_distance_mask;
1454
uint32_t cull_distance_mask;
1455
uint16_t primitive_type;
1457
enum brw_mesh_index_format index_format;
1462
/* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1463
union brw_any_prog_data {
1464
struct brw_stage_prog_data base;
1465
struct brw_vue_prog_data vue;
1466
struct brw_vs_prog_data vs;
1467
struct brw_tcs_prog_data tcs;
1468
struct brw_tes_prog_data tes;
1469
struct brw_gs_prog_data gs;
1470
struct brw_wm_prog_data wm;
1471
struct brw_cs_prog_data cs;
1472
struct brw_bs_prog_data bs;
1473
struct brw_task_prog_data task;
1474
struct brw_mesh_prog_data mesh;
1477
#define DEFINE_PROG_DATA_DOWNCAST(STAGE, CHECK) \
1478
static inline struct brw_##STAGE##_prog_data * \
1479
brw_##STAGE##_prog_data(struct brw_stage_prog_data *prog_data) \
1483
return (struct brw_##STAGE##_prog_data *) prog_data; \
1485
static inline const struct brw_##STAGE##_prog_data * \
1486
brw_##STAGE##_prog_data_const(const struct brw_stage_prog_data *prog_data) \
1490
return (const struct brw_##STAGE##_prog_data *) prog_data; \
1493
DEFINE_PROG_DATA_DOWNCAST(vs, prog_data->stage == MESA_SHADER_VERTEX)
1494
DEFINE_PROG_DATA_DOWNCAST(tcs, prog_data->stage == MESA_SHADER_TESS_CTRL)
1495
DEFINE_PROG_DATA_DOWNCAST(tes, prog_data->stage == MESA_SHADER_TESS_EVAL)
1496
DEFINE_PROG_DATA_DOWNCAST(gs, prog_data->stage == MESA_SHADER_GEOMETRY)
1497
DEFINE_PROG_DATA_DOWNCAST(wm, prog_data->stage == MESA_SHADER_FRAGMENT)
1498
DEFINE_PROG_DATA_DOWNCAST(cs, gl_shader_stage_uses_workgroup(prog_data->stage))
1499
DEFINE_PROG_DATA_DOWNCAST(bs, brw_shader_stage_is_bindless(prog_data->stage))
1501
DEFINE_PROG_DATA_DOWNCAST(vue, prog_data->stage == MESA_SHADER_VERTEX ||
1502
prog_data->stage == MESA_SHADER_TESS_CTRL ||
1503
prog_data->stage == MESA_SHADER_TESS_EVAL ||
1504
prog_data->stage == MESA_SHADER_GEOMETRY)
1506
DEFINE_PROG_DATA_DOWNCAST(task, prog_data->stage == MESA_SHADER_TASK)
1507
DEFINE_PROG_DATA_DOWNCAST(mesh, prog_data->stage == MESA_SHADER_MESH)
1509
/* These are not really brw_stage_prog_data. */
1510
DEFINE_PROG_DATA_DOWNCAST(ff_gs, true)
1511
DEFINE_PROG_DATA_DOWNCAST(clip, true)
1512
DEFINE_PROG_DATA_DOWNCAST(sf, true)
1513
#undef DEFINE_PROG_DATA_DOWNCAST
1515
struct brw_compile_stats {
1516
uint32_t dispatch_width; /**< 0 for vec4 */
1517
uint32_t instructions;
1527
struct brw_compiler *
1528
brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo);
1531
* Returns a compiler configuration for use with disk shader cache
1533
* This value only needs to change for settings that can cause different
1534
* program generation between two runs on the same hardware.
1536
* For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1537
* but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1540
brw_get_compiler_config_value(const struct brw_compiler *compiler);
1543
brw_prog_data_size(gl_shader_stage stage);
1546
brw_prog_key_size(gl_shader_stage stage);
1549
brw_prog_key_set_id(union brw_any_prog_key *key, gl_shader_stage, unsigned id);
1552
* Parameters for compiling a vertex shader.
1554
* Some of these will be modified during the shader compilation.
1556
struct brw_compile_vs_params {
1559
const struct brw_vs_prog_key *key;
1560
struct brw_vs_prog_data *prog_data;
1562
bool edgeflag_is_last; /* true for gallium */
1564
struct brw_compile_stats *stats;
1570
/* If unset, DEBUG_VS is used. */
1571
uint64_t debug_flag;
1575
* Compile a vertex shader.
1577
* Returns the final assembly and updates the parameters structure.
1580
brw_compile_vs(const struct brw_compiler *compiler,
1582
struct brw_compile_vs_params *params);
1585
* Parameters for compiling a tessellation control shader.
1587
* Some of these will be modified during the shader compilation.
1589
struct brw_compile_tcs_params {
1592
const struct brw_tcs_prog_key *key;
1593
struct brw_tcs_prog_data *prog_data;
1595
struct brw_compile_stats *stats;
1603
* Compile a tessellation control shader.
1605
* Returns the final assembly and updates the parameters structure.
1608
brw_compile_tcs(const struct brw_compiler *compiler,
1610
struct brw_compile_tcs_params *params);
1613
* Parameters for compiling a tessellation evaluation shader.
1615
* Some of these will be modified during the shader compilation.
1617
struct brw_compile_tes_params {
1620
const struct brw_tes_prog_key *key;
1621
struct brw_tes_prog_data *prog_data;
1622
const struct brw_vue_map *input_vue_map;
1624
struct brw_compile_stats *stats;
1632
* Compile a tessellation evaluation shader.
1634
* Returns the final assembly and updates the parameters structure.
1637
brw_compile_tes(const struct brw_compiler *compiler,
1639
struct brw_compile_tes_params *params);
1642
* Parameters for compiling a geometry shader.
1644
* Some of these will be modified during the shader compilation.
1646
struct brw_compile_gs_params {
1649
const struct brw_gs_prog_key *key;
1650
struct brw_gs_prog_data *prog_data;
1652
struct brw_compile_stats *stats;
1660
* Compile a geometry shader.
1662
* Returns the final assembly and updates the parameters structure.
1665
brw_compile_gs(const struct brw_compiler *compiler,
1667
struct brw_compile_gs_params *params);
1670
* Compile a strips and fans shader.
1672
* This is a fixed-function shader determined entirely by the shader key and
1675
* Returns the final assembly and the program's size.
1678
brw_compile_sf(const struct brw_compiler *compiler,
1680
const struct brw_sf_prog_key *key,
1681
struct brw_sf_prog_data *prog_data,
1682
struct brw_vue_map *vue_map,
1683
unsigned *final_assembly_size);
1686
* Compile a clipper shader.
1688
* This is a fixed-function shader determined entirely by the shader key and
1691
* Returns the final assembly and the program's size.
1694
brw_compile_clip(const struct brw_compiler *compiler,
1696
const struct brw_clip_prog_key *key,
1697
struct brw_clip_prog_data *prog_data,
1698
struct brw_vue_map *vue_map,
1699
unsigned *final_assembly_size);
1701
struct brw_compile_task_params {
1702
struct nir_shader *nir;
1704
const struct brw_task_prog_key *key;
1705
struct brw_task_prog_data *prog_data;
1707
struct brw_compile_stats *stats;
1714
brw_compile_task(const struct brw_compiler *compiler,
1716
struct brw_compile_task_params *params);
1718
struct brw_compile_mesh_params {
1719
struct nir_shader *nir;
1721
const struct brw_mesh_prog_key *key;
1722
struct brw_mesh_prog_data *prog_data;
1723
const struct brw_tue_map *tue_map;
1725
struct brw_compile_stats *stats;
1732
brw_compile_mesh(const struct brw_compiler *compiler,
1734
struct brw_compile_mesh_params *params);
1737
* Parameters for compiling a fragment shader.
1739
* Some of these will be modified during the shader compilation.
1741
struct brw_compile_fs_params {
1744
const struct brw_wm_prog_key *key;
1745
struct brw_wm_prog_data *prog_data;
1747
const struct brw_vue_map *vue_map;
1748
const struct brw_mue_map *mue_map;
1750
bool allow_spilling;
1753
struct brw_compile_stats *stats;
1759
/* If unset, DEBUG_WM is used. */
1760
uint64_t debug_flag;
1764
* Compile a fragment shader.
1766
* Returns the final assembly and updates the parameters structure.
1769
brw_compile_fs(const struct brw_compiler *compiler,
1771
struct brw_compile_fs_params *params);
1774
* Parameters for compiling a compute shader.
1776
* Some of these will be modified during the shader compilation.
1778
struct brw_compile_cs_params {
1781
const struct brw_cs_prog_key *key;
1782
struct brw_cs_prog_data *prog_data;
1784
struct brw_compile_stats *stats;
1790
/* If unset, DEBUG_CS is used. */
1791
uint64_t debug_flag;
1795
* Compile a compute shader.
1797
* Returns the final assembly and updates the parameters structure.
1800
brw_compile_cs(const struct brw_compiler *compiler,
1802
struct brw_compile_cs_params *params);
1805
* Parameters for compiling a Bindless shader.
1807
* Some of these will be modified during the shader compilation.
1809
struct brw_compile_bs_params {
1812
const struct brw_bs_prog_key *key;
1813
struct brw_bs_prog_data *prog_data;
1815
unsigned num_resume_shaders;
1816
struct nir_shader **resume_shaders;
1818
struct brw_compile_stats *stats;
1826
* Compile a Bindless shader.
1828
* Returns the final assembly and updates the parameters structure.
1831
brw_compile_bs(const struct brw_compiler *compiler,
1833
struct brw_compile_bs_params *params);
1836
* Compile a fixed function geometry shader.
1838
* Returns the final assembly and the program's size.
1841
brw_compile_ff_gs_prog(struct brw_compiler *compiler,
1843
const struct brw_ff_gs_prog_key *key,
1844
struct brw_ff_gs_prog_data *prog_data,
1845
struct brw_vue_map *vue_map,
1846
unsigned *final_assembly_size);
1848
void brw_debug_key_recompile(const struct brw_compiler *c, void *log,
1849
gl_shader_stage stage,
1850
const struct brw_base_prog_key *old_key,
1851
const struct brw_base_prog_key *key);
1853
/* Shared Local Memory Size is specified as powers of two,
1854
* and also have a Gen-dependent minimum value if not zero.
1856
static inline uint32_t
1857
intel_calculate_slm_size(unsigned gen, uint32_t bytes)
1859
assert(bytes <= 64 * 1024);
1861
return MAX2(util_next_power_of_two(bytes), gen >= 9 ? 1024 : 4096);
1866
static inline uint32_t
1867
encode_slm_size(unsigned gen, uint32_t bytes)
1869
uint32_t slm_size = 0;
1871
/* Shared Local Memory is specified as powers of two, and encoded in
1872
* INTERFACE_DESCRIPTOR_DATA with the following representations:
1874
* Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1875
* -------------------------------------------------------------------
1876
* Gfx7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1877
* -------------------------------------------------------------------
1878
* Gfx9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1882
slm_size = intel_calculate_slm_size(gen, bytes);
1883
assert(util_is_power_of_two_nonzero(slm_size));
1886
/* Turn an exponent of 10 (1024 kB) into 1. */
1887
assert(slm_size >= 1024);
1888
slm_size = ffs(slm_size) - 10;
1890
assert(slm_size >= 4096);
1891
/* Convert to the pre-Gfx9 representation. */
1892
slm_size = slm_size / 4096;
1900
brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data,
1904
brw_write_shader_relocs(const struct intel_device_info *devinfo,
1906
const struct brw_stage_prog_data *prog_data,
1907
struct brw_shader_reloc_value *values,
1908
unsigned num_values);
1910
struct brw_cs_dispatch_info {
1911
uint32_t group_size;
1915
/* RightExecutionMask field used in GPGPU_WALKER. */
1916
uint32_t right_mask;
1920
* Get the dispatch information for a shader to be used with GPGPU_WALKER and
1921
* similar instructions.
1923
* If override_local_size is not NULL, it must to point to a 3-element that
1924
* will override the value from prog_data->local_size. This is used by
1925
* ARB_compute_variable_group_size, where the size is set only at dispatch
1926
* time (so prog_data is outdated).
1928
struct brw_cs_dispatch_info
1929
brw_cs_get_dispatch_info(const struct intel_device_info *devinfo,
1930
const struct brw_cs_prog_data *prog_data,
1931
const unsigned *override_local_size);
1934
* Return true if the given shader stage is dispatched contiguously by the
1935
* relevant fixed function starting from channel 0 of the SIMD thread, which
1936
* implies that the dispatch mask of a thread can be assumed to have the form
1937
* '2^n - 1' for some n.
1940
brw_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo,
1941
gl_shader_stage stage,
1942
const struct brw_stage_prog_data *prog_data)
1944
/* The code below makes assumptions about the hardware's thread dispatch
1945
* behavior that could be proven wrong in future generations -- Make sure
1946
* to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1947
* the NIR front-end before changing this assertion.
1949
assert(devinfo->ver <= 12);
1952
case MESA_SHADER_FRAGMENT: {
1953
/* The PSD discards subspans coming in with no lit samples, which in the
1954
* per-pixel shading case implies that each subspan will either be fully
1955
* lit (due to the VMask being used to allow derivative computations),
1956
* or not dispatched at all. In per-sample dispatch mode individual
1957
* samples from the same subspan have a fixed relative location within
1958
* the SIMD thread, so dispatch of unlit samples cannot be avoided in
1959
* general and we should return false.
1961
const struct brw_wm_prog_data *wm_prog_data =
1962
(const struct brw_wm_prog_data *)prog_data;
1963
return devinfo->verx10 < 125 && !wm_prog_data->persample_dispatch;
1965
case MESA_SHADER_COMPUTE:
1966
/* Compute shaders will be spawned with either a fully enabled dispatch
1967
* mask or with whatever bottom/right execution mask was given to the
1968
* GPGPU walker command to be used along the workgroup edges -- In both
1969
* cases the dispatch mask is required to be tightly packed for our
1970
* invocation index calculations to work.
1974
/* Most remaining fixed functions are limited to use a packed dispatch
1975
* mask due to the hardware representation of the dispatch mask as a
1976
* single counter representing the number of enabled channels.
1983
* Computes the first varying slot in the URB produced by the previous stage
1984
* that is used in the next stage. We do this by testing the varying slots in
1985
* the previous stage's vue map against the inputs read in the next stage.
1989
* - Each URB offset contains two varying slots and we can only skip a
1990
* full offset if both slots are unused, so the value we return here is always
1991
* rounded down to the closest multiple of two.
1993
* - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1994
* part of the vue header, so if these are read we can't skip anything.
1997
brw_compute_first_urb_slot_required(uint64_t inputs_read,
1998
const struct brw_vue_map *prev_stage_vue_map)
2000
if ((inputs_read & (VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PRIMITIVE_SHADING_RATE)) == 0) {
2001
for (int i = 0; i < prev_stage_vue_map->num_slots; i++) {
2002
int varying = prev_stage_vue_map->slot_to_varying[i];
2003
if (varying > 0 && (inputs_read & BITFIELD64_BIT(varying)) != 0)
2004
return ROUND_DOWN_TO(i, 2);
2011
/* From InlineData in 3DSTATE_TASK_SHADER_DATA and 3DSTATE_MESH_SHADER_DATA. */
2012
#define BRW_TASK_MESH_INLINE_DATA_SIZE_DW 8
2014
/* InlineData[0-1] is used for Vulkan descriptor. */
2015
#define BRW_TASK_MESH_PUSH_CONSTANTS_START_DW 2
2017
#define BRW_TASK_MESH_PUSH_CONSTANTS_SIZE_DW \
2018
(BRW_TASK_MESH_INLINE_DATA_SIZE_DW - BRW_TASK_MESH_PUSH_CONSTANTS_START_DW)
2021
* This enum is used as the base indice of the nir_load_topology_id_intel
2022
* intrinsic. This is used to return different values based on some aspect of
2023
* the topology of the device.
2025
enum brw_topology_id
2027
/* A value based of the DSS identifier the shader is currently running on.
2028
* Be mindful that the DSS ID can be higher than the total number of DSS on
2029
* the device. This is because of the fusing that can occur on different
2032
BRW_TOPOLOGY_ID_DSS,
2034
/* A value composed of EU ID, thread ID & SIMD lane ID. */
2035
BRW_TOPOLOGY_ID_EU_THREAD_SIMD,
2042
#endif /* BRW_COMPILER_H */
added
removed
src/intel/compiler/brw_compiler.h
