2
* Copyright © 2010 Intel Corporation
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
* copy of this software and associated documentation files (the "Software"),
6
* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
9
* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
15
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26
* This file drives the GLSL IR -> LIR translation, contains the
27
* optimizations on the LIR, and drives the generation of native code
31
#include "main/macros.h"
34
#include "brw_fs_live_variables.h"
36
#include "brw_vec4_gs_visitor.h"
38
#include "brw_dead_control_flow.h"
39
#include "brw_private.h"
40
#include "dev/intel_debug.h"
41
#include "compiler/glsl_types.h"
42
#include "compiler/nir/nir_builder.h"
43
#include "program/prog_parameter.h"
44
#include "util/u_math.h"
48
static unsigned get_lowered_simd_width(const struct intel_device_info *devinfo,
52
fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
53
const fs_reg *src, unsigned sources)
55
memset((void*)this, 0, sizeof(*this));
57
this->src = new fs_reg[MAX2(sources, 3)];
58
for (unsigned i = 0; i < sources; i++)
59
this->src[i] = src[i];
61
this->opcode = opcode;
63
this->sources = sources;
64
this->exec_size = exec_size;
67
assert(dst.file != IMM && dst.file != UNIFORM);
69
assert(this->exec_size != 0);
71
this->conditional_mod = BRW_CONDITIONAL_NONE;
73
/* This will be the case for almost all instructions. */
80
this->size_written = dst.component_size(exec_size);
83
this->size_written = 0;
87
unreachable("Invalid destination register file");
90
this->writes_accumulator = false;
95
init(BRW_OPCODE_NOP, 8, dst, NULL, 0);
98
fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size)
100
init(opcode, exec_size, reg_undef, NULL, 0);
103
fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst)
105
init(opcode, exec_size, dst, NULL, 0);
108
fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
111
const fs_reg src[1] = { src0 };
112
init(opcode, exec_size, dst, src, 1);
115
fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
116
const fs_reg &src0, const fs_reg &src1)
118
const fs_reg src[2] = { src0, src1 };
119
init(opcode, exec_size, dst, src, 2);
122
fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
123
const fs_reg &src0, const fs_reg &src1, const fs_reg &src2)
125
const fs_reg src[3] = { src0, src1, src2 };
126
init(opcode, exec_size, dst, src, 3);
129
fs_inst::fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
130
const fs_reg src[], unsigned sources)
132
init(opcode, exec_width, dst, src, sources);
135
fs_inst::fs_inst(const fs_inst &that)
137
memcpy((void*)this, &that, sizeof(that));
139
this->src = new fs_reg[MAX2(that.sources, 3)];
141
for (unsigned i = 0; i < that.sources; i++)
142
this->src[i] = that.src[i];
151
fs_inst::resize_sources(uint8_t num_sources)
153
if (this->sources != num_sources) {
154
fs_reg *src = new fs_reg[MAX2(num_sources, 3)];
156
for (unsigned i = 0; i < MIN2(this->sources, num_sources); ++i)
157
src[i] = this->src[i];
161
this->sources = num_sources;
166
fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
168
const fs_reg &surf_index,
169
const fs_reg &varying_offset,
170
uint32_t const_offset,
173
/* We have our constant surface use a pitch of 4 bytes, so our index can
174
* be any component of a vector, and then we load 4 contiguous
175
* components starting from that.
177
* We break down the const_offset to a portion added to the variable offset
178
* and a portion done using fs_reg::offset, which means that if you have
179
* GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
180
* we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
181
* later notice that those loads are all the same and eliminate the
184
fs_reg vec4_offset = vgrf(glsl_type::uint_type);
185
bld.ADD(vec4_offset, varying_offset, brw_imm_ud(const_offset & ~0xf));
187
/* The pull load message will load a vec4 (16 bytes). If we are loading
188
* a double this means we are only loading 2 elements worth of data.
189
* We also want to use a 32-bit data type for the dst of the load operation
190
* so other parts of the driver don't get confused about the size of the
193
fs_reg vec4_result = bld.vgrf(BRW_REGISTER_TYPE_F, 4);
194
fs_inst *inst = bld.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
195
vec4_result, surf_index, vec4_offset,
196
brw_imm_ud(alignment));
197
inst->size_written = 4 * vec4_result.component_size(inst->exec_size);
199
shuffle_from_32bit_read(bld, dst, vec4_result,
200
(const_offset & 0xf) / type_sz(dst.type), 1);
204
* A helper for MOV generation for fixing up broken hardware SEND dependency
208
fs_visitor::DEP_RESOLVE_MOV(const fs_builder &bld, int grf)
210
/* The caller always wants uncompressed to emit the minimal extra
211
* dependencies, and to avoid having to deal with aligning its regs to 2.
213
const fs_builder ubld = bld.annotate("send dependency resolve")
216
ubld.MOV(ubld.null_reg_f(), fs_reg(VGRF, grf, BRW_REGISTER_TYPE_F));
220
fs_inst::is_send_from_grf() const
223
case SHADER_OPCODE_SEND:
224
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
225
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
226
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
227
case SHADER_OPCODE_URB_WRITE_SIMD8:
228
case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
229
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
230
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
231
case SHADER_OPCODE_URB_READ_SIMD8:
232
case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
233
case SHADER_OPCODE_INTERLOCK:
234
case SHADER_OPCODE_MEMORY_FENCE:
235
case SHADER_OPCODE_BARRIER:
237
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
238
return src[1].file == VGRF;
239
case FS_OPCODE_FB_WRITE:
240
case FS_OPCODE_FB_READ:
241
return src[0].file == VGRF;
244
return src[0].file == VGRF;
251
fs_inst::is_control_source(unsigned arg) const
254
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
255
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
256
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
259
case SHADER_OPCODE_BROADCAST:
260
case SHADER_OPCODE_SHUFFLE:
261
case SHADER_OPCODE_QUAD_SWIZZLE:
262
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
263
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
264
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
265
case SHADER_OPCODE_GET_BUFFER_SIZE:
268
case SHADER_OPCODE_MOV_INDIRECT:
269
case SHADER_OPCODE_CLUSTER_BROADCAST:
270
case SHADER_OPCODE_TEX:
272
case SHADER_OPCODE_TXD:
273
case SHADER_OPCODE_TXF:
274
case SHADER_OPCODE_TXF_LZ:
275
case SHADER_OPCODE_TXF_CMS:
276
case SHADER_OPCODE_TXF_CMS_W:
277
case SHADER_OPCODE_TXF_UMS:
278
case SHADER_OPCODE_TXF_MCS:
279
case SHADER_OPCODE_TXL:
280
case SHADER_OPCODE_TXL_LZ:
281
case SHADER_OPCODE_TXS:
282
case SHADER_OPCODE_LOD:
283
case SHADER_OPCODE_TG4:
284
case SHADER_OPCODE_TG4_OFFSET:
285
case SHADER_OPCODE_SAMPLEINFO:
286
return arg == 1 || arg == 2;
288
case SHADER_OPCODE_SEND:
289
return arg == 0 || arg == 1;
297
fs_inst::is_payload(unsigned arg) const
300
case FS_OPCODE_FB_WRITE:
301
case FS_OPCODE_FB_READ:
302
case SHADER_OPCODE_URB_WRITE_SIMD8:
303
case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
304
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
305
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
306
case SHADER_OPCODE_URB_READ_SIMD8:
307
case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
308
case VEC4_OPCODE_UNTYPED_ATOMIC:
309
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
310
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
311
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
312
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
313
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
314
case SHADER_OPCODE_INTERLOCK:
315
case SHADER_OPCODE_MEMORY_FENCE:
316
case SHADER_OPCODE_BARRIER:
319
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
322
case SHADER_OPCODE_SEND:
323
return arg == 2 || arg == 3;
334
* Returns true if this instruction's sources and destinations cannot
335
* safely be the same register.
337
* In most cases, a register can be written over safely by the same
338
* instruction that is its last use. For a single instruction, the
339
* sources are dereferenced before writing of the destination starts
342
* However, there are a few cases where this can be problematic:
344
* - Virtual opcodes that translate to multiple instructions in the
345
* code generator: if src == dst and one instruction writes the
346
* destination before a later instruction reads the source, then
347
* src will have been clobbered.
349
* - SIMD16 compressed instructions with certain regioning (see below).
351
* The register allocator uses this information to set up conflicts between
352
* GRF sources and the destination.
355
fs_inst::has_source_and_destination_hazard() const
358
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
359
/* Multiple partial writes to the destination */
361
case SHADER_OPCODE_SHUFFLE:
362
/* This instruction returns an arbitrary channel from the source and
363
* gets split into smaller instructions in the generator. It's possible
364
* that one of the instructions will read from a channel corresponding
365
* to an earlier instruction.
367
case SHADER_OPCODE_SEL_EXEC:
368
/* This is implemented as
370
* mov(16) g4<1>D 0D { align1 WE_all 1H };
371
* mov(16) g4<1>D g5<8,8,1>D { align1 1H }
373
* Because the source is only read in the second instruction, the first
374
* may stomp all over it.
377
case SHADER_OPCODE_QUAD_SWIZZLE:
379
case BRW_SWIZZLE_XXXX:
380
case BRW_SWIZZLE_YYYY:
381
case BRW_SWIZZLE_ZZZZ:
382
case BRW_SWIZZLE_WWWW:
383
case BRW_SWIZZLE_XXZZ:
384
case BRW_SWIZZLE_YYWW:
385
case BRW_SWIZZLE_XYXY:
386
case BRW_SWIZZLE_ZWZW:
387
/* These can be implemented as a single Align1 region on all
388
* platforms, so there's never a hazard between source and
389
* destination. C.f. fs_generator::generate_quad_swizzle().
393
return !is_uniform(src[0]);
396
/* The SIMD16 compressed instruction
398
* add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
400
* is actually decoded in hardware as:
402
* add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
403
* add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
405
* Which is safe. However, if we have uniform accesses
406
* happening, we get into trouble:
408
* add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
409
* add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
411
* Now our destination for the first instruction overwrote the
412
* second instruction's src0, and we get garbage for those 8
413
* pixels. There's a similar issue for the pre-gfx6
414
* pixel_x/pixel_y, which are registers of 16-bit values and thus
415
* would get stomped by the first decode as well.
417
if (exec_size == 16) {
418
for (int i = 0; i < sources; i++) {
419
if (src[i].file == VGRF && (src[i].stride == 0 ||
420
src[i].type == BRW_REGISTER_TYPE_UW ||
421
src[i].type == BRW_REGISTER_TYPE_W ||
422
src[i].type == BRW_REGISTER_TYPE_UB ||
423
src[i].type == BRW_REGISTER_TYPE_B)) {
433
fs_inst::can_do_source_mods(const struct intel_device_info *devinfo) const
435
if (devinfo->ver == 6 && is_math())
438
if (is_send_from_grf())
441
/* From Wa_1604601757:
443
* "When multiplying a DW and any lower precision integer, source modifier
446
if (devinfo->ver >= 12 && (opcode == BRW_OPCODE_MUL ||
447
opcode == BRW_OPCODE_MAD)) {
448
const brw_reg_type exec_type = get_exec_type(this);
449
const unsigned min_type_sz = opcode == BRW_OPCODE_MAD ?
450
MIN2(type_sz(src[1].type), type_sz(src[2].type)) :
451
MIN2(type_sz(src[0].type), type_sz(src[1].type));
453
if (brw_reg_type_is_integer(exec_type) &&
454
type_sz(exec_type) >= 4 &&
455
type_sz(exec_type) != min_type_sz)
459
if (!backend_instruction::can_do_source_mods())
466
fs_inst::can_do_cmod()
468
if (!backend_instruction::can_do_cmod())
471
/* The accumulator result appears to get used for the conditional modifier
472
* generation. When negating a UD value, there is a 33rd bit generated for
473
* the sign in the accumulator value, so now you can't check, for example,
474
* equality with a 32-bit value. See piglit fs-op-neg-uvec4.
476
for (unsigned i = 0; i < sources; i++) {
477
if (brw_reg_type_is_unsigned_integer(src[i].type) && src[i].negate)
485
fs_inst::can_change_types() const
487
return dst.type == src[0].type &&
488
!src[0].abs && !src[0].negate && !saturate &&
489
(opcode == BRW_OPCODE_MOV ||
490
(opcode == BRW_OPCODE_SEL &&
491
dst.type == src[1].type &&
492
predicate != BRW_PREDICATE_NONE &&
493
!src[1].abs && !src[1].negate));
499
memset((void*)this, 0, sizeof(*this));
500
type = BRW_REGISTER_TYPE_UD;
504
/** Generic unset register constructor. */
508
this->file = BAD_FILE;
511
fs_reg::fs_reg(struct ::brw_reg reg) :
516
if (this->file == IMM &&
517
(this->type != BRW_REGISTER_TYPE_V &&
518
this->type != BRW_REGISTER_TYPE_UV &&
519
this->type != BRW_REGISTER_TYPE_VF)) {
525
fs_reg::equals(const fs_reg &r) const
527
return (this->backend_reg::equals(r) &&
532
fs_reg::negative_equals(const fs_reg &r) const
534
return (this->backend_reg::negative_equals(r) &&
539
fs_reg::is_contiguous() const
544
return hstride == BRW_HORIZONTAL_STRIDE_1 &&
545
vstride == width + hstride;
556
unreachable("Invalid register file");
560
fs_reg::component_size(unsigned width) const
562
const unsigned stride = ((file != ARF && file != FIXED_GRF) ? this->stride :
565
return MAX2(width * stride, 1) * type_sz(type);
569
* Create a MOV to read the timestamp register.
572
fs_visitor::get_timestamp(const fs_builder &bld)
574
assert(devinfo->ver >= 7);
576
fs_reg ts = fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE,
579
BRW_REGISTER_TYPE_UD));
581
fs_reg dst = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
583
/* We want to read the 3 fields we care about even if it's not enabled in
586
bld.group(4, 0).exec_all().MOV(dst, ts);
592
fs_visitor::vfail(const char *format, va_list va)
601
msg = ralloc_vasprintf(mem_ctx, format, va);
602
msg = ralloc_asprintf(mem_ctx, "SIMD%d %s compile failed: %s\n",
603
dispatch_width, stage_abbrev, msg);
605
this->fail_msg = msg;
607
if (unlikely(debug_enabled)) {
608
fprintf(stderr, "%s", msg);
613
fs_visitor::fail(const char *format, ...)
617
va_start(va, format);
623
* Mark this program as impossible to compile with dispatch width greater
626
* During the SIMD8 compile (which happens first), we can detect and flag
627
* things that are unsupported in SIMD16+ mode, so the compiler can skip the
628
* SIMD16+ compile altogether.
630
* During a compile of dispatch width greater than n (if one happens anyway),
631
* this just calls fail().
634
fs_visitor::limit_dispatch_width(unsigned n, const char *msg)
636
if (dispatch_width > n) {
639
max_dispatch_width = MIN2(max_dispatch_width, n);
640
brw_shader_perf_log(compiler, log_data,
641
"Shader dispatch width limited to SIMD%d: %s\n",
647
* Returns true if the instruction has a flag that means it won't
648
* update an entire destination register.
650
* For example, dead code elimination and live variable analysis want to know
651
* when a write to a variable screens off any preceding values that were in
655
fs_inst::is_partial_write() const
657
return ((this->predicate && this->opcode != BRW_OPCODE_SEL) ||
658
(this->exec_size * type_sz(this->dst.type)) < 32 ||
659
!this->dst.is_contiguous() ||
660
this->dst.offset % REG_SIZE != 0);
664
fs_inst::components_read(unsigned i) const
666
/* Return zero if the source is not present. */
667
if (src[i].file == BAD_FILE)
671
case FS_OPCODE_LINTERP:
677
case FS_OPCODE_PIXEL_X:
678
case FS_OPCODE_PIXEL_Y:
685
case FS_OPCODE_FB_WRITE_LOGICAL:
686
assert(src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM);
687
/* First/second FB write color. */
689
return src[FB_WRITE_LOGICAL_SRC_COMPONENTS].ud;
693
case SHADER_OPCODE_TEX_LOGICAL:
694
case SHADER_OPCODE_TXD_LOGICAL:
695
case SHADER_OPCODE_TXF_LOGICAL:
696
case SHADER_OPCODE_TXL_LOGICAL:
697
case SHADER_OPCODE_TXS_LOGICAL:
698
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
699
case FS_OPCODE_TXB_LOGICAL:
700
case SHADER_OPCODE_TXF_CMS_LOGICAL:
701
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
702
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
703
case SHADER_OPCODE_TXF_UMS_LOGICAL:
704
case SHADER_OPCODE_TXF_MCS_LOGICAL:
705
case SHADER_OPCODE_LOD_LOGICAL:
706
case SHADER_OPCODE_TG4_LOGICAL:
707
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
708
case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
709
assert(src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM &&
710
src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM);
711
/* Texture coordinates. */
712
if (i == TEX_LOGICAL_SRC_COORDINATE)
713
return src[TEX_LOGICAL_SRC_COORD_COMPONENTS].ud;
714
/* Texture derivatives. */
715
else if ((i == TEX_LOGICAL_SRC_LOD || i == TEX_LOGICAL_SRC_LOD2) &&
716
opcode == SHADER_OPCODE_TXD_LOGICAL)
717
return src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].ud;
718
/* Texture offset. */
719
else if (i == TEX_LOGICAL_SRC_TG4_OFFSET)
722
else if (i == TEX_LOGICAL_SRC_MCS) {
723
if (opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL)
725
else if (opcode == SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL)
732
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
733
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
734
assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM);
735
/* Surface coordinates. */
736
if (i == SURFACE_LOGICAL_SRC_ADDRESS)
737
return src[SURFACE_LOGICAL_SRC_IMM_DIMS].ud;
738
/* Surface operation source (ignored for reads). */
739
else if (i == SURFACE_LOGICAL_SRC_DATA)
744
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
745
case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
746
assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM &&
747
src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM);
748
/* Surface coordinates. */
749
if (i == SURFACE_LOGICAL_SRC_ADDRESS)
750
return src[SURFACE_LOGICAL_SRC_IMM_DIMS].ud;
751
/* Surface operation source. */
752
else if (i == SURFACE_LOGICAL_SRC_DATA)
753
return src[SURFACE_LOGICAL_SRC_IMM_ARG].ud;
757
case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
758
case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL:
759
case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
760
assert(src[2].file == IMM);
763
case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL:
764
assert(src[2].file == IMM);
765
if (i == 1) { /* data to write */
766
const unsigned comps = src[2].ud / exec_size;
773
case SHADER_OPCODE_OWORD_BLOCK_READ_LOGICAL:
774
case SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
775
assert(src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM);
778
case SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL:
779
assert(src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM);
780
if (i == SURFACE_LOGICAL_SRC_DATA) {
781
const unsigned comps = src[SURFACE_LOGICAL_SRC_IMM_ARG].ud / exec_size;
788
case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
789
assert(src[2].file == IMM);
790
return i == 1 ? src[2].ud : 1;
792
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
793
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL:
794
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
795
assert(src[2].file == IMM);
798
const unsigned op = src[2].ud;
813
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
814
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
815
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
816
assert(src[2].file == IMM);
819
const unsigned op = src[2].ud;
820
return op == BRW_AOP_FCMPWR ? 2 : 1;
825
case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
826
case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
827
/* Scattered logical opcodes use the following params:
828
* src[0] Surface coordinates
829
* src[1] Surface operation source (ignored for reads)
831
* src[3] IMM with always 1 dimension.
832
* src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
834
assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM &&
835
src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM);
836
return i == SURFACE_LOGICAL_SRC_DATA ? 0 : 1;
838
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
839
case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
840
assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM &&
841
src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM);
844
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
845
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: {
846
assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM &&
847
src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM);
848
const unsigned op = src[SURFACE_LOGICAL_SRC_IMM_ARG].ud;
849
/* Surface coordinates. */
850
if (i == SURFACE_LOGICAL_SRC_ADDRESS)
851
return src[SURFACE_LOGICAL_SRC_IMM_DIMS].ud;
852
/* Surface operation source. */
853
else if (i == SURFACE_LOGICAL_SRC_DATA && op == BRW_AOP_CMPWR)
855
else if (i == SURFACE_LOGICAL_SRC_DATA &&
856
(op == BRW_AOP_INC || op == BRW_AOP_DEC || op == BRW_AOP_PREDEC))
861
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
862
return (i == 0 ? 2 : 1);
864
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: {
865
assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM &&
866
src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM);
867
const unsigned op = src[SURFACE_LOGICAL_SRC_IMM_ARG].ud;
868
/* Surface coordinates. */
869
if (i == SURFACE_LOGICAL_SRC_ADDRESS)
870
return src[SURFACE_LOGICAL_SRC_IMM_DIMS].ud;
871
/* Surface operation source. */
872
else if (i == SURFACE_LOGICAL_SRC_DATA && op == BRW_AOP_FCMPWR)
884
fs_inst::size_read(int arg) const
887
case SHADER_OPCODE_SEND:
889
return mlen * REG_SIZE;
890
} else if (arg == 3) {
891
return ex_mlen * REG_SIZE;
895
case FS_OPCODE_FB_WRITE:
896
case FS_OPCODE_REP_FB_WRITE:
899
return src[0].file == BAD_FILE ? 0 : 2 * REG_SIZE;
901
return mlen * REG_SIZE;
905
case FS_OPCODE_FB_READ:
906
case SHADER_OPCODE_URB_WRITE_SIMD8:
907
case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
908
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
909
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
910
case SHADER_OPCODE_URB_READ_SIMD8:
911
case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
912
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
913
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
915
return mlen * REG_SIZE;
918
case FS_OPCODE_SET_SAMPLE_ID:
923
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
924
/* The payload is actually stored in src1 */
926
return mlen * REG_SIZE;
929
case FS_OPCODE_LINTERP:
934
case SHADER_OPCODE_LOAD_PAYLOAD:
935
if (arg < this->header_size)
939
case CS_OPCODE_CS_TERMINATE:
940
case SHADER_OPCODE_BARRIER:
943
case SHADER_OPCODE_MOV_INDIRECT:
945
assert(src[2].file == IMM);
951
if (is_tex() && arg == 0 && src[0].file == VGRF)
952
return mlen * REG_SIZE;
956
switch (src[arg].file) {
959
return components_read(arg) * type_sz(src[arg].type);
965
return components_read(arg) * src[arg].component_size(exec_size);
967
unreachable("MRF registers are not allowed as sources");
974
predicate_width(brw_predicate predicate)
977
case BRW_PREDICATE_NONE: return 1;
978
case BRW_PREDICATE_NORMAL: return 1;
979
case BRW_PREDICATE_ALIGN1_ANY2H: return 2;
980
case BRW_PREDICATE_ALIGN1_ALL2H: return 2;
981
case BRW_PREDICATE_ALIGN1_ANY4H: return 4;
982
case BRW_PREDICATE_ALIGN1_ALL4H: return 4;
983
case BRW_PREDICATE_ALIGN1_ANY8H: return 8;
984
case BRW_PREDICATE_ALIGN1_ALL8H: return 8;
985
case BRW_PREDICATE_ALIGN1_ANY16H: return 16;
986
case BRW_PREDICATE_ALIGN1_ALL16H: return 16;
987
case BRW_PREDICATE_ALIGN1_ANY32H: return 32;
988
case BRW_PREDICATE_ALIGN1_ALL32H: return 32;
989
default: unreachable("Unsupported predicate");
993
/* Return the subset of flag registers that an instruction could
994
* potentially read or write based on the execution controls and flag
995
* subregister number of the instruction.
998
flag_mask(const fs_inst *inst, unsigned width)
1000
assert(util_is_power_of_two_nonzero(width));
1001
const unsigned start = (inst->flag_subreg * 16 + inst->group) &
1003
const unsigned end = start + ALIGN(inst->exec_size, width);
1004
return ((1 << DIV_ROUND_UP(end, 8)) - 1) & ~((1 << (start / 8)) - 1);
1008
bit_mask(unsigned n)
1010
return (n >= CHAR_BIT * sizeof(bit_mask(n)) ? ~0u : (1u << n) - 1);
1014
flag_mask(const fs_reg &r, unsigned sz)
1016
if (r.file == ARF) {
1017
const unsigned start = (r.nr - BRW_ARF_FLAG) * 4 + r.subnr;
1018
const unsigned end = start + sz;
1019
return bit_mask(end) & ~bit_mask(start);
1027
fs_inst::flags_read(const intel_device_info *devinfo) const
1029
if (predicate == BRW_PREDICATE_ALIGN1_ANYV ||
1030
predicate == BRW_PREDICATE_ALIGN1_ALLV) {
1031
/* The vertical predication modes combine corresponding bits from
1032
* f0.0 and f1.0 on Gfx7+, and f0.0 and f0.1 on older hardware.
1034
const unsigned shift = devinfo->ver >= 7 ? 4 : 2;
1035
return flag_mask(this, 1) << shift | flag_mask(this, 1);
1036
} else if (predicate) {
1037
return flag_mask(this, predicate_width(predicate));
1040
for (int i = 0; i < sources; i++) {
1041
mask |= flag_mask(src[i], size_read(i));
1048
fs_inst::flags_written(const intel_device_info *devinfo) const
1050
/* On Gfx4 and Gfx5, sel.l (for min) and sel.ge (for max) are implemented
1051
* using a separte cmpn and sel instruction. This lowering occurs in
1052
* fs_vistor::lower_minmax which is called very, very late.
1054
if ((conditional_mod && ((opcode != BRW_OPCODE_SEL || devinfo->ver <= 5) &&
1055
opcode != BRW_OPCODE_CSEL &&
1056
opcode != BRW_OPCODE_IF &&
1057
opcode != BRW_OPCODE_WHILE)) ||
1058
opcode == FS_OPCODE_FB_WRITE) {
1059
return flag_mask(this, 1);
1060
} else if (opcode == SHADER_OPCODE_FIND_LIVE_CHANNEL ||
1061
opcode == SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL ||
1062
opcode == FS_OPCODE_LOAD_LIVE_CHANNELS) {
1063
return flag_mask(this, 32);
1065
return flag_mask(dst, size_written);
1070
* Returns how many MRFs an FS opcode will write over.
1072
* Note that this is not the 0 or 1 implied writes in an actual gen
1073
* instruction -- the FS opcodes often generate MOVs in addition.
1076
fs_inst::implied_mrf_writes() const
1085
case SHADER_OPCODE_RCP:
1086
case SHADER_OPCODE_RSQ:
1087
case SHADER_OPCODE_SQRT:
1088
case SHADER_OPCODE_EXP2:
1089
case SHADER_OPCODE_LOG2:
1090
case SHADER_OPCODE_SIN:
1091
case SHADER_OPCODE_COS:
1092
return 1 * exec_size / 8;
1093
case SHADER_OPCODE_POW:
1094
case SHADER_OPCODE_INT_QUOTIENT:
1095
case SHADER_OPCODE_INT_REMAINDER:
1096
return 2 * exec_size / 8;
1097
case SHADER_OPCODE_TEX:
1099
case SHADER_OPCODE_TXD:
1100
case SHADER_OPCODE_TXF:
1101
case SHADER_OPCODE_TXF_CMS:
1102
case SHADER_OPCODE_TXF_MCS:
1103
case SHADER_OPCODE_TG4:
1104
case SHADER_OPCODE_TG4_OFFSET:
1105
case SHADER_OPCODE_TXL:
1106
case SHADER_OPCODE_TXS:
1107
case SHADER_OPCODE_LOD:
1108
case SHADER_OPCODE_SAMPLEINFO:
1110
case FS_OPCODE_FB_WRITE:
1111
case FS_OPCODE_REP_FB_WRITE:
1112
return src[0].file == BAD_FILE ? 0 : 2;
1113
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1114
case SHADER_OPCODE_GFX4_SCRATCH_READ:
1116
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
1118
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
1121
unreachable("not reached");
1126
fs_visitor::vgrf(const glsl_type *const type)
1128
int reg_width = dispatch_width / 8;
1130
alloc.allocate(glsl_count_dword_slots(type, false) * reg_width),
1131
brw_type_for_base_type(type));
1134
fs_reg::fs_reg(enum brw_reg_file file, int nr)
1139
this->type = BRW_REGISTER_TYPE_F;
1140
this->stride = (file == UNIFORM ? 0 : 1);
1143
fs_reg::fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type)
1149
this->stride = (file == UNIFORM ? 0 : 1);
1152
/* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1153
* This brings in those uniform definitions
1156
fs_visitor::import_uniforms(fs_visitor *v)
1158
this->push_constant_loc = v->push_constant_loc;
1159
this->uniforms = v->uniforms;
1160
this->subgroup_id = v->subgroup_id;
1161
for (unsigned i = 0; i < ARRAY_SIZE(this->group_size); i++)
1162
this->group_size[i] = v->group_size[i];
1166
fs_visitor::emit_fragcoord_interpolation(fs_reg wpos)
1168
assert(stage == MESA_SHADER_FRAGMENT);
1170
/* gl_FragCoord.x */
1171
bld.MOV(wpos, this->pixel_x);
1172
wpos = offset(wpos, bld, 1);
1174
/* gl_FragCoord.y */
1175
bld.MOV(wpos, this->pixel_y);
1176
wpos = offset(wpos, bld, 1);
1178
/* gl_FragCoord.z */
1179
if (devinfo->ver >= 6) {
1180
bld.MOV(wpos, this->pixel_z);
1182
bld.emit(FS_OPCODE_LINTERP, wpos,
1183
this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL],
1184
component(interp_reg(VARYING_SLOT_POS, 2), 0));
1186
wpos = offset(wpos, bld, 1);
1188
/* gl_FragCoord.w: Already set up in emit_interpolation */
1189
bld.MOV(wpos, this->wpos_w);
1192
enum brw_barycentric_mode
1193
brw_barycentric_mode(enum glsl_interp_mode mode, nir_intrinsic_op op)
1195
/* Barycentric modes don't make sense for flat inputs. */
1196
assert(mode != INTERP_MODE_FLAT);
1200
case nir_intrinsic_load_barycentric_pixel:
1201
case nir_intrinsic_load_barycentric_at_offset:
1202
bary = BRW_BARYCENTRIC_PERSPECTIVE_PIXEL;
1204
case nir_intrinsic_load_barycentric_centroid:
1205
bary = BRW_BARYCENTRIC_PERSPECTIVE_CENTROID;
1207
case nir_intrinsic_load_barycentric_sample:
1208
case nir_intrinsic_load_barycentric_at_sample:
1209
bary = BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE;
1212
unreachable("invalid intrinsic");
1215
if (mode == INTERP_MODE_NOPERSPECTIVE)
1218
return (enum brw_barycentric_mode) bary;
1222
* Turn one of the two CENTROID barycentric modes into PIXEL mode.
1224
static enum brw_barycentric_mode
1225
centroid_to_pixel(enum brw_barycentric_mode bary)
1227
assert(bary == BRW_BARYCENTRIC_PERSPECTIVE_CENTROID ||
1228
bary == BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID);
1229
return (enum brw_barycentric_mode) ((unsigned) bary - 1);
1233
fs_visitor::emit_frontfacing_interpolation()
1235
fs_reg ff = bld.vgrf(BRW_REGISTER_TYPE_D);
1237
if (devinfo->ver >= 12) {
1238
fs_reg g1 = fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W));
1240
fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_W);
1241
bld.ASR(tmp, g1, brw_imm_d(15));
1243
} else if (devinfo->ver >= 6) {
1244
/* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1245
* a boolean result from this (~0/true or 0/false).
1247
* We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1248
* this task in only one instruction:
1249
* - a negation source modifier will flip the bit; and
1250
* - a W -> D type conversion will sign extend the bit into the high
1251
* word of the destination.
1253
* An ASR 15 fills the low word of the destination.
1255
fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
1258
bld.ASR(ff, g0, brw_imm_d(15));
1260
/* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1261
* a boolean result from this (1/true or 0/false).
1263
* Like in the above case, since the bit is the MSB of g1.6:UD we can use
1264
* the negation source modifier to flip it. Unfortunately the SHR
1265
* instruction only operates on UD (or D with an abs source modifier)
1266
* sources without negation.
1268
* Instead, use ASR (which will give ~0/true or 0/false).
1270
fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
1273
bld.ASR(ff, g1_6, brw_imm_d(31));
1280
fs_visitor::emit_samplepos_setup()
1282
assert(stage == MESA_SHADER_FRAGMENT);
1283
struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data);
1284
assert(devinfo->ver >= 6);
1286
const fs_builder abld = bld.annotate("compute sample position");
1287
fs_reg pos = abld.vgrf(BRW_REGISTER_TYPE_F, 2);
1289
if (!wm_prog_data->persample_dispatch) {
1290
/* From ARB_sample_shading specification:
1291
* "When rendering to a non-multisample buffer, or if multisample
1292
* rasterization is disabled, gl_SamplePosition will always be
1295
bld.MOV(offset(pos, bld, 0), brw_imm_f(0.5f));
1296
bld.MOV(offset(pos, bld, 1), brw_imm_f(0.5f));
1300
/* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1301
* mode will be enabled.
1303
* From the Ivy Bridge PRM, volume 2 part 1, page 344:
1304
* R31.1:0 Position Offset X/Y for Slot[3:0]
1305
* R31.3:2 Position Offset X/Y for Slot[7:4]
1308
* The X, Y sample positions come in as bytes in thread payload. So, read
1309
* the positions using vstride=16, width=8, hstride=2.
1311
const fs_reg sample_pos_reg =
1312
fetch_payload_reg(abld, payload.sample_pos_reg, BRW_REGISTER_TYPE_W);
1314
for (unsigned i = 0; i < 2; i++) {
1315
fs_reg tmp_d = bld.vgrf(BRW_REGISTER_TYPE_D);
1316
abld.MOV(tmp_d, subscript(sample_pos_reg, BRW_REGISTER_TYPE_B, i));
1317
/* Convert int_sample_pos to floating point */
1318
fs_reg tmp_f = bld.vgrf(BRW_REGISTER_TYPE_F);
1319
abld.MOV(tmp_f, tmp_d);
1320
/* Scale to the range [0, 1] */
1321
abld.MUL(offset(pos, abld, i), tmp_f, brw_imm_f(1 / 16.0f));
1328
fs_visitor::emit_sampleid_setup()
1330
assert(stage == MESA_SHADER_FRAGMENT);
1331
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
1332
assert(devinfo->ver >= 6);
1334
const fs_builder abld = bld.annotate("compute sample id");
1335
fs_reg sample_id = abld.vgrf(BRW_REGISTER_TYPE_UD);
1337
if (!key->multisample_fbo) {
1338
/* As per GL_ARB_sample_shading specification:
1339
* "When rendering to a non-multisample buffer, or if multisample
1340
* rasterization is disabled, gl_SampleID will always be zero."
1342
abld.MOV(sample_id, brw_imm_d(0));
1343
} else if (devinfo->ver >= 8) {
1344
/* Sample ID comes in as 4-bit numbers in g1.0:
1346
* 15:12 Slot 3 SampleID (only used in SIMD16)
1347
* 11:8 Slot 2 SampleID (only used in SIMD16)
1348
* 7:4 Slot 1 SampleID
1349
* 3:0 Slot 0 SampleID
1351
* Each slot corresponds to four channels, so we want to replicate each
1352
* half-byte value to 4 channels in a row:
1354
* dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1355
* 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1357
* dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1358
* 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1360
* First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1361
* channels to read the first byte (7:0), and the second group of 8
1362
* channels to read the second byte (15:8). Then, we shift right by
1363
* a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1364
* values into place. Finally, we AND with 0xf to keep the low nibble.
1366
* shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1367
* and(16) dst<1>D tmp<8,8,1>W 0xf:W
1369
* TODO: These payload bits exist on Gfx7 too, but they appear to always
1370
* be zero, so this code fails to work. We should find out why.
1372
const fs_reg tmp = abld.vgrf(BRW_REGISTER_TYPE_UW);
1374
for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
1375
const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
1376
hbld.SHR(offset(tmp, hbld, i),
1377
stride(retype(brw_vec1_grf(1 + i, 0), BRW_REGISTER_TYPE_UB),
1379
brw_imm_v(0x44440000));
1382
abld.AND(sample_id, tmp, brw_imm_w(0xf));
1384
const fs_reg t1 = component(abld.vgrf(BRW_REGISTER_TYPE_UD), 0);
1385
const fs_reg t2 = abld.vgrf(BRW_REGISTER_TYPE_UW);
1387
/* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1388
* 8x multisampling, subspan 0 will represent sample N (where N
1389
* is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1390
* 7. We can find the value of N by looking at R0.0 bits 7:6
1391
* ("Starting Sample Pair Index (SSPI)") and multiplying by two
1392
* (since samples are always delivered in pairs). That is, we
1393
* compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1394
* we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1395
* case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1396
* 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1397
* populating a temporary variable with the sequence (0, 1, 2, 3),
1398
* and then reading from it using vstride=1, width=4, hstride=0.
1399
* These computations hold good for 4x multisampling as well.
1401
* For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1402
* the first four slots are sample 0 of subspan 0; the next four
1403
* are sample 1 of subspan 0; the third group is sample 0 of
1404
* subspan 1, and finally sample 1 of subspan 1.
1407
/* SKL+ has an extra bit for the Starting Sample Pair Index to
1408
* accomodate 16x MSAA.
1410
abld.exec_all().group(1, 0)
1411
.AND(t1, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)),
1413
abld.exec_all().group(1, 0).SHR(t1, t1, brw_imm_d(5));
1415
/* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1416
* can assume 4x MSAA. Disallow it on IVB+
1418
* FINISHME: One day, we could come up with a way to do this that
1419
* actually works on gfx7.
1421
if (devinfo->ver >= 7)
1422
limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gfx7");
1423
abld.exec_all().group(8, 0).MOV(t2, brw_imm_v(0x32103210));
1425
/* This special instruction takes care of setting vstride=1,
1426
* width=4, hstride=0 of t2 during an ADD instruction.
1428
abld.emit(FS_OPCODE_SET_SAMPLE_ID, sample_id, t1, t2);
1435
fs_visitor::emit_samplemaskin_setup()
1437
assert(stage == MESA_SHADER_FRAGMENT);
1438
struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data);
1439
assert(devinfo->ver >= 6);
1441
fs_reg mask = bld.vgrf(BRW_REGISTER_TYPE_D);
1443
/* The HW doesn't provide us with expected values. */
1444
assert(!wm_prog_data->per_coarse_pixel_dispatch);
1446
fs_reg coverage_mask =
1447
fetch_payload_reg(bld, payload.sample_mask_in_reg, BRW_REGISTER_TYPE_D);
1449
if (wm_prog_data->persample_dispatch) {
1450
/* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1451
* and a mask representing which sample is being processed by the
1452
* current shader invocation.
1454
* From the OES_sample_variables specification:
1455
* "When per-sample shading is active due to the use of a fragment input
1456
* qualified by "sample" or due to the use of the gl_SampleID or
1457
* gl_SamplePosition variables, only the bit for the current sample is
1458
* set in gl_SampleMaskIn."
1460
const fs_builder abld = bld.annotate("compute gl_SampleMaskIn");
1462
if (nir_system_values[SYSTEM_VALUE_SAMPLE_ID].file == BAD_FILE)
1463
nir_system_values[SYSTEM_VALUE_SAMPLE_ID] = emit_sampleid_setup();
1465
fs_reg one = vgrf(glsl_type::int_type);
1466
fs_reg enabled_mask = vgrf(glsl_type::int_type);
1467
abld.MOV(one, brw_imm_d(1));
1468
abld.SHL(enabled_mask, one, nir_system_values[SYSTEM_VALUE_SAMPLE_ID]);
1469
abld.AND(mask, enabled_mask, coverage_mask);
1471
/* In per-pixel mode, the coverage mask is sufficient. */
1472
mask = coverage_mask;
1478
fs_visitor::emit_shading_rate_setup()
1480
assert(devinfo->ver >= 11);
1482
const fs_builder abld = bld.annotate("compute fragment shading rate");
1483
fs_reg rate = abld.vgrf(BRW_REGISTER_TYPE_UD);
1485
struct brw_wm_prog_data *wm_prog_data =
1486
brw_wm_prog_data(bld.shader->stage_prog_data);
1488
/* Coarse pixel shading size fields overlap with other fields of not in
1489
* coarse pixel dispatch mode, so report 0 when that's not the case.
1491
if (wm_prog_data->per_coarse_pixel_dispatch) {
1492
/* The shading rates provided in the shader are the actual 2D shading
1493
* rate while the SPIR-V built-in is the enum value that has the shading
1494
* rate encoded as a bitfield. Fortunately, the bitfield value is just
1495
* the shading rate divided by two and shifted.
1498
/* r1.0 - 0:7 ActualCoarsePixelShadingSize.X */
1499
fs_reg actual_x = fs_reg(retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UB));
1500
/* r1.0 - 15:8 ActualCoarsePixelShadingSize.Y */
1501
fs_reg actual_y = byte_offset(actual_x, 1);
1503
fs_reg int_rate_x = bld.vgrf(BRW_REGISTER_TYPE_UD);
1504
fs_reg int_rate_y = bld.vgrf(BRW_REGISTER_TYPE_UD);
1506
abld.SHR(int_rate_y, actual_y, brw_imm_ud(1));
1507
abld.SHR(int_rate_x, actual_x, brw_imm_ud(1));
1508
abld.SHL(int_rate_x, int_rate_x, brw_imm_ud(2));
1509
abld.OR(rate, int_rate_x, int_rate_y);
1511
abld.MOV(rate, brw_imm_ud(0));
1518
fs_visitor::resolve_source_modifiers(const fs_reg &src)
1520
if (!src.abs && !src.negate)
1523
fs_reg temp = bld.vgrf(src.type);
1530
fs_visitor::emit_gs_thread_end()
1532
assert(stage == MESA_SHADER_GEOMETRY);
1534
struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
1536
if (gs_compile->control_data_header_size_bits > 0) {
1537
emit_gs_control_data_bits(this->final_gs_vertex_count);
1540
const fs_builder abld = bld.annotate("thread end");
1543
if (gs_prog_data->static_vertex_count != -1) {
1544
foreach_in_list_reverse(fs_inst, prev, &this->instructions) {
1545
if (prev->opcode == SHADER_OPCODE_URB_WRITE_SIMD8 ||
1546
prev->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
1547
prev->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
1548
prev->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) {
1551
/* Delete now dead instructions. */
1552
foreach_in_list_reverse_safe(exec_node, dead, &this->instructions) {
1558
} else if (prev->is_control_flow() || prev->has_side_effects()) {
1562
fs_reg hdr = abld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1563
abld.MOV(hdr, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD)));
1564
inst = abld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, hdr);
1567
fs_reg payload = abld.vgrf(BRW_REGISTER_TYPE_UD, 2);
1568
fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
1569
sources[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
1570
sources[1] = this->final_gs_vertex_count;
1571
abld.LOAD_PAYLOAD(payload, sources, 2, 2);
1572
inst = abld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload);
1580
fs_visitor::assign_curb_setup()
1582
unsigned uniform_push_length = DIV_ROUND_UP(stage_prog_data->nr_params, 8);
1584
unsigned ubo_push_length = 0;
1585
unsigned ubo_push_start[4];
1586
for (int i = 0; i < 4; i++) {
1587
ubo_push_start[i] = 8 * (ubo_push_length + uniform_push_length);
1588
ubo_push_length += stage_prog_data->ubo_ranges[i].length;
1591
prog_data->curb_read_length = uniform_push_length + ubo_push_length;
1594
bool is_compute = gl_shader_stage_is_compute(stage);
1596
if (is_compute && brw_cs_prog_data(prog_data)->uses_inline_data) {
1597
/* With COMPUTE_WALKER, we can push up to one register worth of data via
1598
* the inline data parameter in the COMPUTE_WALKER command itself.
1600
* TODO: Support inline data and push at the same time.
1602
assert(devinfo->verx10 >= 125);
1603
assert(uniform_push_length <= 1);
1604
} else if (is_compute && devinfo->verx10 >= 125) {
1605
fs_builder ubld = bld.exec_all().group(8, 0).at(
1606
cfg->first_block(), cfg->first_block()->start());
1608
/* The base address for our push data is passed in as R0.0[31:6]. We
1609
* have to mask off the bottom 6 bits.
1611
fs_reg base_addr = ubld.vgrf(BRW_REGISTER_TYPE_UD);
1612
ubld.group(1, 0).AND(base_addr,
1613
retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD),
1614
brw_imm_ud(INTEL_MASK(31, 6)));
1616
fs_reg header0 = ubld.vgrf(BRW_REGISTER_TYPE_UD);
1617
ubld.MOV(header0, brw_imm_ud(0));
1618
ubld.group(1, 0).SHR(component(header0, 2), base_addr, brw_imm_ud(4));
1620
/* On Gfx12-HP we load constants at the start of the program using A32
1621
* stateless messages.
1623
for (unsigned i = 0; i < uniform_push_length;) {
1624
/* Limit ourselves to HW limit of 8 Owords (8 * 16bytes = 128 bytes
1627
unsigned num_regs = MIN2(uniform_push_length - i, 4);
1628
assert(num_regs > 0);
1629
num_regs = 1 << util_logbase2(num_regs);
1635
header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
1636
ubld.MOV(header, brw_imm_ud(0));
1637
ubld.group(1, 0).ADD(component(header, 2),
1638
component(header0, 2),
1643
brw_imm_ud(0), /* desc */
1644
brw_imm_ud(0), /* ex_desc */
1645
header, /* payload */
1646
fs_reg(), /* payload2 */
1649
fs_reg dest = retype(brw_vec8_grf(payload.num_regs + i, 0),
1650
BRW_REGISTER_TYPE_UD);
1652
/* This instruction has to be run SIMD16 if we're filling more than a
1655
unsigned send_width = MIN2(16, num_regs * 8);
1657
fs_inst *send = ubld.group(send_width, 0).emit(SHADER_OPCODE_SEND,
1659
send->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
1660
send->desc = brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT,
1661
GFX7_DATAPORT_DC_OWORD_BLOCK_READ,
1662
BRW_DATAPORT_OWORD_BLOCK_OWORDS(num_regs * 2));
1663
send->header_size = 1;
1665
send->size_written = num_regs * REG_SIZE;
1666
send->send_is_volatile = true;
1671
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
1674
/* Map the offsets in the UNIFORM file to fixed HW regs. */
1675
foreach_block_and_inst(block, fs_inst, inst, cfg) {
1676
for (unsigned int i = 0; i < inst->sources; i++) {
1677
if (inst->src[i].file == UNIFORM) {
1678
int uniform_nr = inst->src[i].nr + inst->src[i].offset / 4;
1680
if (inst->src[i].nr >= UBO_START) {
1681
/* constant_nr is in 32-bit units, the rest are in bytes */
1682
constant_nr = ubo_push_start[inst->src[i].nr - UBO_START] +
1683
inst->src[i].offset / 4;
1684
} else if (uniform_nr >= 0 && uniform_nr < (int) uniforms) {
1685
constant_nr = push_constant_loc[uniform_nr];
1687
/* Section 5.11 of the OpenGL 4.1 spec says:
1688
* "Out-of-bounds reads return undefined values, which include
1689
* values from other variables of the active program or zero."
1690
* Just return the first push constant.
1695
assert(constant_nr / 8 < 64);
1696
used |= BITFIELD64_BIT(constant_nr / 8);
1698
struct brw_reg brw_reg = brw_vec1_grf(payload.num_regs +
1701
brw_reg.abs = inst->src[i].abs;
1702
brw_reg.negate = inst->src[i].negate;
1704
assert(inst->src[i].stride == 0);
1705
inst->src[i] = byte_offset(
1706
retype(brw_reg, inst->src[i].type),
1707
inst->src[i].offset % 4);
1712
uint64_t want_zero = used & stage_prog_data->zero_push_reg;
1714
fs_builder ubld = bld.exec_all().group(8, 0).at(
1715
cfg->first_block(), cfg->first_block()->start());
1717
/* push_reg_mask_param is in 32-bit units */
1718
unsigned mask_param = stage_prog_data->push_reg_mask_param;
1719
struct brw_reg mask = brw_vec1_grf(payload.num_regs + mask_param / 8,
1723
for (unsigned i = 0; i < 64; i++) {
1724
if (i % 16 == 0 && (want_zero & BITFIELD64_RANGE(i, 16))) {
1725
fs_reg shifted = ubld.vgrf(BRW_REGISTER_TYPE_W, 2);
1726
ubld.SHL(horiz_offset(shifted, 8),
1727
byte_offset(retype(mask, BRW_REGISTER_TYPE_W), i / 8),
1728
brw_imm_v(0x01234567));
1729
ubld.SHL(shifted, horiz_offset(shifted, 8), brw_imm_w(8));
1731
fs_builder ubld16 = ubld.group(16, 0);
1732
b32 = ubld16.vgrf(BRW_REGISTER_TYPE_D);
1733
ubld16.group(16, 0).ASR(b32, shifted, brw_imm_w(15));
1736
if (want_zero & BITFIELD64_BIT(i)) {
1737
assert(i < prog_data->curb_read_length);
1738
struct brw_reg push_reg =
1739
retype(brw_vec8_grf(payload.num_regs + i, 0),
1740
BRW_REGISTER_TYPE_D);
1742
ubld.AND(push_reg, push_reg, component(b32, i % 16));
1746
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
1749
/* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1750
this->first_non_payload_grf = payload.num_regs + prog_data->curb_read_length;
1754
* Build up an array of indices into the urb_setup array that
1755
* references the active entries of the urb_setup array.
1756
* Used to accelerate walking the active entries of the urb_setup array
1760
brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data)
1762
/* TODO(mesh): Review usage of this in the context of Mesh, we may want to
1763
* skip per-primitive attributes here.
1766
/* Make sure uint8_t is sufficient */
1767
STATIC_ASSERT(VARYING_SLOT_MAX <= 0xff);
1769
for (uint8_t attr = 0; attr < VARYING_SLOT_MAX; attr++) {
1770
if (wm_prog_data->urb_setup[attr] >= 0) {
1771
wm_prog_data->urb_setup_attribs[index++] = attr;
1774
wm_prog_data->urb_setup_attribs_count = index;
1778
calculate_urb_setup(const struct intel_device_info *devinfo,
1779
const struct brw_wm_prog_key *key,
1780
struct brw_wm_prog_data *prog_data,
1781
const nir_shader *nir,
1782
const struct brw_mue_map *mue_map)
1784
memset(prog_data->urb_setup, -1,
1785
sizeof(prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
1789
const uint64_t inputs_read =
1790
nir->info.inputs_read & ~nir->info.per_primitive_inputs;
1792
/* Figure out where each of the incoming setup attributes lands. */
1794
/* Per-Primitive Attributes are laid out by Hardware before the regular
1795
* attributes, so order them like this to make easy later to map setup
1796
* into real HW registers.
1798
if (nir->info.per_primitive_inputs) {
1799
for (unsigned i = 0; i < VARYING_SLOT_MAX; i++) {
1800
if (nir->info.per_primitive_inputs & BITFIELD64_BIT(i)) {
1801
prog_data->urb_setup[i] = urb_next++;
1805
/* The actual setup attributes later must be aligned to a full GRF. */
1806
urb_next = ALIGN(urb_next, 2);
1808
prog_data->num_per_primitive_inputs = urb_next;
1811
const uint64_t clip_dist_bits = VARYING_BIT_CLIP_DIST0 |
1812
VARYING_BIT_CLIP_DIST1;
1814
uint64_t unique_fs_attrs = inputs_read & BRW_FS_VARYING_INPUT_MASK;
1816
if (inputs_read & clip_dist_bits) {
1817
assert(mue_map->per_vertex_header_size_dw > 8);
1818
unique_fs_attrs &= ~clip_dist_bits;
1821
/* In Mesh, CLIP_DIST slots are always at the beginning, because
1822
* they come from MUE Vertex Header, not Per-Vertex Attributes.
1824
if (inputs_read & clip_dist_bits) {
1825
prog_data->urb_setup[VARYING_SLOT_CLIP_DIST0] = urb_next++;
1826
prog_data->urb_setup[VARYING_SLOT_CLIP_DIST1] = urb_next++;
1829
/* Per-Vertex attributes are laid out ordered. Because we always link
1830
* Mesh and Fragment shaders, the which slots are written and read by
1831
* each of them will match. */
1832
for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
1833
if (unique_fs_attrs & BITFIELD64_BIT(i))
1834
prog_data->urb_setup[i] = urb_next++;
1836
} else if (devinfo->ver >= 6) {
1837
uint64_t vue_header_bits =
1838
VARYING_BIT_PSIZ | VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT;
1840
uint64_t unique_fs_attrs = inputs_read & BRW_FS_VARYING_INPUT_MASK;
1842
/* VUE header fields all live in the same URB slot, so we pass them
1843
* as a single FS input attribute. We want to only count them once.
1845
if (inputs_read & vue_header_bits) {
1846
unique_fs_attrs &= ~vue_header_bits;
1847
unique_fs_attrs |= VARYING_BIT_PSIZ;
1850
if (util_bitcount64(unique_fs_attrs) <= 16) {
1851
/* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1852
* first 16 varying inputs, so we can put them wherever we want.
1853
* Just put them in order.
1855
* This is useful because it means that (a) inputs not used by the
1856
* fragment shader won't take up valuable register space, and (b) we
1857
* won't have to recompile the fragment shader if it gets paired with
1858
* a different vertex (or geometry) shader.
1860
* VUE header fields share the same FS input attribute.
1862
if (inputs_read & vue_header_bits) {
1863
if (inputs_read & VARYING_BIT_PSIZ)
1864
prog_data->urb_setup[VARYING_SLOT_PSIZ] = urb_next;
1865
if (inputs_read & VARYING_BIT_LAYER)
1866
prog_data->urb_setup[VARYING_SLOT_LAYER] = urb_next;
1867
if (inputs_read & VARYING_BIT_VIEWPORT)
1868
prog_data->urb_setup[VARYING_SLOT_VIEWPORT] = urb_next;
1873
for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
1874
if (inputs_read & BRW_FS_VARYING_INPUT_MASK & ~vue_header_bits &
1875
BITFIELD64_BIT(i)) {
1876
prog_data->urb_setup[i] = urb_next++;
1880
/* We have enough input varyings that the SF/SBE pipeline stage can't
1881
* arbitrarily rearrange them to suit our whim; we have to put them
1882
* in an order that matches the output of the previous pipeline stage
1883
* (geometry or vertex shader).
1886
/* Re-compute the VUE map here in the case that the one coming from
1887
* geometry has more than one position slot (used for Primitive
1890
struct brw_vue_map prev_stage_vue_map;
1891
brw_compute_vue_map(devinfo, &prev_stage_vue_map,
1892
key->input_slots_valid,
1893
nir->info.separate_shader, 1);
1896
brw_compute_first_urb_slot_required(inputs_read,
1897
&prev_stage_vue_map);
1899
assert(prev_stage_vue_map.num_slots <= first_slot + 32);
1900
for (int slot = first_slot; slot < prev_stage_vue_map.num_slots;
1902
int varying = prev_stage_vue_map.slot_to_varying[slot];
1903
if (varying != BRW_VARYING_SLOT_PAD &&
1904
(inputs_read & BRW_FS_VARYING_INPUT_MASK &
1905
BITFIELD64_BIT(varying))) {
1906
prog_data->urb_setup[varying] = slot - first_slot;
1909
urb_next = prev_stage_vue_map.num_slots - first_slot;
1912
/* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1913
for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
1914
/* Point size is packed into the header, not as a general attribute */
1915
if (i == VARYING_SLOT_PSIZ)
1918
if (key->input_slots_valid & BITFIELD64_BIT(i)) {
1919
/* The back color slot is skipped when the front color is
1920
* also written to. In addition, some slots can be
1921
* written in the vertex shader and not read in the
1922
* fragment shader. So the register number must always be
1923
* incremented, mapped or not.
1925
if (_mesa_varying_slot_in_fs((gl_varying_slot) i))
1926
prog_data->urb_setup[i] = urb_next;
1932
* It's a FS only attribute, and we did interpolation for this attribute
1933
* in SF thread. So, count it here, too.
1935
* See compile_sf_prog() for more info.
1937
if (inputs_read & BITFIELD64_BIT(VARYING_SLOT_PNTC))
1938
prog_data->urb_setup[VARYING_SLOT_PNTC] = urb_next++;
1941
prog_data->num_varying_inputs = urb_next - prog_data->num_per_primitive_inputs;
1942
prog_data->inputs = inputs_read;
1944
brw_compute_urb_setup_index(prog_data);
1948
fs_visitor::assign_urb_setup()
1950
assert(stage == MESA_SHADER_FRAGMENT);
1951
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
1953
int urb_start = payload.num_regs + prog_data->base.curb_read_length;
1955
/* Offset all the urb_setup[] index by the actual position of the
1956
* setup regs, now that the location of the constants has been chosen.
1958
foreach_block_and_inst(block, fs_inst, inst, cfg) {
1959
for (int i = 0; i < inst->sources; i++) {
1960
if (inst->src[i].file == ATTR) {
1961
/* ATTR regs in the FS are in units of logical scalar inputs each
1962
* of which consumes half of a GRF register.
1964
assert(inst->src[i].offset < REG_SIZE / 2);
1965
const unsigned grf = urb_start + inst->src[i].nr / 2;
1966
const unsigned offset = (inst->src[i].nr % 2) * (REG_SIZE / 2) +
1967
inst->src[i].offset;
1968
const unsigned width = inst->src[i].stride == 0 ?
1969
1 : MIN2(inst->exec_size, 8);
1970
struct brw_reg reg = stride(
1971
byte_offset(retype(brw_vec8_grf(grf, 0), inst->src[i].type),
1973
width * inst->src[i].stride,
1974
width, inst->src[i].stride);
1975
reg.abs = inst->src[i].abs;
1976
reg.negate = inst->src[i].negate;
1982
/* Each attribute is 4 setup channels, each of which is half a reg. */
1983
this->first_non_payload_grf += prog_data->num_varying_inputs * 2;
1985
/* Unlike regular attributes, per-primitive attributes have all 4 channels
1986
* in the same slot, so each GRF can store two slots.
1988
assert(prog_data->num_per_primitive_inputs % 2 == 0);
1989
this->first_non_payload_grf += prog_data->num_per_primitive_inputs / 2;
1993
fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst)
1995
for (int i = 0; i < inst->sources; i++) {
1996
if (inst->src[i].file == ATTR) {
1997
int grf = payload.num_regs +
1998
prog_data->curb_read_length +
2000
inst->src[i].offset / REG_SIZE;
2002
/* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
2004
* VertStride must be used to cross GRF register boundaries. This
2005
* rule implies that elements within a 'Width' cannot cross GRF
2008
* So, for registers that are large enough, we have to split the exec
2009
* size in two and trust the compression state to sort it out.
2011
unsigned total_size = inst->exec_size *
2012
inst->src[i].stride *
2013
type_sz(inst->src[i].type);
2015
assert(total_size <= 2 * REG_SIZE);
2016
const unsigned exec_size =
2017
(total_size <= REG_SIZE) ? inst->exec_size : inst->exec_size / 2;
2019
unsigned width = inst->src[i].stride == 0 ? 1 : exec_size;
2020
struct brw_reg reg =
2021
stride(byte_offset(retype(brw_vec8_grf(grf, 0), inst->src[i].type),
2022
inst->src[i].offset % REG_SIZE),
2023
exec_size * inst->src[i].stride,
2024
width, inst->src[i].stride);
2025
reg.abs = inst->src[i].abs;
2026
reg.negate = inst->src[i].negate;
2034
fs_visitor::assign_vs_urb_setup()
2036
struct brw_vs_prog_data *vs_prog_data = brw_vs_prog_data(prog_data);
2038
assert(stage == MESA_SHADER_VERTEX);
2040
/* Each attribute is 4 regs. */
2041
this->first_non_payload_grf += 4 * vs_prog_data->nr_attribute_slots;
2043
assert(vs_prog_data->base.urb_read_length <= 15);
2045
/* Rewrite all ATTR file references to the hw grf that they land in. */
2046
foreach_block_and_inst(block, fs_inst, inst, cfg) {
2047
convert_attr_sources_to_hw_regs(inst);
2052
fs_visitor::assign_tcs_urb_setup()
2054
assert(stage == MESA_SHADER_TESS_CTRL);
2056
/* Rewrite all ATTR file references to HW_REGs. */
2057
foreach_block_and_inst(block, fs_inst, inst, cfg) {
2058
convert_attr_sources_to_hw_regs(inst);
2063
fs_visitor::assign_tes_urb_setup()
2065
assert(stage == MESA_SHADER_TESS_EVAL);
2067
struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data);
2069
first_non_payload_grf += 8 * vue_prog_data->urb_read_length;
2071
/* Rewrite all ATTR file references to HW_REGs. */
2072
foreach_block_and_inst(block, fs_inst, inst, cfg) {
2073
convert_attr_sources_to_hw_regs(inst);
2078
fs_visitor::assign_gs_urb_setup()
2080
assert(stage == MESA_SHADER_GEOMETRY);
2082
struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data);
2084
first_non_payload_grf +=
2085
8 * vue_prog_data->urb_read_length * nir->info.gs.vertices_in;
2087
foreach_block_and_inst(block, fs_inst, inst, cfg) {
2088
/* Rewrite all ATTR file references to GRFs. */
2089
convert_attr_sources_to_hw_regs(inst);
2095
* Split large virtual GRFs into separate components if we can.
2097
* This pass aggressively splits VGRFs into as small a chunks as possible,
2098
* down to single registers if it can. If no VGRFs can be split, we return
2099
* false so this pass can safely be used inside an optimization loop. We
2100
* want to split, because virtual GRFs are what we register allocate and
2101
* spill (due to contiguousness requirements for some instructions), and
2102
* they're what we naturally generate in the codegen process, but most
2103
* virtual GRFs don't actually need to be contiguous sets of GRFs. If we
2104
* split, we'll end up with reduced live intervals and better dead code
2105
* elimination and coalescing.
2108
fs_visitor::split_virtual_grfs()
2110
/* Compact the register file so we eliminate dead vgrfs. This
2111
* only defines split points for live registers, so if we have
2112
* too large dead registers they will hit assertions later.
2114
compact_virtual_grfs();
2116
int num_vars = this->alloc.count;
2118
/* Count the total number of registers */
2120
int vgrf_to_reg[num_vars];
2121
for (int i = 0; i < num_vars; i++) {
2122
vgrf_to_reg[i] = reg_count;
2123
reg_count += alloc.sizes[i];
2126
/* An array of "split points". For each register slot, this indicates
2127
* if this slot can be separated from the previous slot. Every time an
2128
* instruction uses multiple elements of a register (as a source or
2129
* destination), we mark the used slots as inseparable. Then we go
2130
* through and split the registers into the smallest pieces we can.
2132
bool *split_points = new bool[reg_count];
2133
memset(split_points, 0, reg_count * sizeof(*split_points));
2135
/* Mark all used registers as fully splittable */
2136
foreach_block_and_inst(block, fs_inst, inst, cfg) {
2137
if (inst->dst.file == VGRF) {
2138
int reg = vgrf_to_reg[inst->dst.nr];
2139
for (unsigned j = 1; j < this->alloc.sizes[inst->dst.nr]; j++)
2140
split_points[reg + j] = true;
2143
for (int i = 0; i < inst->sources; i++) {
2144
if (inst->src[i].file == VGRF) {
2145
int reg = vgrf_to_reg[inst->src[i].nr];
2146
for (unsigned j = 1; j < this->alloc.sizes[inst->src[i].nr]; j++)
2147
split_points[reg + j] = true;
2152
foreach_block_and_inst(block, fs_inst, inst, cfg) {
2153
/* We fix up undef instructions later */
2154
if (inst->opcode == SHADER_OPCODE_UNDEF) {
2155
/* UNDEF instructions are currently only used to undef entire
2156
* registers. We need this invariant later when we split them.
2158
assert(inst->dst.file == VGRF);
2159
assert(inst->dst.offset == 0);
2160
assert(inst->size_written == alloc.sizes[inst->dst.nr] * REG_SIZE);
2164
if (inst->dst.file == VGRF) {
2165
int reg = vgrf_to_reg[inst->dst.nr] + inst->dst.offset / REG_SIZE;
2166
for (unsigned j = 1; j < regs_written(inst); j++)
2167
split_points[reg + j] = false;
2169
for (int i = 0; i < inst->sources; i++) {
2170
if (inst->src[i].file == VGRF) {
2171
int reg = vgrf_to_reg[inst->src[i].nr] + inst->src[i].offset / REG_SIZE;
2172
for (unsigned j = 1; j < regs_read(inst, i); j++)
2173
split_points[reg + j] = false;
2178
/* Bitset of which registers have been split */
2179
bool *vgrf_has_split = new bool[num_vars];
2180
memset(vgrf_has_split, 0, num_vars * sizeof(*vgrf_has_split));
2182
int *new_virtual_grf = new int[reg_count];
2183
int *new_reg_offset = new int[reg_count];
2186
bool has_splits = false;
2187
for (int i = 0; i < num_vars; i++) {
2188
/* The first one should always be 0 as a quick sanity check. */
2189
assert(split_points[reg] == false);
2192
new_reg_offset[reg] = 0;
2197
for (unsigned j = 1; j < alloc.sizes[i]; j++) {
2198
/* If this is a split point, reset the offset to 0 and allocate a
2199
* new virtual GRF for the previous offset many registers
2201
if (split_points[reg]) {
2203
vgrf_has_split[i] = true;
2204
assert(offset <= MAX_VGRF_SIZE);
2205
int grf = alloc.allocate(offset);
2206
for (int k = reg - offset; k < reg; k++)
2207
new_virtual_grf[k] = grf;
2210
new_reg_offset[reg] = offset;
2215
/* The last one gets the original register number */
2216
assert(offset <= MAX_VGRF_SIZE);
2217
alloc.sizes[i] = offset;
2218
for (int k = reg - offset; k < reg; k++)
2219
new_virtual_grf[k] = i;
2221
assert(reg == reg_count);
2229
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
2230
if (inst->opcode == SHADER_OPCODE_UNDEF) {
2231
assert(inst->dst.file == VGRF);
2232
if (vgrf_has_split[inst->dst.nr]) {
2233
const fs_builder ibld(this, block, inst);
2234
assert(inst->size_written % REG_SIZE == 0);
2235
unsigned reg_offset = 0;
2236
while (reg_offset < inst->size_written / REG_SIZE) {
2237
reg = vgrf_to_reg[inst->dst.nr] + reg_offset;
2238
ibld.UNDEF(fs_reg(VGRF, new_virtual_grf[reg], inst->dst.type));
2239
reg_offset += alloc.sizes[new_virtual_grf[reg]];
2241
inst->remove(block);
2243
reg = vgrf_to_reg[inst->dst.nr];
2244
assert(new_reg_offset[reg] == 0);
2245
assert(new_virtual_grf[reg] == (int)inst->dst.nr);
2250
if (inst->dst.file == VGRF) {
2251
reg = vgrf_to_reg[inst->dst.nr] + inst->dst.offset / REG_SIZE;
2252
if (vgrf_has_split[inst->dst.nr]) {
2253
inst->dst.nr = new_virtual_grf[reg];
2254
inst->dst.offset = new_reg_offset[reg] * REG_SIZE +
2255
inst->dst.offset % REG_SIZE;
2256
assert((unsigned)new_reg_offset[reg] <
2257
alloc.sizes[new_virtual_grf[reg]]);
2259
assert(new_reg_offset[reg] == inst->dst.offset / REG_SIZE);
2260
assert(new_virtual_grf[reg] == (int)inst->dst.nr);
2263
for (int i = 0; i < inst->sources; i++) {
2264
if (inst->src[i].file != VGRF)
2267
reg = vgrf_to_reg[inst->src[i].nr] + inst->src[i].offset / REG_SIZE;
2268
if (vgrf_has_split[inst->src[i].nr]) {
2269
inst->src[i].nr = new_virtual_grf[reg];
2270
inst->src[i].offset = new_reg_offset[reg] * REG_SIZE +
2271
inst->src[i].offset % REG_SIZE;
2272
assert((unsigned)new_reg_offset[reg] <
2273
alloc.sizes[new_virtual_grf[reg]]);
2275
assert(new_reg_offset[reg] == inst->src[i].offset / REG_SIZE);
2276
assert(new_virtual_grf[reg] == (int)inst->src[i].nr);
2280
invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL | DEPENDENCY_VARIABLES);
2285
delete[] split_points;
2286
delete[] vgrf_has_split;
2287
delete[] new_virtual_grf;
2288
delete[] new_reg_offset;
2294
* Remove unused virtual GRFs and compact the vgrf_* arrays.
2296
* During code generation, we create tons of temporary variables, many of
2297
* which get immediately killed and are never used again. Yet, in later
2298
* optimization and analysis passes, such as compute_live_intervals, we need
2299
* to loop over all the virtual GRFs. Compacting them can save a lot of
2303
fs_visitor::compact_virtual_grfs()
2305
bool progress = false;
2306
int *remap_table = new int[this->alloc.count];
2307
memset(remap_table, -1, this->alloc.count * sizeof(int));
2309
/* Mark which virtual GRFs are used. */
2310
foreach_block_and_inst(block, const fs_inst, inst, cfg) {
2311
if (inst->dst.file == VGRF)
2312
remap_table[inst->dst.nr] = 0;
2314
for (int i = 0; i < inst->sources; i++) {
2315
if (inst->src[i].file == VGRF)
2316
remap_table[inst->src[i].nr] = 0;
2320
/* Compact the GRF arrays. */
2322
for (unsigned i = 0; i < this->alloc.count; i++) {
2323
if (remap_table[i] == -1) {
2324
/* We just found an unused register. This means that we are
2325
* actually going to compact something.
2329
remap_table[i] = new_index;
2330
alloc.sizes[new_index] = alloc.sizes[i];
2331
invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL | DEPENDENCY_VARIABLES);
2336
this->alloc.count = new_index;
2338
/* Patch all the instructions to use the newly renumbered registers */
2339
foreach_block_and_inst(block, fs_inst, inst, cfg) {
2340
if (inst->dst.file == VGRF)
2341
inst->dst.nr = remap_table[inst->dst.nr];
2343
for (int i = 0; i < inst->sources; i++) {
2344
if (inst->src[i].file == VGRF)
2345
inst->src[i].nr = remap_table[inst->src[i].nr];
2349
/* Patch all the references to delta_xy, since they're used in register
2350
* allocation. If they're unused, switch them to BAD_FILE so we don't
2351
* think some random VGRF is delta_xy.
2353
for (unsigned i = 0; i < ARRAY_SIZE(delta_xy); i++) {
2354
if (delta_xy[i].file == VGRF) {
2355
if (remap_table[delta_xy[i].nr] != -1) {
2356
delta_xy[i].nr = remap_table[delta_xy[i].nr];
2358
delta_xy[i].file = BAD_FILE;
2363
delete[] remap_table;
2369
get_subgroup_id_param_index(const intel_device_info *devinfo,
2370
const brw_stage_prog_data *prog_data)
2372
if (prog_data->nr_params == 0)
2375
if (devinfo->verx10 >= 125)
2378
/* The local thread id is always the last parameter in the list */
2379
uint32_t last_param = prog_data->param[prog_data->nr_params - 1];
2380
if (last_param == BRW_PARAM_BUILTIN_SUBGROUP_ID)
2381
return prog_data->nr_params - 1;
2387
* Assign UNIFORM file registers to either push constants or pull constants.
2389
* We allow a fragment shader to have more than the specified minimum
2390
* maximum number of fragment shader uniform components (64). If
2391
* there are too many of these, they'd fill up all of register space.
2392
* So, this will push some of them out to the pull constant buffer and
2393
* update the program to load them.
2396
fs_visitor::assign_constant_locations()
2398
/* Only the first compile gets to decide on locations. */
2399
if (push_constant_loc)
2402
push_constant_loc = ralloc_array(mem_ctx, int, uniforms);
2403
for (unsigned u = 0; u < uniforms; u++)
2404
push_constant_loc[u] = u;
2406
/* Now that we know how many regular uniforms we'll push, reduce the
2407
* UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2410
* Only allow 16 registers (128 uniform components) as push constants.
2412
* If changing this value, note the limitation about total_regs in
2413
* brw_curbe.c/crocus_state.c
2415
const unsigned max_push_length = compiler->devinfo->ver < 6 ? 16 : 64;
2416
unsigned push_length = DIV_ROUND_UP(stage_prog_data->nr_params, 8);
2417
for (int i = 0; i < 4; i++) {
2418
struct brw_ubo_range *range = &prog_data->ubo_ranges[i];
2420
if (push_length + range->length > max_push_length)
2421
range->length = max_push_length - push_length;
2423
push_length += range->length;
2425
assert(push_length <= max_push_length);
2429
fs_visitor::get_pull_locs(const fs_reg &src,
2430
unsigned *out_surf_index,
2431
unsigned *out_pull_index)
2433
assert(src.file == UNIFORM);
2435
if (src.nr < UBO_START)
2438
const struct brw_ubo_range *range =
2439
&prog_data->ubo_ranges[src.nr - UBO_START];
2441
/* If this access is in our (reduced) range, use the push data. */
2442
if (src.offset / 32 < range->length)
2445
*out_surf_index = range->block;
2446
*out_pull_index = (32 * range->start + src.offset) / 4;
2448
prog_data->has_ubo_pull = true;
2454
* Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2455
* or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2458
fs_visitor::lower_constant_loads()
2460
unsigned index, pull_index;
2462
foreach_block_and_inst_safe (block, fs_inst, inst, cfg) {
2463
/* Set up the annotation tracking for new generated instructions. */
2464
const fs_builder ibld(this, block, inst);
2466
for (int i = 0; i < inst->sources; i++) {
2467
if (inst->src[i].file != UNIFORM)
2470
/* We'll handle this case later */
2471
if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT && i == 0)
2474
if (!get_pull_locs(inst->src[i], &index, &pull_index))
2477
assert(inst->src[i].stride == 0);
2479
const unsigned block_sz = 64; /* Fetch one cacheline at a time. */
2480
const fs_builder ubld = ibld.exec_all().group(block_sz / 4, 0);
2481
const fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_UD);
2482
const unsigned base = pull_index * 4;
2484
ubld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
2485
dst, brw_imm_ud(index), brw_imm_ud(base & ~(block_sz - 1)));
2487
/* Rewrite the instruction to use the temporary VGRF. */
2488
inst->src[i].file = VGRF;
2489
inst->src[i].nr = dst.nr;
2490
inst->src[i].offset = (base & (block_sz - 1)) +
2491
inst->src[i].offset % 4;
2494
if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT &&
2495
inst->src[0].file == UNIFORM) {
2497
if (!get_pull_locs(inst->src[0], &index, &pull_index))
2500
VARYING_PULL_CONSTANT_LOAD(ibld, inst->dst,
2504
inst->remove(block);
2507
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
2511
fs_visitor::opt_algebraic()
2513
bool progress = false;
2515
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
2516
switch (inst->opcode) {
2517
case BRW_OPCODE_MOV:
2518
if (!devinfo->has_64bit_float &&
2519
!devinfo->has_64bit_int &&
2520
(inst->dst.type == BRW_REGISTER_TYPE_DF ||
2521
inst->dst.type == BRW_REGISTER_TYPE_UQ ||
2522
inst->dst.type == BRW_REGISTER_TYPE_Q)) {
2523
assert(inst->dst.type == inst->src[0].type);
2524
assert(!inst->saturate);
2525
assert(!inst->src[0].abs);
2526
assert(!inst->src[0].negate);
2527
const brw::fs_builder ibld(this, block, inst);
2529
ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 1),
2530
subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 1));
2531
ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 0),
2532
subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0));
2534
inst->remove(block);
2538
if ((inst->conditional_mod == BRW_CONDITIONAL_Z ||
2539
inst->conditional_mod == BRW_CONDITIONAL_NZ) &&
2540
inst->dst.is_null() &&
2541
(inst->src[0].abs || inst->src[0].negate)) {
2542
inst->src[0].abs = false;
2543
inst->src[0].negate = false;
2548
if (inst->src[0].file != IMM)
2551
if (inst->saturate) {
2552
/* Full mixed-type saturates don't happen. However, we can end up
2555
* mov.sat(8) g21<1>DF -1F
2557
* Other mixed-size-but-same-base-type cases may also be possible.
2559
if (inst->dst.type != inst->src[0].type &&
2560
inst->dst.type != BRW_REGISTER_TYPE_DF &&
2561
inst->src[0].type != BRW_REGISTER_TYPE_F)
2562
assert(!"unimplemented: saturate mixed types");
2564
if (brw_saturate_immediate(inst->src[0].type,
2565
&inst->src[0].as_brw_reg())) {
2566
inst->saturate = false;
2572
case BRW_OPCODE_MUL:
2573
if (inst->src[1].file != IMM)
2576
if (brw_reg_type_is_floating_point(inst->src[1].type))
2580
if (inst->src[1].is_one()) {
2581
inst->opcode = BRW_OPCODE_MOV;
2582
inst->src[1] = reg_undef;
2588
if (inst->src[1].is_negative_one()) {
2589
inst->opcode = BRW_OPCODE_MOV;
2590
inst->src[0].negate = !inst->src[0].negate;
2591
inst->src[1] = reg_undef;
2597
case BRW_OPCODE_ADD:
2598
if (inst->src[1].file != IMM)
2601
if (brw_reg_type_is_integer(inst->src[1].type) &&
2602
inst->src[1].is_zero()) {
2603
inst->opcode = BRW_OPCODE_MOV;
2604
inst->src[1] = reg_undef;
2609
if (inst->src[0].file == IMM) {
2610
assert(inst->src[0].type == BRW_REGISTER_TYPE_F);
2611
inst->opcode = BRW_OPCODE_MOV;
2612
inst->src[0].f += inst->src[1].f;
2613
inst->src[1] = reg_undef;
2619
if (inst->src[0].equals(inst->src[1]) ||
2620
inst->src[1].is_zero()) {
2621
/* On Gfx8+, the OR instruction can have a source modifier that
2622
* performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
2623
* or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
2625
if (inst->src[0].negate) {
2626
inst->opcode = BRW_OPCODE_NOT;
2627
inst->src[0].negate = false;
2629
inst->opcode = BRW_OPCODE_MOV;
2631
inst->src[1] = reg_undef;
2636
case BRW_OPCODE_CMP:
2637
if ((inst->conditional_mod == BRW_CONDITIONAL_Z ||
2638
inst->conditional_mod == BRW_CONDITIONAL_NZ) &&
2639
inst->src[1].is_zero() &&
2640
(inst->src[0].abs || inst->src[0].negate)) {
2641
inst->src[0].abs = false;
2642
inst->src[0].negate = false;
2647
case BRW_OPCODE_SEL:
2648
if (!devinfo->has_64bit_float &&
2649
!devinfo->has_64bit_int &&
2650
(inst->dst.type == BRW_REGISTER_TYPE_DF ||
2651
inst->dst.type == BRW_REGISTER_TYPE_UQ ||
2652
inst->dst.type == BRW_REGISTER_TYPE_Q)) {
2653
assert(inst->dst.type == inst->src[0].type);
2654
assert(!inst->saturate);
2655
assert(!inst->src[0].abs && !inst->src[0].negate);
2656
assert(!inst->src[1].abs && !inst->src[1].negate);
2657
const brw::fs_builder ibld(this, block, inst);
2659
set_predicate(inst->predicate,
2660
ibld.SEL(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 0),
2661
subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
2662
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0)));
2663
set_predicate(inst->predicate,
2664
ibld.SEL(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 1),
2665
subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 1),
2666
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 1)));
2668
inst->remove(block);
2671
if (inst->src[0].equals(inst->src[1])) {
2672
inst->opcode = BRW_OPCODE_MOV;
2673
inst->src[1] = reg_undef;
2674
inst->predicate = BRW_PREDICATE_NONE;
2675
inst->predicate_inverse = false;
2677
} else if (inst->saturate && inst->src[1].file == IMM) {
2678
switch (inst->conditional_mod) {
2679
case BRW_CONDITIONAL_LE:
2680
case BRW_CONDITIONAL_L:
2681
switch (inst->src[1].type) {
2682
case BRW_REGISTER_TYPE_F:
2683
if (inst->src[1].f >= 1.0f) {
2684
inst->opcode = BRW_OPCODE_MOV;
2685
inst->src[1] = reg_undef;
2686
inst->conditional_mod = BRW_CONDITIONAL_NONE;
2694
case BRW_CONDITIONAL_GE:
2695
case BRW_CONDITIONAL_G:
2696
switch (inst->src[1].type) {
2697
case BRW_REGISTER_TYPE_F:
2698
if (inst->src[1].f <= 0.0f) {
2699
inst->opcode = BRW_OPCODE_MOV;
2700
inst->src[1] = reg_undef;
2701
inst->conditional_mod = BRW_CONDITIONAL_NONE;
2713
case BRW_OPCODE_MAD:
2714
if (inst->src[0].type != BRW_REGISTER_TYPE_F ||
2715
inst->src[1].type != BRW_REGISTER_TYPE_F ||
2716
inst->src[2].type != BRW_REGISTER_TYPE_F)
2718
if (inst->src[1].is_one()) {
2719
inst->opcode = BRW_OPCODE_ADD;
2720
inst->src[1] = inst->src[2];
2721
inst->src[2] = reg_undef;
2723
} else if (inst->src[2].is_one()) {
2724
inst->opcode = BRW_OPCODE_ADD;
2725
inst->src[2] = reg_undef;
2729
case SHADER_OPCODE_BROADCAST:
2730
if (is_uniform(inst->src[0])) {
2731
inst->opcode = BRW_OPCODE_MOV;
2733
inst->force_writemask_all = true;
2735
} else if (inst->src[1].file == IMM) {
2736
inst->opcode = BRW_OPCODE_MOV;
2737
/* It's possible that the selected component will be too large and
2738
* overflow the register. This can happen if someone does a
2739
* readInvocation() from GLSL or SPIR-V and provides an OOB
2740
* invocationIndex. If this happens and we some how manage
2741
* to constant fold it in and get here, then component() may cause
2742
* us to start reading outside of the VGRF which will lead to an
2743
* assert later. Instead, just let it wrap around if it goes over
2746
const unsigned comp = inst->src[1].ud & (inst->exec_size - 1);
2747
inst->src[0] = component(inst->src[0], comp);
2749
inst->force_writemask_all = true;
2754
case SHADER_OPCODE_SHUFFLE:
2755
if (is_uniform(inst->src[0])) {
2756
inst->opcode = BRW_OPCODE_MOV;
2759
} else if (inst->src[1].file == IMM) {
2760
inst->opcode = BRW_OPCODE_MOV;
2761
inst->src[0] = component(inst->src[0],
2772
/* Swap if src[0] is immediate. */
2773
if (progress && inst->is_commutative()) {
2774
if (inst->src[0].file == IMM) {
2775
fs_reg tmp = inst->src[1];
2776
inst->src[1] = inst->src[0];
2783
invalidate_analysis(DEPENDENCY_INSTRUCTION_DATA_FLOW |
2784
DEPENDENCY_INSTRUCTION_DETAIL);
2790
* Optimize sample messages that have constant zero values for the trailing
2791
* texture coordinates. We can just reduce the message length for these
2792
* instructions instead of reserving a register for it. Trailing parameters
2793
* that aren't sent default to zero anyway. This will cause the dead code
2794
* eliminator to remove the MOV instruction that would otherwise be emitted to
2795
* set up the zero value.
2798
fs_visitor::opt_zero_samples()
2800
/* Gfx4 infers the texturing opcode based on the message length so we can't
2801
* change it. Gfx12.5 has restrictions on the number of coordinate
2802
* parameters that have to be provided for some texture types
2805
if (devinfo->ver < 5 || devinfo->verx10 == 125)
2808
bool progress = false;
2810
foreach_block_and_inst(block, fs_inst, inst, cfg) {
2811
if (!inst->is_tex())
2814
fs_inst *load_payload = (fs_inst *) inst->prev;
2816
if (load_payload->is_head_sentinel() ||
2817
load_payload->opcode != SHADER_OPCODE_LOAD_PAYLOAD)
2820
/* We don't want to remove the message header or the first parameter.
2821
* Removing the first parameter is not allowed, see the Haswell PRM
2822
* volume 7, page 149:
2824
* "Parameter 0 is required except for the sampleinfo message, which
2825
* has no parameter 0"
2827
while (inst->mlen > inst->header_size + inst->exec_size / 8 &&
2828
load_payload->src[(inst->mlen - inst->header_size) /
2829
(inst->exec_size / 8) +
2830
inst->header_size - 1].is_zero()) {
2831
inst->mlen -= inst->exec_size / 8;
2837
invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL);
2843
fs_visitor::opt_register_renaming()
2845
bool progress = false;
2848
unsigned remap[alloc.count];
2849
memset(remap, ~0u, sizeof(unsigned) * alloc.count);
2851
foreach_block_and_inst(block, fs_inst, inst, cfg) {
2852
if (inst->opcode == BRW_OPCODE_IF || inst->opcode == BRW_OPCODE_DO) {
2854
} else if (inst->opcode == BRW_OPCODE_ENDIF ||
2855
inst->opcode == BRW_OPCODE_WHILE) {
2859
/* Rewrite instruction sources. */
2860
for (int i = 0; i < inst->sources; i++) {
2861
if (inst->src[i].file == VGRF &&
2862
remap[inst->src[i].nr] != ~0u &&
2863
remap[inst->src[i].nr] != inst->src[i].nr) {
2864
inst->src[i].nr = remap[inst->src[i].nr];
2869
const unsigned dst = inst->dst.nr;
2872
inst->dst.file == VGRF &&
2873
alloc.sizes[inst->dst.nr] * REG_SIZE == inst->size_written &&
2874
!inst->is_partial_write()) {
2875
if (remap[dst] == ~0u) {
2878
remap[dst] = alloc.allocate(regs_written(inst));
2879
inst->dst.nr = remap[dst];
2882
} else if (inst->dst.file == VGRF &&
2883
remap[dst] != ~0u &&
2884
remap[dst] != dst) {
2885
inst->dst.nr = remap[dst];
2891
invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL |
2892
DEPENDENCY_VARIABLES);
2894
for (unsigned i = 0; i < ARRAY_SIZE(delta_xy); i++) {
2895
if (delta_xy[i].file == VGRF && remap[delta_xy[i].nr] != ~0u) {
2896
delta_xy[i].nr = remap[delta_xy[i].nr];
2905
* Remove redundant or useless halts.
2907
* For example, we can eliminate halts in the following sequence:
2909
* halt (redundant with the next halt)
2910
* halt (useless; jumps to the next instruction)
2914
fs_visitor::opt_redundant_halt()
2916
bool progress = false;
2918
unsigned halt_count = 0;
2919
fs_inst *halt_target = NULL;
2920
bblock_t *halt_target_block = NULL;
2921
foreach_block_and_inst(block, fs_inst, inst, cfg) {
2922
if (inst->opcode == BRW_OPCODE_HALT)
2925
if (inst->opcode == SHADER_OPCODE_HALT_TARGET) {
2927
halt_target_block = block;
2933
assert(halt_count == 0);
2937
/* Delete any HALTs immediately before the halt target. */
2938
for (fs_inst *prev = (fs_inst *) halt_target->prev;
2939
!prev->is_head_sentinel() && prev->opcode == BRW_OPCODE_HALT;
2940
prev = (fs_inst *) halt_target->prev) {
2941
prev->remove(halt_target_block);
2946
if (halt_count == 0) {
2947
halt_target->remove(halt_target_block);
2952
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
2958
* Compute a bitmask with GRF granularity with a bit set for each GRF starting
2959
* from \p r.offset which overlaps the region starting at \p s.offset and
2960
* spanning \p ds bytes.
2962
static inline unsigned
2963
mask_relative_to(const fs_reg &r, const fs_reg &s, unsigned ds)
2965
const int rel_offset = reg_offset(s) - reg_offset(r);
2966
const int shift = rel_offset / REG_SIZE;
2967
const unsigned n = DIV_ROUND_UP(rel_offset % REG_SIZE + ds, REG_SIZE);
2968
assert(reg_space(r) == reg_space(s) &&
2969
shift >= 0 && shift < int(8 * sizeof(unsigned)));
2970
return ((1 << n) - 1) << shift;
2974
fs_visitor::compute_to_mrf()
2976
bool progress = false;
2979
/* No MRFs on Gen >= 7. */
2980
if (devinfo->ver >= 7)
2983
const fs_live_variables &live = live_analysis.require();
2985
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
2989
if (inst->opcode != BRW_OPCODE_MOV ||
2990
inst->is_partial_write() ||
2991
inst->dst.file != MRF || inst->src[0].file != VGRF ||
2992
inst->dst.type != inst->src[0].type ||
2993
inst->src[0].abs || inst->src[0].negate ||
2994
!inst->src[0].is_contiguous() ||
2995
inst->src[0].offset % REG_SIZE != 0)
2998
/* Can't compute-to-MRF this GRF if someone else was going to
3001
if (live.vgrf_end[inst->src[0].nr] > ip)
3004
/* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3005
* things that computed the value of all GRFs of the source region. The
3006
* regs_left bitset keeps track of the registers we haven't yet found a
3007
* generating instruction for.
3009
unsigned regs_left = (1 << regs_read(inst, 0)) - 1;
3011
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
3012
if (regions_overlap(scan_inst->dst, scan_inst->size_written,
3013
inst->src[0], inst->size_read(0))) {
3014
/* Found the last thing to write our reg we want to turn
3015
* into a compute-to-MRF.
3018
/* If this one instruction didn't populate all the
3019
* channels, bail. We might be able to rewrite everything
3020
* that writes that reg, but it would require smarter
3023
if (scan_inst->is_partial_write())
3026
/* Handling things not fully contained in the source of the copy
3027
* would need us to understand coalescing out more than one MOV at
3030
if (!region_contained_in(scan_inst->dst, scan_inst->size_written,
3031
inst->src[0], inst->size_read(0)))
3034
/* SEND instructions can't have MRF as a destination. */
3035
if (scan_inst->mlen)
3038
if (devinfo->ver == 6) {
3039
/* gfx6 math instructions must have the destination be
3040
* GRF, so no compute-to-MRF for them.
3042
if (scan_inst->is_math()) {
3047
/* Clear the bits for any registers this instruction overwrites. */
3048
regs_left &= ~mask_relative_to(
3049
inst->src[0], scan_inst->dst, scan_inst->size_written);
3054
/* We don't handle control flow here. Most computation of
3055
* values that end up in MRFs are shortly before the MRF
3058
if (block->start() == scan_inst)
3061
/* You can't read from an MRF, so if someone else reads our
3062
* MRF's source GRF that we wanted to rewrite, that stops us.
3064
bool interfered = false;
3065
for (int i = 0; i < scan_inst->sources; i++) {
3066
if (regions_overlap(scan_inst->src[i], scan_inst->size_read(i),
3067
inst->src[0], inst->size_read(0))) {
3074
if (regions_overlap(scan_inst->dst, scan_inst->size_written,
3075
inst->dst, inst->size_written)) {
3076
/* If somebody else writes our MRF here, we can't
3077
* compute-to-MRF before that.
3082
if (scan_inst->mlen > 0 && scan_inst->base_mrf != -1 &&
3083
regions_overlap(fs_reg(MRF, scan_inst->base_mrf), scan_inst->mlen * REG_SIZE,
3084
inst->dst, inst->size_written)) {
3085
/* Found a SEND instruction, which means that there are
3086
* live values in MRFs from base_mrf to base_mrf +
3087
* scan_inst->mlen - 1. Don't go pushing our MRF write up
3097
/* Found all generating instructions of our MRF's source value, so it
3098
* should be safe to rewrite them to point to the MRF directly.
3100
regs_left = (1 << regs_read(inst, 0)) - 1;
3102
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
3103
if (regions_overlap(scan_inst->dst, scan_inst->size_written,
3104
inst->src[0], inst->size_read(0))) {
3105
/* Clear the bits for any registers this instruction overwrites. */
3106
regs_left &= ~mask_relative_to(
3107
inst->src[0], scan_inst->dst, scan_inst->size_written);
3109
const unsigned rel_offset = reg_offset(scan_inst->dst) -
3110
reg_offset(inst->src[0]);
3112
if (inst->dst.nr & BRW_MRF_COMPR4) {
3113
/* Apply the same address transformation done by the hardware
3114
* for COMPR4 MRF writes.
3116
assert(rel_offset < 2 * REG_SIZE);
3117
scan_inst->dst.nr = inst->dst.nr + rel_offset / REG_SIZE * 4;
3119
/* Clear the COMPR4 bit if the generating instruction is not
3122
if (scan_inst->size_written < 2 * REG_SIZE)
3123
scan_inst->dst.nr &= ~BRW_MRF_COMPR4;
3126
/* Calculate the MRF number the result of this instruction is
3127
* ultimately written to.
3129
scan_inst->dst.nr = inst->dst.nr + rel_offset / REG_SIZE;
3132
scan_inst->dst.file = MRF;
3133
scan_inst->dst.offset = inst->dst.offset + rel_offset % REG_SIZE;
3134
scan_inst->saturate |= inst->saturate;
3141
inst->remove(block);
3146
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
3152
* Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3153
* flow. We could probably do better here with some form of divergence
3157
fs_visitor::eliminate_find_live_channel()
3159
bool progress = false;
3162
if (!brw_stage_has_packed_dispatch(devinfo, stage, stage_prog_data)) {
3163
/* The optimization below assumes that channel zero is live on thread
3164
* dispatch, which may not be the case if the fixed function dispatches
3170
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
3171
switch (inst->opcode) {
3177
case BRW_OPCODE_ENDIF:
3178
case BRW_OPCODE_WHILE:
3182
case BRW_OPCODE_HALT:
3183
/* This can potentially make control flow non-uniform until the end
3188
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
3190
inst->opcode = BRW_OPCODE_MOV;
3191
inst->src[0] = brw_imm_ud(0u);
3193
inst->force_writemask_all = true;
3204
invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL);
3210
* Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3211
* instructions to FS_OPCODE_REP_FB_WRITE.
3214
fs_visitor::emit_repclear_shader()
3216
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
3218
int color_mrf = base_mrf + 2;
3222
mov = bld.exec_all().group(4, 0)
3223
.MOV(brw_message_reg(color_mrf),
3224
fs_reg(UNIFORM, 0, BRW_REGISTER_TYPE_F));
3226
struct brw_reg reg =
3227
brw_reg(BRW_GENERAL_REGISTER_FILE, 2, 3, 0, 0, BRW_REGISTER_TYPE_UD,
3228
BRW_VERTICAL_STRIDE_8, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_4,
3229
BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
3231
mov = bld.exec_all().group(4, 0)
3232
.MOV(brw_uvec_mrf(4, color_mrf, 0), fs_reg(reg));
3235
fs_inst *write = NULL;
3236
if (key->nr_color_regions == 1) {
3237
write = bld.emit(FS_OPCODE_REP_FB_WRITE);
3238
write->saturate = key->clamp_fragment_color;
3239
write->base_mrf = color_mrf;
3241
write->header_size = 0;
3244
assume(key->nr_color_regions > 0);
3246
struct brw_reg header =
3247
retype(brw_message_reg(base_mrf), BRW_REGISTER_TYPE_UD);
3248
bld.exec_all().group(16, 0)
3249
.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
3251
for (int i = 0; i < key->nr_color_regions; ++i) {
3253
bld.exec_all().group(1, 0)
3254
.MOV(component(header, 2), brw_imm_ud(i));
3257
write = bld.emit(FS_OPCODE_REP_FB_WRITE);
3258
write->saturate = key->clamp_fragment_color;
3259
write->base_mrf = base_mrf;
3261
write->header_size = 2;
3266
write->last_rt = true;
3270
assign_constant_locations();
3271
assign_curb_setup();
3273
/* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3275
assert(mov->src[0].file == FIXED_GRF);
3276
mov->src[0] = brw_vec4_grf(mov->src[0].nr, 0);
3283
* Walks through basic blocks, looking for repeated MRF writes and
3284
* removing the later ones.
3287
fs_visitor::remove_duplicate_mrf_writes()
3289
fs_inst *last_mrf_move[BRW_MAX_MRF(devinfo->ver)];
3290
bool progress = false;
3292
/* Need to update the MRF tracking for compressed instructions. */
3293
if (dispatch_width >= 16)
3296
memset(last_mrf_move, 0, sizeof(last_mrf_move));
3298
foreach_block_and_inst_safe (block, fs_inst, inst, cfg) {
3299
if (inst->is_control_flow()) {
3300
memset(last_mrf_move, 0, sizeof(last_mrf_move));
3303
if (inst->opcode == BRW_OPCODE_MOV &&
3304
inst->dst.file == MRF) {
3305
fs_inst *prev_inst = last_mrf_move[inst->dst.nr];
3306
if (prev_inst && prev_inst->opcode == BRW_OPCODE_MOV &&
3307
inst->dst.equals(prev_inst->dst) &&
3308
inst->src[0].equals(prev_inst->src[0]) &&
3309
inst->saturate == prev_inst->saturate &&
3310
inst->predicate == prev_inst->predicate &&
3311
inst->conditional_mod == prev_inst->conditional_mod &&
3312
inst->exec_size == prev_inst->exec_size) {
3313
inst->remove(block);
3319
/* Clear out the last-write records for MRFs that were overwritten. */
3320
if (inst->dst.file == MRF) {
3321
last_mrf_move[inst->dst.nr] = NULL;
3324
if (inst->mlen > 0 && inst->base_mrf != -1) {
3325
/* Found a SEND instruction, which will include two or fewer
3326
* implied MRF writes. We could do better here.
3328
for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
3329
last_mrf_move[inst->base_mrf + i] = NULL;
3333
/* Clear out any MRF move records whose sources got overwritten. */
3334
for (unsigned i = 0; i < ARRAY_SIZE(last_mrf_move); i++) {
3335
if (last_mrf_move[i] &&
3336
regions_overlap(inst->dst, inst->size_written,
3337
last_mrf_move[i]->src[0],
3338
last_mrf_move[i]->size_read(0))) {
3339
last_mrf_move[i] = NULL;
3343
if (inst->opcode == BRW_OPCODE_MOV &&
3344
inst->dst.file == MRF &&
3345
inst->src[0].file != ARF &&
3346
!inst->is_partial_write()) {
3347
last_mrf_move[inst->dst.nr] = inst;
3352
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
3358
* Rounding modes for conversion instructions are included for each
3359
* conversion, but right now it is a state. So once it is set,
3360
* we don't need to call it again for subsequent calls.
3362
* This is useful for vector/matrices conversions, as setting the
3363
* mode once is enough for the full vector/matrix
3366
fs_visitor::remove_extra_rounding_modes()
3368
bool progress = false;
3369
unsigned execution_mode = this->nir->info.float_controls_execution_mode;
3371
brw_rnd_mode base_mode = BRW_RND_MODE_UNSPECIFIED;
3372
if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 |
3373
FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 |
3374
FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64) &
3376
base_mode = BRW_RND_MODE_RTNE;
3377
if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 |
3378
FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 |
3379
FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64) &
3381
base_mode = BRW_RND_MODE_RTZ;
3383
foreach_block (block, cfg) {
3384
brw_rnd_mode prev_mode = base_mode;
3386
foreach_inst_in_block_safe (fs_inst, inst, block) {
3387
if (inst->opcode == SHADER_OPCODE_RND_MODE) {
3388
assert(inst->src[0].file == BRW_IMMEDIATE_VALUE);
3389
const brw_rnd_mode mode = (brw_rnd_mode) inst->src[0].d;
3390
if (mode == prev_mode) {
3391
inst->remove(block);
3401
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
3407
clear_deps_for_inst_src(fs_inst *inst, bool *deps, int first_grf, int grf_len)
3409
/* Clear the flag for registers that actually got read (as expected). */
3410
for (int i = 0; i < inst->sources; i++) {
3412
if (inst->src[i].file == VGRF || inst->src[i].file == FIXED_GRF) {
3413
grf = inst->src[i].nr;
3418
if (grf >= first_grf &&
3419
grf < first_grf + grf_len) {
3420
deps[grf - first_grf] = false;
3421
if (inst->exec_size == 16)
3422
deps[grf - first_grf + 1] = false;
3428
* Implements this workaround for the original 965:
3430
* "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3431
* check for post destination dependencies on this instruction, software
3432
* must ensure that there is no destination hazard for the case of ‘write
3433
* followed by a posted write’ shown in the following example.
3436
* 2. send r3.xy <rest of send instruction>
3439
* Due to no post-destination dependency check on the ‘send’, the above
3440
* code sequence could have two instructions (1 and 2) in flight at the
3441
* same time that both consider ‘r3’ as the target of their final writes.
3444
fs_visitor::insert_gfx4_pre_send_dependency_workarounds(bblock_t *block,
3447
int write_len = regs_written(inst);
3448
int first_write_grf = inst->dst.nr;
3449
bool needs_dep[BRW_MAX_MRF(devinfo->ver)];
3450
assert(write_len < (int)sizeof(needs_dep) - 1);
3452
memset(needs_dep, false, sizeof(needs_dep));
3453
memset(needs_dep, true, write_len);
3455
clear_deps_for_inst_src(inst, needs_dep, first_write_grf, write_len);
3457
/* Walk backwards looking for writes to registers we're writing which
3458
* aren't read since being written. If we hit the start of the program,
3459
* we assume that there are no outstanding dependencies on entry to the
3462
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
3463
/* If we hit control flow, assume that there *are* outstanding
3464
* dependencies, and force their cleanup before our instruction.
3466
if (block->start() == scan_inst && block->num != 0) {
3467
for (int i = 0; i < write_len; i++) {
3469
DEP_RESOLVE_MOV(fs_builder(this, block, inst),
3470
first_write_grf + i);
3475
/* We insert our reads as late as possible on the assumption that any
3476
* instruction but a MOV that might have left us an outstanding
3477
* dependency has more latency than a MOV.
3479
if (scan_inst->dst.file == VGRF) {
3480
for (unsigned i = 0; i < regs_written(scan_inst); i++) {
3481
int reg = scan_inst->dst.nr + i;
3483
if (reg >= first_write_grf &&
3484
reg < first_write_grf + write_len &&
3485
needs_dep[reg - first_write_grf]) {
3486
DEP_RESOLVE_MOV(fs_builder(this, block, inst), reg);
3487
needs_dep[reg - first_write_grf] = false;
3488
if (scan_inst->exec_size == 16)
3489
needs_dep[reg - first_write_grf + 1] = false;
3494
/* Clear the flag for registers that actually got read (as expected). */
3495
clear_deps_for_inst_src(scan_inst, needs_dep, first_write_grf, write_len);
3497
/* Continue the loop only if we haven't resolved all the dependencies */
3499
for (i = 0; i < write_len; i++) {
3509
* Implements this workaround for the original 965:
3511
* "[DevBW, DevCL] Errata: A destination register from a send can not be
3512
* used as a destination register until after it has been sourced by an
3513
* instruction with a different destination register.
3516
fs_visitor::insert_gfx4_post_send_dependency_workarounds(bblock_t *block, fs_inst *inst)
3518
int write_len = regs_written(inst);
3519
unsigned first_write_grf = inst->dst.nr;
3520
bool needs_dep[BRW_MAX_MRF(devinfo->ver)];
3521
assert(write_len < (int)sizeof(needs_dep) - 1);
3523
memset(needs_dep, false, sizeof(needs_dep));
3524
memset(needs_dep, true, write_len);
3525
/* Walk forwards looking for writes to registers we're writing which aren't
3526
* read before being written.
3528
foreach_inst_in_block_starting_from(fs_inst, scan_inst, inst) {
3529
/* If we hit control flow, force resolve all remaining dependencies. */
3530
if (block->end() == scan_inst && block->num != cfg->num_blocks - 1) {
3531
for (int i = 0; i < write_len; i++) {
3533
DEP_RESOLVE_MOV(fs_builder(this, block, scan_inst),
3534
first_write_grf + i);
3539
/* Clear the flag for registers that actually got read (as expected). */
3540
clear_deps_for_inst_src(scan_inst, needs_dep, first_write_grf, write_len);
3542
/* We insert our reads as late as possible since they're reading the
3543
* result of a SEND, which has massive latency.
3545
if (scan_inst->dst.file == VGRF &&
3546
scan_inst->dst.nr >= first_write_grf &&
3547
scan_inst->dst.nr < first_write_grf + write_len &&
3548
needs_dep[scan_inst->dst.nr - first_write_grf]) {
3549
DEP_RESOLVE_MOV(fs_builder(this, block, scan_inst),
3551
needs_dep[scan_inst->dst.nr - first_write_grf] = false;
3554
/* Continue the loop only if we haven't resolved all the dependencies */
3556
for (i = 0; i < write_len; i++) {
3566
fs_visitor::insert_gfx4_send_dependency_workarounds()
3568
if (devinfo->ver != 4 || devinfo->platform == INTEL_PLATFORM_G4X)
3571
bool progress = false;
3573
foreach_block_and_inst(block, fs_inst, inst, cfg) {
3574
if (inst->mlen != 0 && inst->dst.file == VGRF) {
3575
insert_gfx4_pre_send_dependency_workarounds(block, inst);
3576
insert_gfx4_post_send_dependency_workarounds(block, inst);
3582
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
3586
* Turns the generic expression-style uniform pull constant load instruction
3587
* into a hardware-specific series of instructions for loading a pull
3590
* The expression style allows the CSE pass before this to optimize out
3591
* repeated loads from the same offset, and gives the pre-register-allocation
3592
* scheduling full flexibility, while the conversion to native instructions
3593
* allows the post-register-allocation scheduler the best information
3596
* Note that execution masking for setting up pull constant loads is special:
3597
* the channels that need to be written are unrelated to the current execution
3598
* mask, since a later instruction will use one of the result channels as a
3599
* source operand for all 8 or 16 of its channels.
3602
fs_visitor::lower_uniform_pull_constant_loads()
3604
foreach_block_and_inst (block, fs_inst, inst, cfg) {
3605
if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD)
3608
const fs_reg& surface = inst->src[0];
3609
const fs_reg& offset_B = inst->src[1];
3610
assert(offset_B.file == IMM);
3612
if (devinfo->has_lsc) {
3613
const fs_builder ubld =
3614
fs_builder(this, block, inst).group(8, 0).exec_all();
3616
const fs_reg payload = ubld.vgrf(BRW_REGISTER_TYPE_UD);
3617
ubld.MOV(payload, offset_B);
3619
inst->sfid = GFX12_SFID_UGM;
3620
inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD,
3622
LSC_ADDR_SURFTYPE_BTI,
3624
1 /* num_coordinates */,
3626
inst->size_written / 4,
3627
true /* transpose */,
3628
LSC_CACHE_LOAD_L1STATE_L3MOCS,
3629
true /* has_dest */);
3632
if (surface.file == IMM) {
3633
ex_desc = brw_imm_ud(lsc_bti_ex_desc(devinfo, surface.ud));
3635
/* We only need the first component for the payload so we can use
3636
* one of the other components for the extended descriptor
3638
ex_desc = component(payload, 1);
3639
ubld.group(1, 0).SHL(ex_desc, surface, brw_imm_ud(24));
3642
/* Update the original instruction. */
3643
inst->opcode = SHADER_OPCODE_SEND;
3644
inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
3646
inst->header_size = 0;
3647
inst->send_has_side_effects = false;
3648
inst->send_is_volatile = true;
3649
inst->exec_size = 1;
3651
/* Finally, the payload */
3652
inst->resize_sources(3);
3653
inst->src[0] = brw_imm_ud(0); /* desc */
3654
inst->src[1] = ex_desc;
3655
inst->src[2] = payload;
3657
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
3658
} else if (devinfo->ver >= 7) {
3659
const fs_builder ubld = fs_builder(this, block, inst).exec_all();
3660
const fs_reg payload = ubld.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD);
3662
ubld.group(8, 0).MOV(payload,
3663
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
3664
ubld.group(1, 0).MOV(component(payload, 2),
3665
brw_imm_ud(offset_B.ud / 16));
3667
inst->opcode = FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7;
3668
inst->src[1] = payload;
3669
inst->header_size = 1;
3672
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
3674
/* Before register allocation, we didn't tell the scheduler about the
3675
* MRF we use. We know it's safe to use this MRF because nothing
3676
* else does except for register spill/unspill, which generates and
3677
* uses its MRF within a single IR instruction.
3679
inst->base_mrf = FIRST_PULL_LOAD_MRF(devinfo->ver) + 1;
3686
fs_visitor::lower_load_payload()
3688
bool progress = false;
3690
foreach_block_and_inst_safe (block, fs_inst, inst, cfg) {
3691
if (inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD)
3694
assert(inst->dst.file == MRF || inst->dst.file == VGRF);
3695
assert(inst->saturate == false);
3696
fs_reg dst = inst->dst;
3698
/* Get rid of COMPR4. We'll add it back in if we need it */
3699
if (dst.file == MRF)
3700
dst.nr = dst.nr & ~BRW_MRF_COMPR4;
3702
const fs_builder ibld(this, block, inst);
3703
const fs_builder ubld = ibld.exec_all();
3705
for (uint8_t i = 0; i < inst->header_size;) {
3706
/* Number of header GRFs to initialize at once with a single MOV
3710
(i + 1 < inst->header_size && inst->src[i].stride == 1 &&
3711
inst->src[i + 1].equals(byte_offset(inst->src[i], REG_SIZE))) ?
3714
if (inst->src[i].file != BAD_FILE)
3715
ubld.group(8 * n, 0).MOV(retype(dst, BRW_REGISTER_TYPE_UD),
3716
retype(inst->src[i], BRW_REGISTER_TYPE_UD));
3718
dst = byte_offset(dst, n * REG_SIZE);
3722
if (inst->dst.file == MRF && (inst->dst.nr & BRW_MRF_COMPR4) &&
3723
inst->exec_size > 8) {
3724
/* In this case, the payload portion of the LOAD_PAYLOAD isn't
3725
* a straightforward copy. Instead, the result of the
3726
* LOAD_PAYLOAD is treated as interleaved and the first four
3727
* non-header sources are unpacked as:
3738
* This is used for gen <= 5 fb writes.
3740
assert(inst->exec_size == 16);
3741
assert(inst->header_size + 4 <= inst->sources);
3742
for (uint8_t i = inst->header_size; i < inst->header_size + 4; i++) {
3743
if (inst->src[i].file != BAD_FILE) {
3744
if (devinfo->has_compr4) {
3745
fs_reg compr4_dst = retype(dst, inst->src[i].type);
3746
compr4_dst.nr |= BRW_MRF_COMPR4;
3747
ibld.MOV(compr4_dst, inst->src[i]);
3749
/* Platform doesn't have COMPR4. We have to fake it */
3750
fs_reg mov_dst = retype(dst, inst->src[i].type);
3751
ibld.quarter(0).MOV(mov_dst, quarter(inst->src[i], 0));
3753
ibld.quarter(1).MOV(mov_dst, quarter(inst->src[i], 1));
3760
/* The loop above only ever incremented us through the first set
3761
* of 4 registers. However, thanks to the magic of COMPR4, we
3762
* actually wrote to the first 8 registers, so we need to take
3763
* that into account now.
3767
/* The COMPR4 code took care of the first 4 sources. We'll let
3768
* the regular path handle any remaining sources. Yes, we are
3769
* modifying the instruction but we're about to delete it so
3770
* this really doesn't hurt anything.
3772
inst->header_size += 4;
3775
for (uint8_t i = inst->header_size; i < inst->sources; i++) {
3776
dst.type = inst->src[i].type;
3777
if (inst->src[i].file != BAD_FILE) {
3778
ibld.MOV(dst, inst->src[i]);
3780
dst = offset(dst, ibld, 1);
3783
inst->remove(block);
3788
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
3794
fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block)
3796
const fs_builder ibld(this, block, inst);
3798
const bool ud = (inst->src[1].type == BRW_REGISTER_TYPE_UD);
3799
if (inst->src[1].file == IMM &&
3800
(( ud && inst->src[1].ud <= UINT16_MAX) ||
3801
(!ud && inst->src[1].d <= INT16_MAX && inst->src[1].d >= INT16_MIN))) {
3802
/* The MUL instruction isn't commutative. On Gen <= 6, only the low
3803
* 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3806
* If multiplying by an immediate value that fits in 16-bits, do a
3807
* single MUL instruction with that value in the proper location.
3809
if (devinfo->ver < 7) {
3810
fs_reg imm(VGRF, alloc.allocate(dispatch_width / 8), inst->dst.type);
3811
ibld.MOV(imm, inst->src[1]);
3812
ibld.MUL(inst->dst, imm, inst->src[0]);
3814
ibld.MUL(inst->dst, inst->src[0],
3815
ud ? brw_imm_uw(inst->src[1].ud)
3816
: brw_imm_w(inst->src[1].d));
3819
/* Gen < 8 (and some Gfx8+ low-power parts like Cherryview) cannot
3820
* do 32-bit integer multiplication in one instruction, but instead
3821
* must do a sequence (which actually calculates a 64-bit result):
3823
* mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3824
* mach(8) null g3<8,8,1>D g4<8,8,1>D
3825
* mov(8) g2<1>D acc0<8,8,1>D
3827
* But on Gen > 6, the ability to use second accumulator register
3828
* (acc1) for non-float data types was removed, preventing a simple
3829
* implementation in SIMD16. A 16-channel result can be calculated by
3830
* executing the three instructions twice in SIMD8, once with quarter
3831
* control of 1Q for the first eight channels and again with 2Q for
3832
* the second eight channels.
3834
* Which accumulator register is implicitly accessed (by AccWrEnable
3835
* for instance) is determined by the quarter control. Unfortunately
3836
* Ivybridge (and presumably Baytrail) has a hardware bug in which an
3837
* implicit accumulator access by an instruction with 2Q will access
3838
* acc1 regardless of whether the data type is usable in acc1.
3840
* Specifically, the 2Q mach(8) writes acc1 which does not exist for
3841
* integer data types.
3843
* Since we only want the low 32-bits of the result, we can do two
3844
* 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3845
* adjust the high result and add them (like the mach is doing):
3847
* mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3848
* mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3849
* shl(8) g9<1>D g8<8,8,1>D 16D
3850
* add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3852
* We avoid the shl instruction by realizing that we only want to add
3853
* the low 16-bits of the "high" result to the high 16-bits of the
3854
* "low" result and using proper regioning on the add:
3856
* mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3857
* mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3858
* add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3860
* Since it does not use the (single) accumulator register, we can
3861
* schedule multi-component multiplications much better.
3864
bool needs_mov = false;
3865
fs_reg orig_dst = inst->dst;
3867
/* Get a new VGRF for the "low" 32x16-bit multiplication result if
3868
* reusing the original destination is impossible due to hardware
3869
* restrictions, source/destination overlap, or it being the null
3872
fs_reg low = inst->dst;
3873
if (orig_dst.is_null() || orig_dst.file == MRF ||
3874
regions_overlap(inst->dst, inst->size_written,
3875
inst->src[0], inst->size_read(0)) ||
3876
regions_overlap(inst->dst, inst->size_written,
3877
inst->src[1], inst->size_read(1)) ||
3878
inst->dst.stride >= 4) {
3880
low = fs_reg(VGRF, alloc.allocate(regs_written(inst)),
3884
/* Get a new VGRF but keep the same stride as inst->dst */
3885
fs_reg high(VGRF, alloc.allocate(regs_written(inst)), inst->dst.type);
3886
high.stride = inst->dst.stride;
3887
high.offset = inst->dst.offset % REG_SIZE;
3889
if (devinfo->ver >= 7) {
3890
/* From Wa_1604601757:
3892
* "When multiplying a DW and any lower precision integer, source modifier
3893
* is not supported."
3895
* An unsupported negate modifier on src[1] would ordinarily be
3896
* lowered by the subsequent lower_regioning pass. In this case that
3897
* pass would spawn another dword multiply. Instead, lower the
3900
const bool source_mods_unsupported = (devinfo->ver >= 12);
3902
if (inst->src[1].abs || (inst->src[1].negate &&
3903
source_mods_unsupported))
3904
lower_src_modifiers(this, block, inst, 1);
3906
if (inst->src[1].file == IMM) {
3907
ibld.MUL(low, inst->src[0],
3908
brw_imm_uw(inst->src[1].ud & 0xffff));
3909
ibld.MUL(high, inst->src[0],
3910
brw_imm_uw(inst->src[1].ud >> 16));
3912
ibld.MUL(low, inst->src[0],
3913
subscript(inst->src[1], BRW_REGISTER_TYPE_UW, 0));
3914
ibld.MUL(high, inst->src[0],
3915
subscript(inst->src[1], BRW_REGISTER_TYPE_UW, 1));
3918
if (inst->src[0].abs)
3919
lower_src_modifiers(this, block, inst, 0);
3921
ibld.MUL(low, subscript(inst->src[0], BRW_REGISTER_TYPE_UW, 0),
3923
ibld.MUL(high, subscript(inst->src[0], BRW_REGISTER_TYPE_UW, 1),
3927
ibld.ADD(subscript(low, BRW_REGISTER_TYPE_UW, 1),
3928
subscript(low, BRW_REGISTER_TYPE_UW, 1),
3929
subscript(high, BRW_REGISTER_TYPE_UW, 0));
3931
if (needs_mov || inst->conditional_mod)
3932
set_condmod(inst->conditional_mod, ibld.MOV(orig_dst, low));
3937
fs_visitor::lower_mul_qword_inst(fs_inst *inst, bblock_t *block)
3939
const fs_builder ibld(this, block, inst);
3941
/* Considering two 64-bit integers ab and cd where each letter ab
3942
* corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd
3943
* only need to provide the YZ part of the result. -------
3945
* Only BD needs to be 64 bits. For AD and BC we only care + AD
3946
* about the lower 32 bits (since they are part of the upper + BC
3947
* 32 bits of our result). AC is not needed since it starts + AC
3948
* on the 65th bit of the result. -------
3951
unsigned int q_regs = regs_written(inst);
3952
unsigned int d_regs = (q_regs + 1) / 2;
3954
fs_reg bd(VGRF, alloc.allocate(q_regs), BRW_REGISTER_TYPE_UQ);
3955
fs_reg ad(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD);
3956
fs_reg bc(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD);
3958
/* Here we need the full 64 bit result for 32b * 32b. */
3959
if (devinfo->has_integer_dword_mul) {
3960
ibld.MUL(bd, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
3961
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0));
3963
fs_reg bd_high(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD);
3964
fs_reg bd_low(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD);
3965
fs_reg acc = retype(brw_acc_reg(inst->exec_size), BRW_REGISTER_TYPE_UD);
3967
fs_inst *mul = ibld.MUL(acc,
3968
subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
3969
subscript(inst->src[1], BRW_REGISTER_TYPE_UW, 0));
3970
mul->writes_accumulator = true;
3972
ibld.MACH(bd_high, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
3973
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0));
3974
ibld.MOV(bd_low, acc);
3976
ibld.MOV(subscript(bd, BRW_REGISTER_TYPE_UD, 0), bd_low);
3977
ibld.MOV(subscript(bd, BRW_REGISTER_TYPE_UD, 1), bd_high);
3980
ibld.MUL(ad, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 1),
3981
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0));
3982
ibld.MUL(bc, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
3983
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 1));
3985
ibld.ADD(ad, ad, bc);
3986
ibld.ADD(subscript(bd, BRW_REGISTER_TYPE_UD, 1),
3987
subscript(bd, BRW_REGISTER_TYPE_UD, 1), ad);
3989
if (devinfo->has_64bit_int) {
3990
ibld.MOV(inst->dst, bd);
3992
ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 0),
3993
subscript(bd, BRW_REGISTER_TYPE_UD, 0));
3994
ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 1),
3995
subscript(bd, BRW_REGISTER_TYPE_UD, 1));
4000
fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block)
4002
const fs_builder ibld(this, block, inst);
4004
/* According to the BDW+ BSpec page for the "Multiply Accumulate
4005
* High" instruction:
4007
* "An added preliminary mov is required for source modification on
4009
* mov (8) r3.0<1>:d -r3<8;8,1>:d
4010
* mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
4011
* mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
4013
if (devinfo->ver >= 8 && (inst->src[1].negate || inst->src[1].abs))
4014
lower_src_modifiers(this, block, inst, 1);
4016
/* Should have been lowered to 8-wide. */
4017
assert(inst->exec_size <= get_lowered_simd_width(devinfo, inst));
4018
const fs_reg acc = retype(brw_acc_reg(inst->exec_size), inst->dst.type);
4019
fs_inst *mul = ibld.MUL(acc, inst->src[0], inst->src[1]);
4020
fs_inst *mach = ibld.MACH(inst->dst, inst->src[0], inst->src[1]);
4022
if (devinfo->ver >= 8) {
4023
/* Until Gfx8, integer multiplies read 32-bits from one source,
4024
* and 16-bits from the other, and relying on the MACH instruction
4025
* to generate the high bits of the result.
4027
* On Gfx8, the multiply instruction does a full 32x32-bit
4028
* multiply, but in order to do a 64-bit multiply we can simulate
4029
* the previous behavior and then use a MACH instruction.
4031
assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
4032
mul->src[1].type == BRW_REGISTER_TYPE_UD);
4033
mul->src[1].type = BRW_REGISTER_TYPE_UW;
4034
mul->src[1].stride *= 2;
4036
if (mul->src[1].file == IMM) {
4037
mul->src[1] = brw_imm_uw(mul->src[1].ud);
4039
} else if (devinfo->verx10 == 70 &&
4041
/* Among other things the quarter control bits influence which
4042
* accumulator register is used by the hardware for instructions
4043
* that access the accumulator implicitly (e.g. MACH). A
4044
* second-half instruction would normally map to acc1, which
4045
* doesn't exist on Gfx7 and up (the hardware does emulate it for
4046
* floating-point instructions *only* by taking advantage of the
4047
* extra precision of acc0 not normally used for floating point
4050
* HSW and up are careful enough not to try to access an
4051
* accumulator register that doesn't exist, but on earlier Gfx7
4052
* hardware we need to make sure that the quarter control bits are
4053
* zero to avoid non-deterministic behaviour and emit an extra MOV
4054
* to get the result masked correctly according to the current
4058
mach->force_writemask_all = true;
4059
mach->dst = ibld.vgrf(inst->dst.type);
4060
ibld.MOV(inst->dst, mach->dst);
4065
fs_visitor::lower_integer_multiplication()
4067
bool progress = false;
4069
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
4070
if (inst->opcode == BRW_OPCODE_MUL) {
4071
/* If the instruction is already in a form that does not need lowering,
4074
if (devinfo->ver >= 7) {
4075
if (type_sz(inst->src[1].type) < 4 && type_sz(inst->src[0].type) <= 4)
4078
if (type_sz(inst->src[0].type) < 4 && type_sz(inst->src[1].type) <= 4)
4082
if ((inst->dst.type == BRW_REGISTER_TYPE_Q ||
4083
inst->dst.type == BRW_REGISTER_TYPE_UQ) &&
4084
(inst->src[0].type == BRW_REGISTER_TYPE_Q ||
4085
inst->src[0].type == BRW_REGISTER_TYPE_UQ) &&
4086
(inst->src[1].type == BRW_REGISTER_TYPE_Q ||
4087
inst->src[1].type == BRW_REGISTER_TYPE_UQ)) {
4088
lower_mul_qword_inst(inst, block);
4089
inst->remove(block);
4091
} else if (!inst->dst.is_accumulator() &&
4092
(inst->dst.type == BRW_REGISTER_TYPE_D ||
4093
inst->dst.type == BRW_REGISTER_TYPE_UD) &&
4094
(!devinfo->has_integer_dword_mul ||
4095
devinfo->verx10 >= 125)) {
4096
lower_mul_dword_inst(inst, block);
4097
inst->remove(block);
4100
} else if (inst->opcode == SHADER_OPCODE_MULH) {
4101
lower_mulh_inst(inst, block);
4102
inst->remove(block);
4109
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
4115
fs_visitor::lower_minmax()
4117
assert(devinfo->ver < 6);
4119
bool progress = false;
4121
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
4122
const fs_builder ibld(this, block, inst);
4124
if (inst->opcode == BRW_OPCODE_SEL &&
4125
inst->predicate == BRW_PREDICATE_NONE) {
4126
/* If src1 is an immediate value that is not NaN, then it can't be
4127
* NaN. In that case, emit CMP because it is much better for cmod
4128
* propagation. Likewise if src1 is not float. Gfx4 and Gfx5 don't
4129
* support HF or DF, so it is not necessary to check for those.
4131
if (inst->src[1].type != BRW_REGISTER_TYPE_F ||
4132
(inst->src[1].file == IMM && !isnan(inst->src[1].f))) {
4133
ibld.CMP(ibld.null_reg_d(), inst->src[0], inst->src[1],
4134
inst->conditional_mod);
4136
ibld.CMPN(ibld.null_reg_d(), inst->src[0], inst->src[1],
4137
inst->conditional_mod);
4139
inst->predicate = BRW_PREDICATE_NORMAL;
4140
inst->conditional_mod = BRW_CONDITIONAL_NONE;
4147
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
4153
fs_visitor::lower_sub_sat()
4155
bool progress = false;
4157
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
4158
const fs_builder ibld(this, block, inst);
4160
if (inst->opcode == SHADER_OPCODE_USUB_SAT ||
4161
inst->opcode == SHADER_OPCODE_ISUB_SAT) {
4162
/* The fundamental problem is the hardware performs source negation
4163
* at the bit width of the source. If the source is 0x80000000D, the
4164
* negation is 0x80000000D. As a result, subtractSaturate(0,
4165
* 0x80000000) will produce 0x80000000 instead of 0x7fffffff. There
4166
* are at least three ways to resolve this:
4168
* 1. Use the accumulator for the negated source. The accumulator is
4169
* 33 bits, so our source 0x80000000 is sign-extended to
4170
* 0x1800000000. The negation of which is 0x080000000. This
4171
* doesn't help for 64-bit integers (which are already bigger than
4172
* 33 bits). There are also only 8 accumulators, so SIMD16 or
4173
* SIMD32 instructions would have to be split into multiple SIMD8
4176
* 2. Use slightly different math. For any n-bit value x, we know (x
4177
* >> 1) != -(x >> 1). We can use this fact to only do
4178
* subtractions involving (x >> 1). subtractSaturate(a, b) ==
4179
* subtractSaturate(subtractSaturate(a, (b >> 1)), b - (b >> 1)).
4181
* 3. For unsigned sources, it is sufficient to replace the
4182
* subtractSaturate with (a > b) ? a - b : 0.
4184
* It may also be possible to use the SUBB instruction. This
4185
* implicitly writes the accumulator, so it could only be used in the
4186
* same situations as #1 above. It is further limited by only
4187
* allowing UD sources.
4189
if (inst->exec_size == 8 && inst->src[0].type != BRW_REGISTER_TYPE_Q &&
4190
inst->src[0].type != BRW_REGISTER_TYPE_UQ) {
4191
fs_reg acc(ARF, BRW_ARF_ACCUMULATOR, inst->src[1].type);
4193
ibld.MOV(acc, inst->src[1]);
4194
fs_inst *add = ibld.ADD(inst->dst, acc, inst->src[0]);
4195
add->saturate = true;
4196
add->src[0].negate = true;
4197
} else if (inst->opcode == SHADER_OPCODE_ISUB_SAT) {
4199
* dst = add.sat(add.sat(src0, -tmp), -(src1 - tmp));
4201
fs_reg tmp1 = ibld.vgrf(inst->src[0].type);
4202
fs_reg tmp2 = ibld.vgrf(inst->src[0].type);
4203
fs_reg tmp3 = ibld.vgrf(inst->src[0].type);
4206
ibld.SHR(tmp1, inst->src[1], brw_imm_d(1));
4208
add = ibld.ADD(tmp2, inst->src[1], tmp1);
4209
add->src[1].negate = true;
4211
add = ibld.ADD(tmp3, inst->src[0], tmp1);
4212
add->src[1].negate = true;
4213
add->saturate = true;
4215
add = ibld.ADD(inst->dst, tmp3, tmp2);
4216
add->src[1].negate = true;
4217
add->saturate = true;
4219
/* a > b ? a - b : 0 */
4220
ibld.CMP(ibld.null_reg_d(), inst->src[0], inst->src[1],
4223
fs_inst *add = ibld.ADD(inst->dst, inst->src[0], inst->src[1]);
4224
add->src[1].negate = !add->src[1].negate;
4226
ibld.SEL(inst->dst, inst->dst, brw_imm_ud(0))
4227
->predicate = BRW_PREDICATE_NORMAL;
4230
inst->remove(block);
4236
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
4242
* Get the mask of SIMD channels enabled during dispatch and not yet disabled
4243
* by discard. Due to the layout of the sample mask in the fragment shader
4244
* thread payload, \p bld is required to have a dispatch_width() not greater
4245
* than 16 for fragment shaders.
4248
sample_mask_reg(const fs_builder &bld)
4250
const fs_visitor *v = static_cast<const fs_visitor *>(bld.shader);
4252
if (v->stage != MESA_SHADER_FRAGMENT) {
4253
return brw_imm_ud(0xffffffff);
4254
} else if (brw_wm_prog_data(v->stage_prog_data)->uses_kill) {
4255
assert(bld.dispatch_width() <= 16);
4256
return brw_flag_subreg(sample_mask_flag_subreg(v) + bld.group() / 16);
4258
assert(v->devinfo->ver >= 6 && bld.dispatch_width() <= 16);
4259
return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7),
4260
BRW_REGISTER_TYPE_UW);
4265
setup_color_payload(const fs_builder &bld, const brw_wm_prog_key *key,
4266
fs_reg *dst, fs_reg color, unsigned components)
4268
if (key->clamp_fragment_color) {
4269
fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, 4);
4270
assert(color.type == BRW_REGISTER_TYPE_F);
4272
for (unsigned i = 0; i < components; i++)
4274
bld.MOV(offset(tmp, bld, i), offset(color, bld, i)));
4279
for (unsigned i = 0; i < components; i++)
4280
dst[i] = offset(color, bld, i);
4284
brw_fb_write_msg_control(const fs_inst *inst,
4285
const struct brw_wm_prog_data *prog_data)
4289
if (inst->opcode == FS_OPCODE_REP_FB_WRITE) {
4290
assert(inst->group == 0 && inst->exec_size == 16);
4291
mctl = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
4292
} else if (prog_data->dual_src_blend) {
4293
assert(inst->exec_size == 8);
4295
if (inst->group % 16 == 0)
4296
mctl = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
4297
else if (inst->group % 16 == 8)
4298
mctl = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
4300
unreachable("Invalid dual-source FB write instruction group");
4302
assert(inst->group == 0 || (inst->group == 16 && inst->exec_size == 16));
4304
if (inst->exec_size == 16)
4305
mctl = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
4306
else if (inst->exec_size == 8)
4307
mctl = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
4309
unreachable("Invalid FB write execution size");
4316
lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
4317
const struct brw_wm_prog_data *prog_data,
4318
const brw_wm_prog_key *key,
4319
const fs_visitor::thread_payload &payload)
4321
assert(inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM);
4322
const intel_device_info *devinfo = bld.shader->devinfo;
4323
const fs_reg &color0 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR0];
4324
const fs_reg &color1 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR1];
4325
const fs_reg &src0_alpha = inst->src[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA];
4326
const fs_reg &src_depth = inst->src[FB_WRITE_LOGICAL_SRC_SRC_DEPTH];
4327
const fs_reg &dst_depth = inst->src[FB_WRITE_LOGICAL_SRC_DST_DEPTH];
4328
const fs_reg &src_stencil = inst->src[FB_WRITE_LOGICAL_SRC_SRC_STENCIL];
4329
fs_reg sample_mask = inst->src[FB_WRITE_LOGICAL_SRC_OMASK];
4330
const unsigned components =
4331
inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].ud;
4333
assert(inst->target != 0 || src0_alpha.file == BAD_FILE);
4335
/* We can potentially have a message length of up to 15, so we have to set
4336
* base_mrf to either 0 or 1 in order to fit in m0..m15.
4339
int header_size = 2, payload_header_size;
4340
unsigned length = 0;
4342
if (devinfo->ver < 6) {
4343
/* TODO: Support SIMD32 on gfx4-5 */
4344
assert(bld.group() < 16);
4346
/* For gfx4-5, we always have a header consisting of g0 and g1. We have
4347
* an implied MOV from g0,g1 to the start of the message. The MOV from
4348
* g0 is handled by the hardware and the MOV from g1 is provided by the
4349
* generator. This is required because, on gfx4-5, the generator may
4350
* generate two write messages with different message lengths in order
4351
* to handle AA data properly.
4353
* Also, since the pixel mask goes in the g0 portion of the message and
4354
* since render target writes are the last thing in the shader, we write
4355
* the pixel mask directly into g0 and it will get copied as part of the
4358
if (prog_data->uses_kill) {
4359
bld.exec_all().group(1, 0)
4360
.MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW),
4361
sample_mask_reg(bld));
4364
assert(length == 0);
4366
} else if ((devinfo->verx10 <= 70 &&
4367
prog_data->uses_kill) ||
4368
(devinfo->ver < 11 &&
4369
(color1.file != BAD_FILE || key->nr_color_regions > 1))) {
4370
/* From the Sandy Bridge PRM, volume 4, page 198:
4372
* "Dispatched Pixel Enables. One bit per pixel indicating
4373
* which pixels were originally enabled when the thread was
4374
* dispatched. This field is only required for the end-of-
4375
* thread message and on all dual-source messages."
4377
const fs_builder ubld = bld.exec_all().group(8, 0);
4379
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2);
4380
if (bld.group() < 16) {
4381
/* The header starts off as g0 and g1 for the first half */
4382
ubld.group(16, 0).MOV(header, retype(brw_vec8_grf(0, 0),
4383
BRW_REGISTER_TYPE_UD));
4385
/* The header starts off as g0 and g2 for the second half */
4386
assert(bld.group() < 32);
4387
const fs_reg header_sources[2] = {
4388
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD),
4389
retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD),
4391
ubld.LOAD_PAYLOAD(header, header_sources, 2, 0);
4393
/* Gfx12 will require additional fix-ups if we ever hit this path. */
4394
assert(devinfo->ver < 12);
4397
uint32_t g00_bits = 0;
4399
/* Set "Source0 Alpha Present to RenderTarget" bit in message
4402
if (src0_alpha.file != BAD_FILE)
4403
g00_bits |= 1 << 11;
4405
/* Set computes stencil to render target */
4406
if (prog_data->computed_stencil)
4407
g00_bits |= 1 << 14;
4410
/* OR extra bits into g0.0 */
4411
ubld.group(1, 0).OR(component(header, 0),
4412
retype(brw_vec1_grf(0, 0),
4413
BRW_REGISTER_TYPE_UD),
4414
brw_imm_ud(g00_bits));
4417
/* Set the render target index for choosing BLEND_STATE. */
4418
if (inst->target > 0) {
4419
ubld.group(1, 0).MOV(component(header, 2), brw_imm_ud(inst->target));
4422
if (prog_data->uses_kill) {
4423
ubld.group(1, 0).MOV(retype(component(header, 15),
4424
BRW_REGISTER_TYPE_UW),
4425
sample_mask_reg(bld));
4428
assert(length == 0);
4429
sources[0] = header;
4430
sources[1] = horiz_offset(header, 8);
4433
assert(length == 0 || length == 2);
4434
header_size = length;
4436
if (payload.aa_dest_stencil_reg[0]) {
4437
assert(inst->group < 16);
4438
sources[length] = fs_reg(VGRF, bld.shader->alloc.allocate(1));
4439
bld.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4440
.MOV(sources[length],
4441
fs_reg(brw_vec8_grf(payload.aa_dest_stencil_reg[0], 0)));
4445
if (src0_alpha.file != BAD_FILE) {
4446
for (unsigned i = 0; i < bld.dispatch_width() / 8; i++) {
4447
const fs_builder &ubld = bld.exec_all().group(8, i)
4448
.annotate("FB write src0 alpha");
4449
const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_F);
4450
ubld.MOV(tmp, horiz_offset(src0_alpha, i * 8));
4451
setup_color_payload(ubld, key, &sources[length], tmp, 1);
4456
if (sample_mask.file != BAD_FILE) {
4457
sources[length] = fs_reg(VGRF, bld.shader->alloc.allocate(1),
4458
BRW_REGISTER_TYPE_UD);
4460
/* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4461
* relevant. Since it's unsigned single words one vgrf is always
4462
* 16-wide, but only the lower or higher 8 channels will be used by the
4463
* hardware when doing a SIMD8 write depending on whether we have
4464
* selected the subspans for the first or second half respectively.
4466
assert(sample_mask.file != BAD_FILE && type_sz(sample_mask.type) == 4);
4467
sample_mask.type = BRW_REGISTER_TYPE_UW;
4468
sample_mask.stride *= 2;
4470
bld.exec_all().annotate("FB write oMask")
4471
.MOV(horiz_offset(retype(sources[length], BRW_REGISTER_TYPE_UW),
4477
payload_header_size = length;
4479
setup_color_payload(bld, key, &sources[length], color0, components);
4482
if (color1.file != BAD_FILE) {
4483
setup_color_payload(bld, key, &sources[length], color1, components);
4487
if (src_depth.file != BAD_FILE) {
4488
sources[length] = src_depth;
4492
if (dst_depth.file != BAD_FILE) {
4493
sources[length] = dst_depth;
4497
if (src_stencil.file != BAD_FILE) {
4498
assert(devinfo->ver >= 9);
4499
assert(bld.dispatch_width() == 8);
4501
/* XXX: src_stencil is only available on gfx9+. dst_depth is never
4502
* available on gfx9+. As such it's impossible to have both enabled at the
4503
* same time and therefore length cannot overrun the array.
4505
assert(length < 15);
4507
sources[length] = bld.vgrf(BRW_REGISTER_TYPE_UD);
4508
bld.exec_all().annotate("FB write OS")
4509
.MOV(retype(sources[length], BRW_REGISTER_TYPE_UB),
4510
subscript(src_stencil, BRW_REGISTER_TYPE_UB, 0));
4515
if (devinfo->ver >= 7) {
4516
/* Send from the GRF */
4517
fs_reg payload = fs_reg(VGRF, -1, BRW_REGISTER_TYPE_F);
4518
load = bld.LOAD_PAYLOAD(payload, sources, length, payload_header_size);
4519
payload.nr = bld.shader->alloc.allocate(regs_written(load));
4520
load->dst = payload;
4522
uint32_t msg_ctl = brw_fb_write_msg_control(inst, prog_data);
4525
(inst->group / 16) << 11 | /* rt slot group */
4526
brw_fb_write_desc(devinfo, inst->target, msg_ctl, inst->last_rt,
4527
prog_data->per_coarse_pixel_dispatch);
4529
uint32_t ex_desc = 0;
4530
if (devinfo->ver >= 11) {
4531
/* Set the "Render Target Index" and "Src0 Alpha Present" fields
4532
* in the extended message descriptor, in lieu of using a header.
4534
ex_desc = inst->target << 12 | (src0_alpha.file != BAD_FILE) << 15;
4536
if (key->nr_color_regions == 0)
4537
ex_desc |= 1 << 20; /* Null Render Target */
4539
inst->ex_desc = ex_desc;
4541
inst->opcode = SHADER_OPCODE_SEND;
4542
inst->resize_sources(3);
4543
inst->sfid = GFX6_SFID_DATAPORT_RENDER_CACHE;
4544
inst->src[0] = brw_imm_ud(0);
4545
inst->src[1] = brw_imm_ud(0);
4546
inst->src[2] = payload;
4547
inst->mlen = regs_written(load);
4549
inst->header_size = header_size;
4550
inst->check_tdr = true;
4551
inst->send_has_side_effects = true;
4553
/* Send from the MRF */
4554
load = bld.LOAD_PAYLOAD(fs_reg(MRF, 1, BRW_REGISTER_TYPE_F),
4555
sources, length, payload_header_size);
4557
/* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4558
* will do this for us if we just give it a COMPR4 destination.
4560
if (devinfo->ver < 6 && bld.dispatch_width() == 16)
4561
load->dst.nr |= BRW_MRF_COMPR4;
4563
if (devinfo->ver < 6) {
4564
/* Set up src[0] for the implied MOV from grf0-1 */
4565
inst->resize_sources(1);
4566
inst->src[0] = brw_vec8_grf(0, 0);
4568
inst->resize_sources(0);
4571
inst->opcode = FS_OPCODE_FB_WRITE;
4572
inst->mlen = regs_written(load);
4573
inst->header_size = header_size;
4578
lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst)
4580
const intel_device_info *devinfo = bld.shader->devinfo;
4581
const fs_builder &ubld = bld.exec_all().group(8, 0);
4582
const unsigned length = 2;
4583
const fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD, length);
4585
if (bld.group() < 16) {
4586
ubld.group(16, 0).MOV(header, retype(brw_vec8_grf(0, 0),
4587
BRW_REGISTER_TYPE_UD));
4589
assert(bld.group() < 32);
4590
const fs_reg header_sources[] = {
4591
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD),
4592
retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD)
4594
ubld.LOAD_PAYLOAD(header, header_sources, ARRAY_SIZE(header_sources), 0);
4596
if (devinfo->ver >= 12) {
4597
/* On Gfx12 the Viewport and Render Target Array Index fields (AKA
4598
* Poly 0 Info) are provided in r1.1 instead of r0.0, and the render
4599
* target message header format was updated accordingly -- However
4600
* the updated format only works for the lower 16 channels in a
4601
* SIMD32 thread, since the higher 16 channels want the subspan data
4602
* from r2 instead of r1, so we need to copy over the contents of
4603
* r1.1 in order to fix things up.
4605
ubld.group(1, 0).MOV(component(header, 9),
4606
retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_UD));
4610
/* BSpec 12470 (Gfx8-11), BSpec 47842 (Gfx12+) :
4612
* "Must be zero for Render Target Read message."
4615
* - 14 : Stencil Present to Render Target
4616
* - 13 : Source Depth Present to Render Target
4617
* - 12 : oMask to Render Target
4618
* - 11 : Source0 Alpha Present to Render Target
4620
ubld.group(1, 0).AND(component(header, 0),
4621
component(header, 0),
4622
brw_imm_ud(~INTEL_MASK(14, 11)));
4624
inst->resize_sources(1);
4625
inst->src[0] = header;
4626
inst->opcode = FS_OPCODE_FB_READ;
4627
inst->mlen = length;
4628
inst->header_size = length;
4632
lower_sampler_logical_send_gfx4(const fs_builder &bld, fs_inst *inst, opcode op,
4633
const fs_reg &coordinate,
4634
const fs_reg &shadow_c,
4635
const fs_reg &lod, const fs_reg &lod2,
4636
const fs_reg &surface,
4637
const fs_reg &sampler,
4638
unsigned coord_components,
4639
unsigned grad_components)
4641
const bool has_lod = (op == SHADER_OPCODE_TXL || op == FS_OPCODE_TXB ||
4642
op == SHADER_OPCODE_TXF || op == SHADER_OPCODE_TXS);
4643
fs_reg msg_begin(MRF, 1, BRW_REGISTER_TYPE_F);
4644
fs_reg msg_end = msg_begin;
4647
msg_end = offset(msg_end, bld.group(8, 0), 1);
4649
for (unsigned i = 0; i < coord_components; i++)
4650
bld.MOV(retype(offset(msg_end, bld, i), coordinate.type),
4651
offset(coordinate, bld, i));
4653
msg_end = offset(msg_end, bld, coord_components);
4655
/* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4656
* require all three components to be present and zero if they are unused.
4658
if (coord_components > 0 &&
4659
(has_lod || shadow_c.file != BAD_FILE ||
4660
(op == SHADER_OPCODE_TEX && bld.dispatch_width() == 8))) {
4661
assert(coord_components <= 3);
4662
for (unsigned i = 0; i < 3 - coord_components; i++)
4663
bld.MOV(offset(msg_end, bld, i), brw_imm_f(0.0f));
4665
msg_end = offset(msg_end, bld, 3 - coord_components);
4668
if (op == SHADER_OPCODE_TXD) {
4669
/* TXD unsupported in SIMD16 mode. */
4670
assert(bld.dispatch_width() == 8);
4672
/* the slots for u and v are always present, but r is optional */
4673
if (coord_components < 2)
4674
msg_end = offset(msg_end, bld, 2 - coord_components);
4677
* dPdx = dudx, dvdx, drdx
4678
* dPdy = dudy, dvdy, drdy
4680
* 1-arg: Does not exist.
4682
* 2-arg: dudx dvdx dudy dvdy
4683
* dPdx.x dPdx.y dPdy.x dPdy.y
4686
* 3-arg: dudx dvdx drdx dudy dvdy drdy
4687
* dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4688
* m5 m6 m7 m8 m9 m10
4690
for (unsigned i = 0; i < grad_components; i++)
4691
bld.MOV(offset(msg_end, bld, i), offset(lod, bld, i));
4693
msg_end = offset(msg_end, bld, MAX2(grad_components, 2));
4695
for (unsigned i = 0; i < grad_components; i++)
4696
bld.MOV(offset(msg_end, bld, i), offset(lod2, bld, i));
4698
msg_end = offset(msg_end, bld, MAX2(grad_components, 2));
4702
/* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4703
* shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4705
assert(shadow_c.file != BAD_FILE ? bld.dispatch_width() == 8 :
4706
bld.dispatch_width() == 16);
4708
const brw_reg_type type =
4709
(op == SHADER_OPCODE_TXF || op == SHADER_OPCODE_TXS ?
4710
BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_F);
4711
bld.MOV(retype(msg_end, type), lod);
4712
msg_end = offset(msg_end, bld, 1);
4715
if (shadow_c.file != BAD_FILE) {
4716
if (op == SHADER_OPCODE_TEX && bld.dispatch_width() == 8) {
4717
/* There's no plain shadow compare message, so we use shadow
4718
* compare with a bias of 0.0.
4720
bld.MOV(msg_end, brw_imm_f(0.0f));
4721
msg_end = offset(msg_end, bld, 1);
4724
bld.MOV(msg_end, shadow_c);
4725
msg_end = offset(msg_end, bld, 1);
4729
inst->src[0] = reg_undef;
4730
inst->src[1] = surface;
4731
inst->src[2] = sampler;
4732
inst->resize_sources(3);
4733
inst->base_mrf = msg_begin.nr;
4734
inst->mlen = msg_end.nr - msg_begin.nr;
4735
inst->header_size = 1;
4739
lower_sampler_logical_send_gfx5(const fs_builder &bld, fs_inst *inst, opcode op,
4740
const fs_reg &coordinate,
4741
const fs_reg &shadow_c,
4742
const fs_reg &lod, const fs_reg &lod2,
4743
const fs_reg &sample_index,
4744
const fs_reg &surface,
4745
const fs_reg &sampler,
4746
unsigned coord_components,
4747
unsigned grad_components)
4749
fs_reg message(MRF, 2, BRW_REGISTER_TYPE_F);
4750
fs_reg msg_coords = message;
4751
unsigned header_size = 0;
4753
if (inst->offset != 0) {
4754
/* The offsets set up by the visitor are in the m1 header, so we can't
4761
for (unsigned i = 0; i < coord_components; i++)
4762
bld.MOV(retype(offset(msg_coords, bld, i), coordinate.type),
4763
offset(coordinate, bld, i));
4765
fs_reg msg_end = offset(msg_coords, bld, coord_components);
4766
fs_reg msg_lod = offset(msg_coords, bld, 4);
4768
if (shadow_c.file != BAD_FILE) {
4769
fs_reg msg_shadow = msg_lod;
4770
bld.MOV(msg_shadow, shadow_c);
4771
msg_lod = offset(msg_shadow, bld, 1);
4776
case SHADER_OPCODE_TXL:
4778
bld.MOV(msg_lod, lod);
4779
msg_end = offset(msg_lod, bld, 1);
4781
case SHADER_OPCODE_TXD:
4784
* dPdx = dudx, dvdx, drdx
4785
* dPdy = dudy, dvdy, drdy
4787
* Load up these values:
4788
* - dudx dudy dvdx dvdy drdx drdy
4789
* - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4792
for (unsigned i = 0; i < grad_components; i++) {
4793
bld.MOV(msg_end, offset(lod, bld, i));
4794
msg_end = offset(msg_end, bld, 1);
4796
bld.MOV(msg_end, offset(lod2, bld, i));
4797
msg_end = offset(msg_end, bld, 1);
4800
case SHADER_OPCODE_TXS:
4801
msg_lod = retype(msg_end, BRW_REGISTER_TYPE_UD);
4802
bld.MOV(msg_lod, lod);
4803
msg_end = offset(msg_lod, bld, 1);
4805
case SHADER_OPCODE_TXF:
4806
msg_lod = offset(msg_coords, bld, 3);
4807
bld.MOV(retype(msg_lod, BRW_REGISTER_TYPE_UD), lod);
4808
msg_end = offset(msg_lod, bld, 1);
4810
case SHADER_OPCODE_TXF_CMS:
4811
msg_lod = offset(msg_coords, bld, 3);
4813
bld.MOV(retype(msg_lod, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
4815
bld.MOV(retype(offset(msg_lod, bld, 1), BRW_REGISTER_TYPE_UD), sample_index);
4816
msg_end = offset(msg_lod, bld, 2);
4823
inst->src[0] = reg_undef;
4824
inst->src[1] = surface;
4825
inst->src[2] = sampler;
4826
inst->resize_sources(3);
4827
inst->base_mrf = message.nr;
4828
inst->mlen = msg_end.nr - message.nr;
4829
inst->header_size = header_size;
4831
/* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4832
assert(inst->mlen <= MAX_SAMPLER_MESSAGE_SIZE);
4836
is_high_sampler(const struct intel_device_info *devinfo, const fs_reg &sampler)
4838
if (devinfo->verx10 <= 70)
4841
return sampler.file != IMM || sampler.ud >= 16;
4845
sampler_msg_type(const intel_device_info *devinfo,
4846
opcode opcode, bool shadow_compare)
4848
assert(devinfo->ver >= 5);
4850
case SHADER_OPCODE_TEX:
4851
return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE :
4852
GFX5_SAMPLER_MESSAGE_SAMPLE;
4854
return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE :
4855
GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS;
4856
case SHADER_OPCODE_TXL:
4857
return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE :
4858
GFX5_SAMPLER_MESSAGE_SAMPLE_LOD;
4859
case SHADER_OPCODE_TXL_LZ:
4860
return shadow_compare ? GFX9_SAMPLER_MESSAGE_SAMPLE_C_LZ :
4861
GFX9_SAMPLER_MESSAGE_SAMPLE_LZ;
4862
case SHADER_OPCODE_TXS:
4863
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
4864
return GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
4865
case SHADER_OPCODE_TXD:
4866
assert(!shadow_compare || devinfo->verx10 >= 75);
4867
return shadow_compare ? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE :
4868
GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
4869
case SHADER_OPCODE_TXF:
4870
return GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
4871
case SHADER_OPCODE_TXF_LZ:
4872
assert(devinfo->ver >= 9);
4873
return GFX9_SAMPLER_MESSAGE_SAMPLE_LD_LZ;
4874
case SHADER_OPCODE_TXF_CMS_W:
4875
assert(devinfo->ver >= 9);
4876
return GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
4877
case SHADER_OPCODE_TXF_CMS:
4878
return devinfo->ver >= 7 ? GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS :
4879
GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
4880
case SHADER_OPCODE_TXF_UMS:
4881
assert(devinfo->ver >= 7);
4882
return GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
4883
case SHADER_OPCODE_TXF_MCS:
4884
assert(devinfo->ver >= 7);
4885
return GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
4886
case SHADER_OPCODE_LOD:
4887
return GFX5_SAMPLER_MESSAGE_LOD;
4888
case SHADER_OPCODE_TG4:
4889
assert(devinfo->ver >= 7);
4890
return shadow_compare ? GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C :
4891
GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
4893
case SHADER_OPCODE_TG4_OFFSET:
4894
assert(devinfo->ver >= 7);
4895
return shadow_compare ? GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C :
4896
GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
4897
case SHADER_OPCODE_SAMPLEINFO:
4898
return GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
4900
unreachable("not reached");
4905
* Emit a LOAD_PAYLOAD instruction while ensuring the sources are aligned to
4906
* the given requested_alignment_sz.
4909
emit_load_payload_with_padding(const fs_builder &bld, const fs_reg &dst,
4910
const fs_reg *src, unsigned sources,
4911
unsigned header_size,
4912
unsigned requested_alignment_sz)
4914
unsigned length = 0;
4916
sources * DIV_ROUND_UP(requested_alignment_sz, bld.dispatch_width());
4917
fs_reg *src_comps = new fs_reg[num_srcs];
4919
for (unsigned i = 0; i < header_size; i++)
4920
src_comps[length++] = src[i];
4922
for (unsigned i = header_size; i < sources; i++) {
4924
retype(dst, src[i].type).component_size(bld.dispatch_width());
4925
const enum brw_reg_type padding_payload_type =
4926
brw_reg_type_from_bit_size(type_sz(src[i].type) * 8,
4927
BRW_REGISTER_TYPE_UD);
4929
src_comps[length++] = src[i];
4931
/* Expand the real sources if component of requested payload type is
4932
* larger than real source component.
4934
if (src_sz < requested_alignment_sz) {
4935
for (unsigned j = 0; j < (requested_alignment_sz / src_sz) - 1; j++) {
4936
src_comps[length++] = retype(fs_reg(), padding_payload_type);
4941
fs_inst *inst = bld.LOAD_PAYLOAD(dst, src_comps, length, header_size);
4948
lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
4949
const fs_reg &coordinate,
4950
const fs_reg &shadow_c,
4951
fs_reg lod, const fs_reg &lod2,
4952
const fs_reg &min_lod,
4953
const fs_reg &sample_index,
4955
const fs_reg &surface,
4956
const fs_reg &sampler,
4957
const fs_reg &surface_handle,
4958
const fs_reg &sampler_handle,
4959
const fs_reg &tg4_offset,
4960
unsigned payload_type_bit_size,
4961
unsigned coord_components,
4962
unsigned grad_components)
4964
const intel_device_info *devinfo = bld.shader->devinfo;
4965
const enum brw_reg_type payload_type =
4966
brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_F);
4967
const enum brw_reg_type payload_unsigned_type =
4968
brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_UD);
4969
const enum brw_reg_type payload_signed_type =
4970
brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_D);
4971
unsigned reg_width = bld.dispatch_width() / 8;
4972
unsigned header_size = 0, length = 0;
4973
fs_reg sources[MAX_SAMPLER_MESSAGE_SIZE];
4974
for (unsigned i = 0; i < ARRAY_SIZE(sources); i++)
4975
sources[i] = bld.vgrf(payload_type);
4977
/* We must have exactly one of surface/sampler and surface/sampler_handle */
4978
assert((surface.file == BAD_FILE) != (surface_handle.file == BAD_FILE));
4979
assert((sampler.file == BAD_FILE) != (sampler_handle.file == BAD_FILE));
4981
if (op == SHADER_OPCODE_TG4 || op == SHADER_OPCODE_TG4_OFFSET ||
4982
inst->offset != 0 || inst->eot ||
4983
op == SHADER_OPCODE_SAMPLEINFO ||
4984
sampler_handle.file != BAD_FILE ||
4985
is_high_sampler(devinfo, sampler)) {
4986
/* For general texture offsets (no txf workaround), we need a header to
4989
* TG4 needs to place its channel select in the header, for interaction
4990
* with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4991
* larger sampler numbers we need to offset the Sampler State Pointer in
4994
fs_reg header = retype(sources[0], BRW_REGISTER_TYPE_UD);
4998
/* If we're requesting fewer than four channels worth of response,
4999
* and we have an explicit header, we need to set up the sampler
5000
* writemask. It's reversed from normal: 1 means "don't write".
5002
if (!inst->eot && regs_written(inst) != 4 * reg_width) {
5003
assert(regs_written(inst) % reg_width == 0);
5004
unsigned mask = ~((1 << (regs_written(inst) / reg_width)) - 1) & 0xf;
5005
inst->offset |= mask << 12;
5008
/* Build the actual header */
5009
const fs_builder ubld = bld.exec_all().group(8, 0);
5010
const fs_builder ubld1 = ubld.group(1, 0);
5011
ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
5013
ubld1.MOV(component(header, 2), brw_imm_ud(inst->offset));
5014
} else if (bld.shader->stage != MESA_SHADER_VERTEX &&
5015
bld.shader->stage != MESA_SHADER_FRAGMENT) {
5016
/* The vertex and fragment stages have g0.2 set to 0, so
5017
* header0.2 is 0 when g0 is copied. Other stages may not, so we
5018
* must set it to 0 to avoid setting undesirable bits in the
5021
ubld1.MOV(component(header, 2), brw_imm_ud(0));
5024
if (sampler_handle.file != BAD_FILE) {
5025
/* Bindless sampler handles aren't relative to the sampler state
5026
* pointer passed into the shader through SAMPLER_STATE_POINTERS_*.
5027
* Instead, it's an absolute pointer relative to dynamic state base
5030
* Sampler states are 16 bytes each and the pointer we give here has
5031
* to be 32-byte aligned. In order to avoid more indirect messages
5032
* than required, we assume that all bindless sampler states are
5033
* 32-byte aligned. This sacrifices a bit of general state base
5034
* address space but means we can do something more efficient in the
5037
ubld1.MOV(component(header, 3), sampler_handle);
5038
} else if (is_high_sampler(devinfo, sampler)) {
5039
fs_reg sampler_state_ptr =
5040
retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD);
5042
/* Gfx11+ sampler message headers include bits in 4:0 which conflict
5043
* with the ones included in g0.3 bits 4:0. Mask them out.
5045
if (devinfo->ver >= 11) {
5046
sampler_state_ptr = ubld1.vgrf(BRW_REGISTER_TYPE_UD);
5047
ubld1.AND(sampler_state_ptr,
5048
retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
5049
brw_imm_ud(INTEL_MASK(31, 5)));
5052
if (sampler.file == BRW_IMMEDIATE_VALUE) {
5053
assert(sampler.ud >= 16);
5054
const int sampler_state_size = 16; /* 16 bytes */
5056
ubld1.ADD(component(header, 3), sampler_state_ptr,
5057
brw_imm_ud(16 * (sampler.ud / 16) * sampler_state_size));
5059
fs_reg tmp = ubld1.vgrf(BRW_REGISTER_TYPE_UD);
5060
ubld1.AND(tmp, sampler, brw_imm_ud(0x0f0));
5061
ubld1.SHL(tmp, tmp, brw_imm_ud(4));
5062
ubld1.ADD(component(header, 3), sampler_state_ptr, tmp);
5064
} else if (devinfo->ver >= 11) {
5065
/* Gfx11+ sampler message headers include bits in 4:0 which conflict
5066
* with the ones included in g0.3 bits 4:0. Mask them out.
5068
ubld1.AND(component(header, 3),
5069
retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
5070
brw_imm_ud(INTEL_MASK(31, 5)));
5074
if (shadow_c.file != BAD_FILE) {
5075
bld.MOV(sources[length], shadow_c);
5079
bool coordinate_done = false;
5081
/* Set up the LOD info */
5084
case SHADER_OPCODE_TXL:
5085
if (devinfo->ver >= 9 && op == SHADER_OPCODE_TXL && lod.is_zero()) {
5086
op = SHADER_OPCODE_TXL_LZ;
5089
bld.MOV(sources[length], lod);
5092
case SHADER_OPCODE_TXD:
5093
/* TXD should have been lowered in SIMD16 mode. */
5094
assert(bld.dispatch_width() == 8);
5096
/* Load dPdx and the coordinate together:
5097
* [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
5099
for (unsigned i = 0; i < coord_components; i++) {
5100
bld.MOV(sources[length++], offset(coordinate, bld, i));
5102
/* For cube map array, the coordinate is (u,v,r,ai) but there are
5103
* only derivatives for (u, v, r).
5105
if (i < grad_components) {
5106
bld.MOV(sources[length++], offset(lod, bld, i));
5107
bld.MOV(sources[length++], offset(lod2, bld, i));
5111
coordinate_done = true;
5113
case SHADER_OPCODE_TXS:
5114
bld.MOV(retype(sources[length], payload_unsigned_type), lod);
5117
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
5118
/* We need an LOD; just use 0 */
5119
bld.MOV(retype(sources[length], payload_unsigned_type), brw_imm_ud(0));
5122
case SHADER_OPCODE_TXF:
5123
/* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
5124
* On Gfx9 they are u, v, lod, r
5126
bld.MOV(retype(sources[length++], payload_signed_type), coordinate);
5128
if (devinfo->ver >= 9) {
5129
if (coord_components >= 2) {
5130
bld.MOV(retype(sources[length], payload_signed_type),
5131
offset(coordinate, bld, 1));
5133
sources[length] = brw_imm_d(0);
5138
if (devinfo->ver >= 9 && lod.is_zero()) {
5139
op = SHADER_OPCODE_TXF_LZ;
5141
bld.MOV(retype(sources[length], payload_signed_type), lod);
5145
for (unsigned i = devinfo->ver >= 9 ? 2 : 1; i < coord_components; i++)
5146
bld.MOV(retype(sources[length++], payload_signed_type),
5147
offset(coordinate, bld, i));
5149
coordinate_done = true;
5152
case SHADER_OPCODE_TXF_CMS:
5153
case SHADER_OPCODE_TXF_CMS_W:
5154
case SHADER_OPCODE_TXF_UMS:
5155
case SHADER_OPCODE_TXF_MCS:
5156
if (op == SHADER_OPCODE_TXF_UMS ||
5157
op == SHADER_OPCODE_TXF_CMS ||
5158
op == SHADER_OPCODE_TXF_CMS_W) {
5159
bld.MOV(retype(sources[length++], payload_unsigned_type), sample_index);
5162
/* Data from the multisample control surface. */
5163
if (op == SHADER_OPCODE_TXF_CMS || op == SHADER_OPCODE_TXF_CMS_W) {
5164
unsigned num_mcs_components = 1;
5166
/* From the Gfx12HP BSpec: Render Engine - 3D and GPGPU Programs -
5167
* Shared Functions - 3D Sampler - Messages - Message Format:
5169
* ld2dms_w si mcs0 mcs1 mcs2 mcs3 u v r
5171
if (devinfo->verx10 >= 125 && op == SHADER_OPCODE_TXF_CMS_W)
5172
num_mcs_components = 4;
5173
else if (op == SHADER_OPCODE_TXF_CMS_W)
5174
num_mcs_components = 2;
5176
for (unsigned i = 0; i < num_mcs_components; ++i) {
5177
bld.MOV(retype(sources[length++], payload_unsigned_type),
5178
mcs.file == IMM ? mcs : offset(mcs, bld, i));
5182
/* There is no offsetting for this message; just copy in the integer
5183
* texture coordinates.
5185
for (unsigned i = 0; i < coord_components; i++)
5186
bld.MOV(retype(sources[length++], payload_signed_type),
5187
offset(coordinate, bld, i));
5189
coordinate_done = true;
5191
case SHADER_OPCODE_TG4_OFFSET:
5192
/* More crazy intermixing */
5193
for (unsigned i = 0; i < 2; i++) /* u, v */
5194
bld.MOV(sources[length++], offset(coordinate, bld, i));
5196
for (unsigned i = 0; i < 2; i++) /* offu, offv */
5197
bld.MOV(retype(sources[length++], payload_signed_type),
5198
offset(tg4_offset, bld, i));
5200
if (coord_components == 3) /* r if present */
5201
bld.MOV(sources[length++], offset(coordinate, bld, 2));
5203
coordinate_done = true;
5209
/* Set up the coordinate (except for cases where it was done above) */
5210
if (!coordinate_done) {
5211
for (unsigned i = 0; i < coord_components; i++)
5212
bld.MOV(retype(sources[length++], payload_type),
5213
offset(coordinate, bld, i));
5216
if (min_lod.file != BAD_FILE) {
5217
/* Account for all of the missing coordinate sources */
5218
if (op == SHADER_OPCODE_TXD && devinfo->verx10 >= 125) {
5219
/* On DG2 and newer platforms, sample_d can only be used with 1D and
5220
* 2D surfaces, so the maximum number of gradient components is 2.
5221
* In spite of this limitation, the Bspec lists a mysterious R
5222
* component before the min_lod, so the maximum coordinate components
5227
length += 3 - coord_components;
5228
length += (2 - grad_components) * 2;
5230
length += 4 - coord_components;
5231
if (op == SHADER_OPCODE_TXD)
5232
length += (3 - grad_components) * 2;
5235
bld.MOV(sources[length++], min_lod);
5238
const fs_reg src_payload =
5239
fs_reg(VGRF, bld.shader->alloc.allocate(length * reg_width),
5240
BRW_REGISTER_TYPE_F);
5241
/* In case of 16-bit payload each component takes one full register in
5242
* both SIMD8H and SIMD16H modes. In both cases one reg can hold 16
5243
* elements. In SIMD8H case hardware simply expects the components to be
5244
* padded (i.e., aligned on reg boundary).
5246
fs_inst *load_payload_inst =
5247
emit_load_payload_with_padding(bld, src_payload, sources, length,
5248
header_size, REG_SIZE);
5249
unsigned mlen = load_payload_inst->size_written / REG_SIZE;
5250
unsigned simd_mode = 0;
5251
if (payload_type_bit_size == 16) {
5252
assert(devinfo->ver >= 11);
5253
simd_mode = inst->exec_size <= 8 ? GFX10_SAMPLER_SIMD_MODE_SIMD8H :
5254
GFX10_SAMPLER_SIMD_MODE_SIMD16H;
5256
simd_mode = inst->exec_size <= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8 :
5257
BRW_SAMPLER_SIMD_MODE_SIMD16;
5260
/* Generate the SEND. */
5261
inst->opcode = SHADER_OPCODE_SEND;
5263
inst->header_size = header_size;
5265
const unsigned msg_type =
5266
sampler_msg_type(devinfo, op, inst->shadow_compare);
5268
inst->sfid = BRW_SFID_SAMPLER;
5269
if (surface.file == IMM &&
5270
(sampler.file == IMM || sampler_handle.file != BAD_FILE)) {
5271
inst->desc = brw_sampler_desc(devinfo, surface.ud,
5272
sampler.file == IMM ? sampler.ud % 16 : 0,
5275
0 /* return_format unused on gfx7+ */);
5276
inst->src[0] = brw_imm_ud(0);
5277
inst->src[1] = brw_imm_ud(0);
5278
} else if (surface_handle.file != BAD_FILE) {
5279
/* Bindless surface */
5280
assert(devinfo->ver >= 9);
5281
inst->desc = brw_sampler_desc(devinfo,
5283
sampler.file == IMM ? sampler.ud % 16 : 0,
5286
0 /* return_format unused on gfx7+ */);
5288
/* For bindless samplers, the entire address is included in the message
5289
* header so we can leave the portion in the message descriptor 0.
5291
if (sampler_handle.file != BAD_FILE || sampler.file == IMM) {
5292
inst->src[0] = brw_imm_ud(0);
5294
const fs_builder ubld = bld.group(1, 0).exec_all();
5295
fs_reg desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
5296
ubld.SHL(desc, sampler, brw_imm_ud(8));
5297
inst->src[0] = desc;
5300
/* We assume that the driver provided the handle in the top 20 bits so
5301
* we can use the surface handle directly as the extended descriptor.
5303
inst->src[1] = retype(surface_handle, BRW_REGISTER_TYPE_UD);
5305
/* Immediate portion of the descriptor */
5306
inst->desc = brw_sampler_desc(devinfo,
5311
0 /* return_format unused on gfx7+ */);
5312
const fs_builder ubld = bld.group(1, 0).exec_all();
5313
fs_reg desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
5314
if (surface.equals(sampler)) {
5315
/* This case is common in GL */
5316
ubld.MUL(desc, surface, brw_imm_ud(0x101));
5318
if (sampler_handle.file != BAD_FILE) {
5319
ubld.MOV(desc, surface);
5320
} else if (sampler.file == IMM) {
5321
ubld.OR(desc, surface, brw_imm_ud(sampler.ud << 8));
5323
ubld.SHL(desc, sampler, brw_imm_ud(8));
5324
ubld.OR(desc, desc, surface);
5327
ubld.AND(desc, desc, brw_imm_ud(0xfff));
5329
inst->src[0] = component(desc, 0);
5330
inst->src[1] = brw_imm_ud(0); /* ex_desc */
5335
inst->src[2] = src_payload;
5336
inst->resize_sources(3);
5339
/* EOT sampler messages don't make sense to split because it would
5340
* involve ending half of the thread early.
5342
assert(inst->group == 0);
5343
/* We need to use SENDC for EOT sampler messages */
5344
inst->check_tdr = true;
5345
inst->send_has_side_effects = true;
5348
/* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
5349
assert(inst->mlen <= MAX_SAMPLER_MESSAGE_SIZE);
5353
get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo,
5354
opcode op, const fs_reg *src)
5356
unsigned src_type_size = 0;
5358
/* All sources need to have the same size, therefore seek the first valid
5359
* and take the size from there.
5361
for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) {
5362
if (src[i].file != BAD_FILE) {
5363
src_type_size = brw_reg_type_to_size(src[i].type);
5368
assert(src_type_size == 2 || src_type_size == 4);
5371
/* Make sure all sources agree. On gfx12 this doesn't hold when sampling
5372
* compressed multisampled surfaces. There the payload contains MCS data
5373
* which is already in 16-bits unlike the other parameters that need forced
5376
if (devinfo->verx10 < 125 ||
5377
(op != SHADER_OPCODE_TXF_CMS_W &&
5378
op != SHADER_OPCODE_TXF_CMS)) {
5379
for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) {
5380
assert(src[i].file == BAD_FILE ||
5381
brw_reg_type_to_size(src[i].type) == src_type_size);
5386
if (devinfo->verx10 < 125)
5387
return src_type_size * 8;
5389
/* Force conversion from 32-bit sources to 16-bit payload. From the XeHP Bspec:
5390
* 3D and GPGPU Programs - Shared Functions - 3D Sampler - Messages - Message
5391
* Format [GFX12:HAS:1209977870] *
5393
* ld2dms_w SIMD8H and SIMD16H Only
5394
* ld_mcs SIMD8H and SIMD16H Only
5395
* ld2dms REMOVEDBY(GEN:HAS:1406788836)
5398
if (op == SHADER_OPCODE_TXF_CMS_W ||
5399
op == SHADER_OPCODE_TXF_CMS ||
5400
op == SHADER_OPCODE_TXF_UMS ||
5401
op == SHADER_OPCODE_TXF_MCS)
5404
return src_type_size * 8;
5408
lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
5410
const intel_device_info *devinfo = bld.shader->devinfo;
5411
const fs_reg &coordinate = inst->src[TEX_LOGICAL_SRC_COORDINATE];
5412
const fs_reg &shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C];
5413
const fs_reg &lod = inst->src[TEX_LOGICAL_SRC_LOD];
5414
const fs_reg &lod2 = inst->src[TEX_LOGICAL_SRC_LOD2];
5415
const fs_reg &min_lod = inst->src[TEX_LOGICAL_SRC_MIN_LOD];
5416
const fs_reg &sample_index = inst->src[TEX_LOGICAL_SRC_SAMPLE_INDEX];
5417
const fs_reg &mcs = inst->src[TEX_LOGICAL_SRC_MCS];
5418
const fs_reg &surface = inst->src[TEX_LOGICAL_SRC_SURFACE];
5419
const fs_reg &sampler = inst->src[TEX_LOGICAL_SRC_SAMPLER];
5420
const fs_reg &surface_handle = inst->src[TEX_LOGICAL_SRC_SURFACE_HANDLE];
5421
const fs_reg &sampler_handle = inst->src[TEX_LOGICAL_SRC_SAMPLER_HANDLE];
5422
const fs_reg &tg4_offset = inst->src[TEX_LOGICAL_SRC_TG4_OFFSET];
5423
assert(inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM);
5424
const unsigned coord_components = inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].ud;
5425
assert(inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM);
5426
const unsigned grad_components = inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].ud;
5428
if (devinfo->ver >= 7) {
5429
const unsigned msg_payload_type_bit_size =
5430
get_sampler_msg_payload_type_bit_size(devinfo, op, inst->src);
5432
/* 16-bit payloads are available only on gfx11+ */
5433
assert(msg_payload_type_bit_size != 16 || devinfo->ver >= 11);
5435
lower_sampler_logical_send_gfx7(bld, inst, op, coordinate,
5436
shadow_c, lod, lod2, min_lod,
5438
mcs, surface, sampler,
5439
surface_handle, sampler_handle,
5441
msg_payload_type_bit_size,
5442
coord_components, grad_components);
5443
} else if (devinfo->ver >= 5) {
5444
lower_sampler_logical_send_gfx5(bld, inst, op, coordinate,
5445
shadow_c, lod, lod2, sample_index,
5447
coord_components, grad_components);
5449
lower_sampler_logical_send_gfx4(bld, inst, op, coordinate,
5450
shadow_c, lod, lod2,
5452
coord_components, grad_components);
5457
* Predicate the specified instruction on the sample mask.
5460
emit_predicate_on_sample_mask(const fs_builder &bld, fs_inst *inst)
5462
assert(bld.shader->stage == MESA_SHADER_FRAGMENT &&
5463
bld.group() == inst->group &&
5464
bld.dispatch_width() == inst->exec_size);
5466
const fs_visitor *v = static_cast<const fs_visitor *>(bld.shader);
5467
const fs_reg sample_mask = sample_mask_reg(bld);
5468
const unsigned subreg = sample_mask_flag_subreg(v);
5470
if (brw_wm_prog_data(v->stage_prog_data)->uses_kill) {
5471
assert(sample_mask.file == ARF &&
5472
sample_mask.nr == brw_flag_subreg(subreg).nr &&
5473
sample_mask.subnr == brw_flag_subreg(
5474
subreg + inst->group / 16).subnr);
5476
bld.group(1, 0).exec_all()
5477
.MOV(brw_flag_subreg(subreg + inst->group / 16), sample_mask);
5480
if (inst->predicate) {
5481
assert(inst->predicate == BRW_PREDICATE_NORMAL);
5482
assert(!inst->predicate_inverse);
5483
assert(inst->flag_subreg == 0);
5484
/* Combine the sample mask with the existing predicate by using a
5485
* vertical predication mode.
5487
inst->predicate = BRW_PREDICATE_ALIGN1_ALLV;
5489
inst->flag_subreg = subreg;
5490
inst->predicate = BRW_PREDICATE_NORMAL;
5491
inst->predicate_inverse = false;
5496
fs_visitor::emit_is_helper_invocation(fs_reg result)
5498
/* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
5499
* the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
5500
* consideration demoted invocations.
5502
result.type = BRW_REGISTER_TYPE_UD;
5504
bld.MOV(result, brw_imm_ud(0));
5506
/* See sample_mask_reg() for why we split SIMD32 into SIMD16 here. */
5507
unsigned width = bld.dispatch_width();
5508
for (unsigned i = 0; i < DIV_ROUND_UP(width, 16); i++) {
5509
const fs_builder b = bld.group(MIN2(width, 16), i);
5511
fs_inst *mov = b.MOV(offset(result, b, i), brw_imm_ud(~0));
5513
/* The at() ensures that any code emitted to get the predicate happens
5514
* before the mov right above. This is not an issue elsewhere because
5515
* lowering code already set up the builder this way.
5517
emit_predicate_on_sample_mask(b.at(NULL, mov), mov);
5518
mov->predicate_inverse = true;
5523
* Predicate the specified instruction on the vector mask.
5526
emit_predicate_on_vector_mask(const fs_builder &bld, fs_inst *inst)
5528
assert(bld.shader->stage == MESA_SHADER_FRAGMENT &&
5529
bld.group() == inst->group &&
5530
bld.dispatch_width() == inst->exec_size);
5532
const fs_builder ubld = bld.exec_all().group(1, 0);
5534
const fs_visitor *v = static_cast<const fs_visitor *>(bld.shader);
5535
const fs_reg vector_mask = ubld.vgrf(BRW_REGISTER_TYPE_UW);
5536
ubld.emit(SHADER_OPCODE_READ_SR_REG, vector_mask, brw_imm_ud(3));
5537
const unsigned subreg = sample_mask_flag_subreg(v);
5539
ubld.MOV(brw_flag_subreg(subreg + inst->group / 16), vector_mask);
5541
if (inst->predicate) {
5542
assert(inst->predicate == BRW_PREDICATE_NORMAL);
5543
assert(!inst->predicate_inverse);
5544
assert(inst->flag_subreg == 0);
5545
/* Combine the vector mask with the existing predicate by using a
5546
* vertical predication mode.
5548
inst->predicate = BRW_PREDICATE_ALIGN1_ALLV;
5550
inst->flag_subreg = subreg;
5551
inst->predicate = BRW_PREDICATE_NORMAL;
5552
inst->predicate_inverse = false;
5557
setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc,
5558
const fs_reg &surface, const fs_reg &surface_handle)
5560
const ASSERTED intel_device_info *devinfo = bld.shader->devinfo;
5562
/* We must have exactly one of surface and surface_handle */
5563
assert((surface.file == BAD_FILE) != (surface_handle.file == BAD_FILE));
5565
if (surface.file == IMM) {
5566
inst->desc = desc | (surface.ud & 0xff);
5567
inst->src[0] = brw_imm_ud(0);
5568
inst->src[1] = brw_imm_ud(0); /* ex_desc */
5569
} else if (surface_handle.file != BAD_FILE) {
5570
/* Bindless surface */
5571
assert(devinfo->ver >= 9);
5572
inst->desc = desc | GFX9_BTI_BINDLESS;
5573
inst->src[0] = brw_imm_ud(0);
5575
/* We assume that the driver provided the handle in the top 20 bits so
5576
* we can use the surface handle directly as the extended descriptor.
5578
inst->src[1] = retype(surface_handle, BRW_REGISTER_TYPE_UD);
5581
const fs_builder ubld = bld.exec_all().group(1, 0);
5582
fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD);
5583
ubld.AND(tmp, surface, brw_imm_ud(0xff));
5584
inst->src[0] = component(tmp, 0);
5585
inst->src[1] = brw_imm_ud(0); /* ex_desc */
5590
lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
5592
const intel_device_info *devinfo = bld.shader->devinfo;
5594
/* Get the logical send arguments. */
5595
const fs_reg &addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS];
5596
const fs_reg &src = inst->src[SURFACE_LOGICAL_SRC_DATA];
5597
const fs_reg &surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE];
5598
const fs_reg &surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE];
5599
const UNUSED fs_reg &dims = inst->src[SURFACE_LOGICAL_SRC_IMM_DIMS];
5600
const fs_reg &arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG];
5601
const fs_reg &allow_sample_mask =
5602
inst->src[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK];
5603
assert(arg.file == IMM);
5604
assert(allow_sample_mask.file == IMM);
5606
/* Calculate the total number of components of the payload. */
5607
const unsigned addr_sz = inst->components_read(SURFACE_LOGICAL_SRC_ADDRESS);
5608
const unsigned src_sz = inst->components_read(SURFACE_LOGICAL_SRC_DATA);
5610
const bool is_typed_access =
5611
inst->opcode == SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL ||
5612
inst->opcode == SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL ||
5613
inst->opcode == SHADER_OPCODE_TYPED_ATOMIC_LOGICAL;
5615
const bool is_surface_access = is_typed_access ||
5616
inst->opcode == SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL ||
5617
inst->opcode == SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL ||
5618
inst->opcode == SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL;
5620
const bool is_stateless =
5621
surface.file == IMM && (surface.ud == BRW_BTI_STATELESS ||
5622
surface.ud == GFX8_BTI_STATELESS_NON_COHERENT);
5624
const bool has_side_effects = inst->has_side_effects();
5626
fs_reg sample_mask = allow_sample_mask.ud ? sample_mask_reg(bld) :
5627
fs_reg(brw_imm_d(0xffff));
5629
/* From the BDW PRM Volume 7, page 147:
5631
* "For the Data Cache Data Port*, the header must be present for the
5632
* following message types: [...] Typed read/write/atomics"
5634
* Earlier generations have a similar wording. Because of this restriction
5635
* we don't attempt to implement sample masks via predication for such
5636
* messages prior to Gfx9, since we have to provide a header anyway. On
5637
* Gfx11+ the header has been removed so we can only use predication.
5639
* For all stateless A32 messages, we also need a header
5642
if ((devinfo->ver < 9 && is_typed_access) || is_stateless) {
5643
fs_builder ubld = bld.exec_all().group(8, 0);
5644
header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
5646
assert(!is_surface_access);
5647
ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, header);
5649
ubld.MOV(header, brw_imm_d(0));
5650
if (is_surface_access)
5651
ubld.group(1, 0).MOV(component(header, 7), sample_mask);
5654
const unsigned header_sz = header.file != BAD_FILE ? 1 : 0;
5656
fs_reg payload, payload2;
5657
unsigned mlen, ex_mlen = 0;
5658
if (devinfo->ver >= 9 &&
5659
(src.file == BAD_FILE || header.file == BAD_FILE)) {
5660
/* We have split sends on gfx9 and above */
5661
if (header.file == BAD_FILE) {
5662
payload = bld.move_to_vgrf(addr, addr_sz);
5663
payload2 = bld.move_to_vgrf(src, src_sz);
5664
mlen = addr_sz * (inst->exec_size / 8);
5665
ex_mlen = src_sz * (inst->exec_size / 8);
5667
assert(src.file == BAD_FILE);
5669
payload2 = bld.move_to_vgrf(addr, addr_sz);
5671
ex_mlen = addr_sz * (inst->exec_size / 8);
5674
/* Allocate space for the payload. */
5675
const unsigned sz = header_sz + addr_sz + src_sz;
5676
payload = bld.vgrf(BRW_REGISTER_TYPE_UD, sz);
5677
fs_reg *const components = new fs_reg[sz];
5680
/* Construct the payload. */
5681
if (header.file != BAD_FILE)
5682
components[n++] = header;
5684
for (unsigned i = 0; i < addr_sz; i++)
5685
components[n++] = offset(addr, bld, i);
5687
for (unsigned i = 0; i < src_sz; i++)
5688
components[n++] = offset(src, bld, i);
5690
bld.LOAD_PAYLOAD(payload, components, sz, header_sz);
5691
mlen = header_sz + (addr_sz + src_sz) * inst->exec_size / 8;
5693
delete[] components;
5696
/* Predicate the instruction on the sample mask if no header is
5699
if ((header.file == BAD_FILE || !is_surface_access) &&
5700
sample_mask.file != BAD_FILE && sample_mask.file != IMM)
5701
emit_predicate_on_sample_mask(bld, inst);
5704
switch (inst->opcode) {
5705
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
5706
case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
5707
/* Byte scattered opcodes go through the normal data cache */
5708
sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
5711
case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
5712
case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
5713
sfid = devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
5714
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
5715
BRW_DATAPORT_READ_TARGET_RENDER_CACHE;
5718
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
5719
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
5720
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
5721
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
5722
/* Untyped Surface messages go through the data cache but the SFID value
5723
* changed on Haswell.
5725
sfid = (devinfo->verx10 >= 75 ?
5726
HSW_SFID_DATAPORT_DATA_CACHE_1 :
5727
GFX7_SFID_DATAPORT_DATA_CACHE);
5730
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
5731
case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
5732
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
5733
/* Typed surface messages go through the render cache on IVB and the
5734
* data cache on HSW+.
5736
sfid = (devinfo->verx10 >= 75 ?
5737
HSW_SFID_DATAPORT_DATA_CACHE_1 :
5738
GFX6_SFID_DATAPORT_RENDER_CACHE);
5742
unreachable("Unsupported surface opcode");
5746
switch (inst->opcode) {
5747
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
5748
desc = brw_dp_untyped_surface_rw_desc(devinfo, inst->exec_size,
5749
arg.ud, /* num_channels */
5753
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
5754
desc = brw_dp_untyped_surface_rw_desc(devinfo, inst->exec_size,
5755
arg.ud, /* num_channels */
5759
case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
5760
desc = brw_dp_byte_scattered_rw_desc(devinfo, inst->exec_size,
5761
arg.ud, /* bit_size */
5765
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
5766
desc = brw_dp_byte_scattered_rw_desc(devinfo, inst->exec_size,
5767
arg.ud, /* bit_size */
5771
case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
5772
assert(arg.ud == 32); /* bit_size */
5773
desc = brw_dp_dword_scattered_rw_desc(devinfo, inst->exec_size,
5777
case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
5778
assert(arg.ud == 32); /* bit_size */
5779
desc = brw_dp_dword_scattered_rw_desc(devinfo, inst->exec_size,
5783
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
5784
desc = brw_dp_untyped_atomic_desc(devinfo, inst->exec_size,
5785
arg.ud, /* atomic_op */
5786
!inst->dst.is_null());
5789
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
5790
desc = brw_dp_untyped_atomic_float_desc(devinfo, inst->exec_size,
5791
arg.ud, /* atomic_op */
5792
!inst->dst.is_null());
5795
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
5796
desc = brw_dp_typed_surface_rw_desc(devinfo, inst->exec_size, inst->group,
5797
arg.ud, /* num_channels */
5801
case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
5802
desc = brw_dp_typed_surface_rw_desc(devinfo, inst->exec_size, inst->group,
5803
arg.ud, /* num_channels */
5807
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
5808
desc = brw_dp_typed_atomic_desc(devinfo, inst->exec_size, inst->group,
5809
arg.ud, /* atomic_op */
5810
!inst->dst.is_null());
5814
unreachable("Unknown surface logical instruction");
5817
/* Update the original instruction. */
5818
inst->opcode = SHADER_OPCODE_SEND;
5820
inst->ex_mlen = ex_mlen;
5821
inst->header_size = header_sz;
5822
inst->send_has_side_effects = has_side_effects;
5823
inst->send_is_volatile = !has_side_effects;
5825
/* Set up SFID and descriptors */
5827
setup_surface_descriptors(bld, inst, desc, surface, surface_handle);
5829
inst->resize_sources(4);
5831
/* Finally, the payload */
5832
inst->src[2] = payload;
5833
inst->src[3] = payload2;
5836
static enum lsc_opcode
5837
brw_atomic_op_to_lsc_atomic_op(unsigned op)
5841
return LSC_OP_ATOMIC_AND;
5843
return LSC_OP_ATOMIC_OR;
5845
return LSC_OP_ATOMIC_XOR;
5847
return LSC_OP_ATOMIC_STORE;
5849
return LSC_OP_ATOMIC_INC;
5851
return LSC_OP_ATOMIC_DEC;
5853
return LSC_OP_ATOMIC_ADD;
5855
return LSC_OP_ATOMIC_SUB;
5857
return LSC_OP_ATOMIC_MAX;
5859
return LSC_OP_ATOMIC_MIN;
5861
return LSC_OP_ATOMIC_UMAX;
5863
return LSC_OP_ATOMIC_UMIN;
5865
return LSC_OP_ATOMIC_CMPXCHG;
5868
unreachable("invalid atomic opcode");
5872
static enum lsc_opcode
5873
brw_atomic_op_to_lsc_fatomic_op(uint32_t aop)
5877
return LSC_OP_ATOMIC_FMAX;
5879
return LSC_OP_ATOMIC_FMIN;
5880
case BRW_AOP_FCMPWR:
5881
return LSC_OP_ATOMIC_FCMPXCHG;
5883
return LSC_OP_ATOMIC_FADD;
5885
unreachable("Unsupported float atomic opcode");
5889
static enum lsc_data_size
5890
lsc_bits_to_data_size(unsigned bit_size)
5892
switch (bit_size / 8) {
5893
case 1: return LSC_DATA_SIZE_D8U32;
5894
case 2: return LSC_DATA_SIZE_D16U32;
5895
case 4: return LSC_DATA_SIZE_D32;
5896
case 8: return LSC_DATA_SIZE_D64;
5898
unreachable("Unsupported data size.");
5903
lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst)
5905
const intel_device_info *devinfo = bld.shader->devinfo;
5906
assert(devinfo->has_lsc);
5908
/* Get the logical send arguments. */
5909
const fs_reg addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS];
5910
const fs_reg src = inst->src[SURFACE_LOGICAL_SRC_DATA];
5911
const fs_reg surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE];
5912
const fs_reg surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE];
5913
const UNUSED fs_reg &dims = inst->src[SURFACE_LOGICAL_SRC_IMM_DIMS];
5914
const fs_reg arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG];
5915
const fs_reg allow_sample_mask =
5916
inst->src[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK];
5917
assert(arg.file == IMM);
5918
assert(allow_sample_mask.file == IMM);
5920
/* Calculate the total number of components of the payload. */
5921
const unsigned addr_sz = inst->components_read(SURFACE_LOGICAL_SRC_ADDRESS);
5922
const unsigned src_comps = inst->components_read(SURFACE_LOGICAL_SRC_DATA);
5923
const unsigned src_sz = type_sz(src.type);
5925
const bool has_side_effects = inst->has_side_effects();
5927
unsigned ex_mlen = 0;
5928
fs_reg payload, payload2;
5929
payload = bld.move_to_vgrf(addr, addr_sz);
5930
if (src.file != BAD_FILE) {
5931
payload2 = bld.move_to_vgrf(src, src_comps);
5932
ex_mlen = (src_comps * src_sz * inst->exec_size) / REG_SIZE;
5935
/* Predicate the instruction on the sample mask if needed */
5936
fs_reg sample_mask = allow_sample_mask.ud ? sample_mask_reg(bld) :
5937
fs_reg(brw_imm_d(0xffff));
5938
if (sample_mask.file != BAD_FILE && sample_mask.file != IMM)
5939
emit_predicate_on_sample_mask(bld, inst);
5941
if (surface.file == IMM && surface.ud == GFX7_BTI_SLM)
5942
inst->sfid = GFX12_SFID_SLM;
5944
inst->sfid = GFX12_SFID_UGM;
5946
/* We must have exactly one of surface and surface_handle */
5947
assert((surface.file == BAD_FILE) != (surface_handle.file == BAD_FILE));
5949
enum lsc_addr_surface_type surf_type;
5950
if (surface_handle.file != BAD_FILE)
5951
surf_type = LSC_ADDR_SURFTYPE_BSS;
5952
else if (surface.file == IMM && surface.ud == GFX7_BTI_SLM)
5953
surf_type = LSC_ADDR_SURFTYPE_FLAT;
5955
surf_type = LSC_ADDR_SURFTYPE_BTI;
5957
switch (inst->opcode) {
5958
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
5959
inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD_CMASK, inst->exec_size,
5960
surf_type, LSC_ADDR_SIZE_A32,
5961
1 /* num_coordinates */,
5962
LSC_DATA_SIZE_D32, arg.ud /* num_channels */,
5963
false /* transpose */,
5964
LSC_CACHE_LOAD_L1STATE_L3MOCS,
5965
true /* has_dest */);
5967
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
5968
inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE_CMASK, inst->exec_size,
5969
surf_type, LSC_ADDR_SIZE_A32,
5970
1 /* num_coordinates */,
5971
LSC_DATA_SIZE_D32, arg.ud /* num_channels */,
5972
false /* transpose */,
5973
LSC_CACHE_STORE_L1STATE_L3MOCS,
5974
false /* has_dest */);
5976
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
5977
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: {
5978
/* Bspec: Atomic instruction -> Cache section:
5980
* Atomic messages are always forced to "un-cacheable" in the L1
5983
enum lsc_opcode opcode =
5984
inst->opcode == SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL ?
5985
brw_atomic_op_to_lsc_fatomic_op(arg.ud) :
5986
brw_atomic_op_to_lsc_atomic_op(arg.ud);
5987
inst->desc = lsc_msg_desc(devinfo, opcode, inst->exec_size,
5988
surf_type, LSC_ADDR_SIZE_A32,
5989
1 /* num_coordinates */,
5990
lsc_bits_to_data_size(src_sz * 8),
5991
1 /* num_channels */,
5992
false /* transpose */,
5993
LSC_CACHE_STORE_L1UC_L3WB,
5994
!inst->dst.is_null());
5997
case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
5998
inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, inst->exec_size,
5999
surf_type, LSC_ADDR_SIZE_A32,
6000
1 /* num_coordinates */,
6001
lsc_bits_to_data_size(arg.ud),
6002
1 /* num_channels */,
6003
false /* transpose */,
6004
LSC_CACHE_LOAD_L1STATE_L3MOCS,
6005
true /* has_dest */);
6007
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
6008
inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE, inst->exec_size,
6009
surf_type, LSC_ADDR_SIZE_A32,
6010
1 /* num_coordinates */,
6011
lsc_bits_to_data_size(arg.ud),
6012
1 /* num_channels */,
6013
false /* transpose */,
6014
LSC_CACHE_STORE_L1STATE_L3MOCS,
6015
false /* has_dest */);
6018
unreachable("Unknown surface logical instruction");
6021
inst->src[0] = brw_imm_ud(0);
6023
/* Set up extended descriptors */
6024
switch (surf_type) {
6025
case LSC_ADDR_SURFTYPE_FLAT:
6026
inst->src[1] = brw_imm_ud(0);
6028
case LSC_ADDR_SURFTYPE_BSS:
6029
/* We assume that the driver provided the handle in the top 20 bits so
6030
* we can use the surface handle directly as the extended descriptor.
6032
inst->src[1] = retype(surface_handle, BRW_REGISTER_TYPE_UD);
6034
case LSC_ADDR_SURFTYPE_BTI:
6035
if (surface.file == IMM) {
6036
inst->src[1] = brw_imm_ud(lsc_bti_ex_desc(devinfo, surface.ud));
6038
const fs_builder ubld = bld.exec_all().group(1, 0);
6039
fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD);
6040
ubld.SHL(tmp, surface, brw_imm_ud(24));
6041
inst->src[1] = component(tmp, 0);
6045
unreachable("Unknown surface type");
6048
/* Update the original instruction. */
6049
inst->opcode = SHADER_OPCODE_SEND;
6050
inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
6051
inst->ex_mlen = ex_mlen;
6052
inst->header_size = 0;
6053
inst->send_has_side_effects = has_side_effects;
6054
inst->send_is_volatile = !has_side_effects;
6056
inst->resize_sources(4);
6058
/* Finally, the payload */
6059
inst->src[2] = payload;
6060
inst->src[3] = payload2;
6064
lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst)
6066
const intel_device_info *devinfo = bld.shader->devinfo;
6067
assert(devinfo->ver >= 9);
6069
/* Get the logical send arguments. */
6070
const fs_reg &addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS];
6071
const fs_reg &src = inst->src[SURFACE_LOGICAL_SRC_DATA];
6072
const fs_reg &surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE];
6073
const fs_reg &surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE];
6074
const fs_reg &arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG];
6075
assert(arg.file == IMM);
6076
assert(inst->src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == BAD_FILE);
6077
assert(inst->src[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK].file == BAD_FILE);
6079
const bool is_stateless =
6080
surface.file == IMM && (surface.ud == BRW_BTI_STATELESS ||
6081
surface.ud == GFX8_BTI_STATELESS_NON_COHERENT);
6083
const bool has_side_effects = inst->has_side_effects();
6085
const bool align_16B =
6086
inst->opcode != SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL;
6088
const bool write = inst->opcode == SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL;
6090
/* The address is stored in the header. See MH_A32_GO and MH_BTS_GO. */
6091
fs_builder ubld = bld.exec_all().group(8, 0);
6092
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
6095
ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, header);
6097
ubld.MOV(header, brw_imm_d(0));
6099
/* Address in OWord units when aligned to OWords. */
6101
ubld.group(1, 0).SHR(component(header, 2), addr, brw_imm_ud(4));
6103
ubld.group(1, 0).MOV(component(header, 2), addr);
6106
unsigned ex_mlen = 0;
6108
const unsigned src_sz = inst->components_read(SURFACE_LOGICAL_SRC_DATA);
6109
data = retype(bld.move_to_vgrf(src, src_sz), BRW_REGISTER_TYPE_UD);
6110
ex_mlen = src_sz * type_sz(src.type) * inst->exec_size / REG_SIZE;
6113
inst->opcode = SHADER_OPCODE_SEND;
6115
inst->ex_mlen = ex_mlen;
6116
inst->header_size = 1;
6117
inst->send_has_side_effects = has_side_effects;
6118
inst->send_is_volatile = !has_side_effects;
6120
inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
6122
const uint32_t desc = brw_dp_oword_block_rw_desc(devinfo, align_16B,
6124
setup_surface_descriptors(bld, inst, desc, surface, surface_handle);
6126
inst->resize_sources(4);
6128
inst->src[2] = header;
6129
inst->src[3] = data;
6133
emit_a64_oword_block_header(const fs_builder &bld, const fs_reg &addr)
6135
const fs_builder ubld = bld.exec_all().group(8, 0);
6136
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
6137
ubld.MOV(header, brw_imm_ud(0));
6139
/* Use a 2-wide MOV to fill out the address */
6140
assert(type_sz(addr.type) == 8 && addr.stride == 0);
6141
fs_reg addr_vec2 = addr;
6142
addr_vec2.type = BRW_REGISTER_TYPE_UD;
6143
addr_vec2.stride = 1;
6144
ubld.group(2, 0).MOV(header, addr_vec2);
6150
emit_fragment_mask(const fs_builder &bld, fs_inst *inst)
6152
assert(inst->src[A64_LOGICAL_ENABLE_HELPERS].file == IMM);
6153
const bool enable_helpers = inst->src[A64_LOGICAL_ENABLE_HELPERS].ud;
6155
/* If we're a fragment shader, we have to predicate with the sample mask to
6156
* avoid helper invocations to avoid helper invocations in instructions
6157
* with side effects, unless they are explicitly required.
6159
* There are also special cases when we actually want to run on helpers
6162
assert(bld.shader->stage == MESA_SHADER_FRAGMENT);
6164
emit_predicate_on_vector_mask(bld, inst);
6165
else if (inst->has_side_effects())
6166
emit_predicate_on_sample_mask(bld, inst);
6170
lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst)
6172
const intel_device_info *devinfo = bld.shader->devinfo;
6174
/* Get the logical send arguments. */
6175
const fs_reg &addr = inst->src[A64_LOGICAL_ADDRESS];
6176
const fs_reg &src = inst->src[A64_LOGICAL_SRC];
6177
const unsigned src_sz = type_sz(src.type);
6179
const unsigned src_comps = inst->components_read(1);
6180
assert(inst->src[A64_LOGICAL_ARG].file == IMM);
6181
const unsigned arg = inst->src[A64_LOGICAL_ARG].ud;
6182
const bool has_side_effects = inst->has_side_effects();
6184
fs_reg payload = retype(bld.move_to_vgrf(addr, 1), BRW_REGISTER_TYPE_UD);
6185
fs_reg payload2 = retype(bld.move_to_vgrf(src, src_comps),
6186
BRW_REGISTER_TYPE_UD);
6187
unsigned ex_mlen = src_comps * src_sz * inst->exec_size / REG_SIZE;
6189
switch (inst->opcode) {
6190
case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
6191
inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD_CMASK, inst->exec_size,
6192
LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A64,
6193
1 /* num_coordinates */,
6194
LSC_DATA_SIZE_D32, arg /* num_channels */,
6195
false /* transpose */,
6196
LSC_CACHE_LOAD_L1STATE_L3MOCS,
6197
true /* has_dest */);
6199
case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
6200
inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE_CMASK, inst->exec_size,
6201
LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A64,
6202
1 /* num_coordinates */,
6203
LSC_DATA_SIZE_D32, arg /* num_channels */,
6204
false /* transpose */,
6205
LSC_CACHE_STORE_L1STATE_L3MOCS,
6206
false /* has_dest */);
6208
case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
6209
inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, inst->exec_size,
6210
LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A64,
6211
1 /* num_coordinates */,
6212
lsc_bits_to_data_size(arg),
6213
1 /* num_channels */,
6214
false /* transpose */,
6215
LSC_CACHE_LOAD_L1STATE_L3MOCS,
6216
true /* has_dest */);
6218
case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
6219
inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE, inst->exec_size,
6220
LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A64,
6221
1 /* num_coordinates */,
6222
lsc_bits_to_data_size(arg),
6223
1 /* num_channels */,
6224
false /* transpose */,
6225
LSC_CACHE_STORE_L1STATE_L3MOCS,
6226
false /* has_dest */);
6228
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
6229
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL:
6230
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: {
6231
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
6232
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
6233
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
6234
/* Bspec: Atomic instruction -> Cache section:
6236
* Atomic messages are always forced to "un-cacheable" in the L1
6239
enum lsc_opcode opcode =
6240
(inst->opcode == SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL ||
6241
inst->opcode == SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL ||
6242
inst->opcode == SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL) ?
6243
brw_atomic_op_to_lsc_atomic_op(arg) :
6244
brw_atomic_op_to_lsc_fatomic_op(arg);
6245
inst->desc = lsc_msg_desc(devinfo, opcode, inst->exec_size,
6246
LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A64,
6247
1 /* num_coordinates */,
6248
lsc_bits_to_data_size(src_sz * 8),
6249
1 /* num_channels */,
6250
false /* transpose */,
6251
LSC_CACHE_STORE_L1UC_L3WB,
6252
!inst->dst.is_null());
6256
unreachable("Unknown A64 logical instruction");
6259
if (bld.shader->stage == MESA_SHADER_FRAGMENT)
6260
emit_fragment_mask(bld, inst);
6262
/* Update the original instruction. */
6263
inst->opcode = SHADER_OPCODE_SEND;
6264
inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
6265
inst->ex_mlen = ex_mlen;
6266
inst->header_size = 0;
6267
inst->send_has_side_effects = has_side_effects;
6268
inst->send_is_volatile = !has_side_effects;
6270
/* Set up SFID and descriptors */
6271
inst->sfid = GFX12_SFID_UGM;
6272
inst->resize_sources(4);
6273
inst->src[0] = brw_imm_ud(0); /* desc */
6274
inst->src[1] = brw_imm_ud(0); /* ex_desc */
6275
inst->src[2] = payload;
6276
inst->src[3] = payload2;
6280
lower_a64_logical_send(const fs_builder &bld, fs_inst *inst)
6282
const intel_device_info *devinfo = bld.shader->devinfo;
6284
const fs_reg &addr = inst->src[A64_LOGICAL_ADDRESS];
6285
const fs_reg &src = inst->src[A64_LOGICAL_SRC];
6286
const unsigned src_comps = inst->components_read(1);
6287
assert(inst->src[A64_LOGICAL_ARG].file == IMM);
6288
const unsigned arg = inst->src[A64_LOGICAL_ARG].ud;
6289
const bool has_side_effects = inst->has_side_effects();
6291
fs_reg payload, payload2;
6292
unsigned mlen, ex_mlen = 0, header_size = 0;
6293
if (inst->opcode == SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL ||
6294
inst->opcode == SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL ||
6295
inst->opcode == SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL) {
6296
assert(devinfo->ver >= 9);
6298
/* OWORD messages only take a scalar address in a header */
6301
payload = emit_a64_oword_block_header(bld, addr);
6303
if (inst->opcode == SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL) {
6304
ex_mlen = src_comps * type_sz(src.type) * inst->exec_size / REG_SIZE;
6305
payload2 = retype(bld.move_to_vgrf(src, src_comps),
6306
BRW_REGISTER_TYPE_UD);
6308
} else if (devinfo->ver >= 9) {
6309
/* On Skylake and above, we have SENDS */
6310
mlen = 2 * (inst->exec_size / 8);
6311
ex_mlen = src_comps * type_sz(src.type) * inst->exec_size / REG_SIZE;
6312
payload = retype(bld.move_to_vgrf(addr, 1), BRW_REGISTER_TYPE_UD);
6313
payload2 = retype(bld.move_to_vgrf(src, src_comps),
6314
BRW_REGISTER_TYPE_UD);
6316
/* Add two because the address is 64-bit */
6317
const unsigned dwords = 2 + src_comps;
6318
mlen = dwords * (inst->exec_size / 8);
6324
for (unsigned i = 0; i < src_comps; i++)
6325
sources[1 + i] = offset(src, bld, i);
6327
payload = bld.vgrf(BRW_REGISTER_TYPE_UD, dwords);
6328
bld.LOAD_PAYLOAD(payload, sources, 1 + src_comps, 0);
6332
switch (inst->opcode) {
6333
case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
6334
desc = brw_dp_a64_untyped_surface_rw_desc(devinfo, inst->exec_size,
6335
arg, /* num_channels */
6339
case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
6340
desc = brw_dp_a64_untyped_surface_rw_desc(devinfo, inst->exec_size,
6341
arg, /* num_channels */
6345
case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL:
6346
desc = brw_dp_a64_oword_block_rw_desc(devinfo,
6347
true, /* align_16B */
6348
arg, /* num_dwords */
6352
case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
6353
desc = brw_dp_a64_oword_block_rw_desc(devinfo,
6354
false, /* align_16B */
6355
arg, /* num_dwords */
6359
case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL:
6360
desc = brw_dp_a64_oword_block_rw_desc(devinfo,
6361
true, /* align_16B */
6362
arg, /* num_dwords */
6366
case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
6367
desc = brw_dp_a64_byte_scattered_rw_desc(devinfo, inst->exec_size,
6372
case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
6373
desc = brw_dp_a64_byte_scattered_rw_desc(devinfo, inst->exec_size,
6378
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
6379
desc = brw_dp_a64_untyped_atomic_desc(devinfo, inst->exec_size, 32,
6380
arg, /* atomic_op */
6381
!inst->dst.is_null());
6384
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL:
6385
desc = brw_dp_a64_untyped_atomic_desc(devinfo, inst->exec_size, 16,
6386
arg, /* atomic_op */
6387
!inst->dst.is_null());
6390
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
6391
desc = brw_dp_a64_untyped_atomic_desc(devinfo, inst->exec_size, 64,
6392
arg, /* atomic_op */
6393
!inst->dst.is_null());
6396
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
6397
desc = brw_dp_a64_untyped_atomic_float_desc(devinfo, inst->exec_size,
6399
arg, /* atomic_op */
6400
!inst->dst.is_null());
6403
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
6404
desc = brw_dp_a64_untyped_atomic_float_desc(devinfo, inst->exec_size,
6406
arg, /* atomic_op */
6407
!inst->dst.is_null());
6411
unreachable("Unknown A64 logical instruction");
6414
if (bld.shader->stage == MESA_SHADER_FRAGMENT)
6415
emit_fragment_mask(bld, inst);
6417
/* Update the original instruction. */
6418
inst->opcode = SHADER_OPCODE_SEND;
6420
inst->ex_mlen = ex_mlen;
6421
inst->header_size = header_size;
6422
inst->send_has_side_effects = has_side_effects;
6423
inst->send_is_volatile = !has_side_effects;
6425
/* Set up SFID and descriptors */
6426
inst->sfid = HSW_SFID_DATAPORT_DATA_CACHE_1;
6428
inst->resize_sources(4);
6429
inst->src[0] = brw_imm_ud(0); /* desc */
6430
inst->src[1] = brw_imm_ud(0); /* ex_desc */
6431
inst->src[2] = payload;
6432
inst->src[3] = payload2;
6436
lower_lsc_varying_pull_constant_logical_send(const fs_builder &bld,
6439
const intel_device_info *devinfo = bld.shader->devinfo;
6440
ASSERTED const brw_compiler *compiler = bld.shader->compiler;
6442
fs_reg index = inst->src[0];
6444
/* We are switching the instruction from an ALU-like instruction to a
6445
* send-from-grf instruction. Since sends can't handle strides or
6446
* source modifiers, we have to make a copy of the offset source.
6448
fs_reg ubo_offset = bld.move_to_vgrf(inst->src[1], 1);
6450
assert(inst->src[2].file == BRW_IMMEDIATE_VALUE);
6451
unsigned alignment = inst->src[2].ud;
6453
inst->opcode = SHADER_OPCODE_SEND;
6454
inst->sfid = GFX12_SFID_UGM;
6455
inst->resize_sources(3);
6456
inst->src[0] = brw_imm_ud(0);
6458
if (index.file == IMM) {
6459
inst->src[1] = brw_imm_ud(lsc_bti_ex_desc(devinfo, index.ud));
6461
const fs_builder ubld = bld.exec_all().group(1, 0);
6462
fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD);
6463
ubld.SHL(tmp, index, brw_imm_ud(24));
6464
inst->src[1] = component(tmp, 0);
6467
assert(!compiler->indirect_ubos_use_sampler);
6469
inst->src[2] = ubo_offset; /* payload */
6470
if (alignment >= 4) {
6471
inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD_CMASK, inst->exec_size,
6472
LSC_ADDR_SURFTYPE_BTI, LSC_ADDR_SIZE_A32,
6473
1 /* num_coordinates */,
6475
4 /* num_channels */,
6476
false /* transpose */,
6477
LSC_CACHE_LOAD_L1STATE_L3MOCS,
6478
true /* has_dest */);
6479
inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
6481
inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, inst->exec_size,
6482
LSC_ADDR_SURFTYPE_BTI, LSC_ADDR_SIZE_A32,
6483
1 /* num_coordinates */,
6485
1 /* num_channels */,
6486
false /* transpose */,
6487
LSC_CACHE_LOAD_L1STATE_L3MOCS,
6488
true /* has_dest */);
6489
inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
6490
/* The byte scattered messages can only read one dword at a time so
6491
* we have to duplicate the message 4 times to read the full vec4.
6492
* Hopefully, dead code will clean up the mess if some of them aren't
6495
assert(inst->size_written == 16 * inst->exec_size);
6496
inst->size_written /= 4;
6497
for (unsigned c = 1; c < 4; c++) {
6498
/* Emit a copy of the instruction because we're about to modify
6499
* it. Because this loop starts at 1, we will emit copies for the
6500
* first 3 and the final one will be the modified instruction.
6504
/* Offset the source */
6505
inst->src[2] = bld.vgrf(BRW_REGISTER_TYPE_UD);
6506
bld.ADD(inst->src[2], ubo_offset, brw_imm_ud(c * 4));
6508
/* Offset the destination */
6509
inst->dst = offset(inst->dst, bld, 1);
6515
lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
6517
const intel_device_info *devinfo = bld.shader->devinfo;
6518
const brw_compiler *compiler = bld.shader->compiler;
6520
if (devinfo->ver >= 7) {
6521
fs_reg index = inst->src[0];
6522
/* We are switching the instruction from an ALU-like instruction to a
6523
* send-from-grf instruction. Since sends can't handle strides or
6524
* source modifiers, we have to make a copy of the offset source.
6526
fs_reg ubo_offset = bld.vgrf(BRW_REGISTER_TYPE_UD);
6527
bld.MOV(ubo_offset, inst->src[1]);
6529
assert(inst->src[2].file == BRW_IMMEDIATE_VALUE);
6530
unsigned alignment = inst->src[2].ud;
6532
inst->opcode = SHADER_OPCODE_SEND;
6533
inst->mlen = inst->exec_size / 8;
6534
inst->resize_sources(3);
6536
if (index.file == IMM) {
6537
inst->desc = index.ud & 0xff;
6538
inst->src[0] = brw_imm_ud(0);
6541
const fs_builder ubld = bld.exec_all().group(1, 0);
6542
fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD);
6543
ubld.AND(tmp, index, brw_imm_ud(0xff));
6544
inst->src[0] = component(tmp, 0);
6546
inst->src[1] = brw_imm_ud(0); /* ex_desc */
6547
inst->src[2] = ubo_offset; /* payload */
6549
if (compiler->indirect_ubos_use_sampler) {
6550
const unsigned simd_mode =
6551
inst->exec_size <= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8 :
6552
BRW_SAMPLER_SIMD_MODE_SIMD16;
6554
inst->sfid = BRW_SFID_SAMPLER;
6555
inst->desc |= brw_sampler_desc(devinfo, 0, 0,
6556
GFX5_SAMPLER_MESSAGE_SAMPLE_LD,
6558
} else if (alignment >= 4) {
6559
inst->sfid = (devinfo->verx10 >= 75 ?
6560
HSW_SFID_DATAPORT_DATA_CACHE_1 :
6561
GFX7_SFID_DATAPORT_DATA_CACHE);
6562
inst->desc |= brw_dp_untyped_surface_rw_desc(devinfo, inst->exec_size,
6563
4, /* num_channels */
6566
inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
6567
inst->desc |= brw_dp_byte_scattered_rw_desc(devinfo, inst->exec_size,
6570
/* The byte scattered messages can only read one dword at a time so
6571
* we have to duplicate the message 4 times to read the full vec4.
6572
* Hopefully, dead code will clean up the mess if some of them aren't
6575
assert(inst->size_written == 16 * inst->exec_size);
6576
inst->size_written /= 4;
6577
for (unsigned c = 1; c < 4; c++) {
6578
/* Emit a copy of the instruction because we're about to modify
6579
* it. Because this loop starts at 1, we will emit copies for the
6580
* first 3 and the final one will be the modified instruction.
6584
/* Offset the source */
6585
inst->src[2] = bld.vgrf(BRW_REGISTER_TYPE_UD);
6586
bld.ADD(inst->src[2], ubo_offset, brw_imm_ud(c * 4));
6588
/* Offset the destination */
6589
inst->dst = offset(inst->dst, bld, 1);
6593
const fs_reg payload(MRF, FIRST_PULL_LOAD_MRF(devinfo->ver),
6594
BRW_REGISTER_TYPE_UD);
6596
bld.MOV(byte_offset(payload, REG_SIZE), inst->src[1]);
6598
inst->opcode = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4;
6599
inst->resize_sources(1);
6600
inst->base_mrf = payload.nr;
6601
inst->header_size = 1;
6602
inst->mlen = 1 + inst->exec_size / 8;
6607
lower_math_logical_send(const fs_builder &bld, fs_inst *inst)
6609
assert(bld.shader->devinfo->ver < 6);
6612
inst->mlen = inst->sources * inst->exec_size / 8;
6614
if (inst->sources > 1) {
6615
/* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
6616
* "Message Payload":
6618
* "Operand0[7]. For the INT DIV functions, this operand is the
6621
* "Operand1[7]. For the INT DIV functions, this operand is the
6624
const bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
6625
const fs_reg src0 = is_int_div ? inst->src[1] : inst->src[0];
6626
const fs_reg src1 = is_int_div ? inst->src[0] : inst->src[1];
6628
inst->resize_sources(1);
6629
inst->src[0] = src0;
6631
assert(inst->exec_size == 8);
6632
bld.MOV(fs_reg(MRF, inst->base_mrf + 1, src1.type), src1);
6637
lower_btd_logical_send(const fs_builder &bld, fs_inst *inst)
6639
const intel_device_info *devinfo = bld.shader->devinfo;
6640
fs_reg global_addr = inst->src[0];
6641
const fs_reg &btd_record = inst->src[1];
6643
const unsigned mlen = 2;
6644
const fs_builder ubld = bld.exec_all().group(8, 0);
6645
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2);
6647
ubld.MOV(header, brw_imm_ud(0));
6648
switch (inst->opcode) {
6649
case SHADER_OPCODE_BTD_SPAWN_LOGICAL:
6650
assert(type_sz(global_addr.type) == 8 && global_addr.stride == 0);
6651
global_addr.type = BRW_REGISTER_TYPE_UD;
6652
global_addr.stride = 1;
6653
ubld.group(2, 0).MOV(header, global_addr);
6656
case SHADER_OPCODE_BTD_RETIRE_LOGICAL:
6657
/* The bottom bit is the Stack ID release bit */
6658
ubld.group(1, 0).MOV(header, brw_imm_ud(1));
6662
unreachable("Invalid BTD message");
6665
/* Stack IDs are always in R1 regardless of whether we're coming from a
6666
* bindless shader or a regular compute shader.
6669
retype(byte_offset(header, REG_SIZE), BRW_REGISTER_TYPE_UW);
6670
bld.MOV(stack_ids, retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UW));
6672
unsigned ex_mlen = 0;
6674
if (inst->opcode == SHADER_OPCODE_BTD_SPAWN_LOGICAL) {
6675
ex_mlen = 2 * (inst->exec_size / 8);
6676
payload = bld.move_to_vgrf(btd_record, 1);
6678
assert(inst->opcode == SHADER_OPCODE_BTD_RETIRE_LOGICAL);
6679
/* All these messages take a BTD and things complain if we don't provide
6680
* one for RETIRE. However, it shouldn't ever actually get used so fill
6683
ex_mlen = 2 * (inst->exec_size / 8);
6684
payload = bld.move_to_vgrf(brw_imm_uq(0), 1);
6687
/* Update the original instruction. */
6688
inst->opcode = SHADER_OPCODE_SEND;
6690
inst->ex_mlen = ex_mlen;
6691
inst->header_size = 0; /* HW docs require has_header = false */
6692
inst->send_has_side_effects = true;
6693
inst->send_is_volatile = false;
6695
/* Set up SFID and descriptors */
6696
inst->sfid = GEN_RT_SFID_BINDLESS_THREAD_DISPATCH;
6697
inst->desc = brw_btd_spawn_desc(devinfo, inst->exec_size,
6698
GEN_RT_BTD_MESSAGE_SPAWN);
6699
inst->resize_sources(4);
6700
inst->src[0] = brw_imm_ud(0); /* desc */
6701
inst->src[1] = brw_imm_ud(0); /* ex_desc */
6702
inst->src[2] = header;
6703
inst->src[3] = payload;
6707
lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst)
6709
const intel_device_info *devinfo = bld.shader->devinfo;
6710
const fs_reg &globals_addr = inst->src[RT_LOGICAL_SRC_GLOBALS];
6711
const fs_reg &bvh_level =
6712
inst->src[RT_LOGICAL_SRC_BVH_LEVEL].file == BRW_IMMEDIATE_VALUE ?
6713
inst->src[RT_LOGICAL_SRC_BVH_LEVEL] :
6714
bld.move_to_vgrf(inst->src[RT_LOGICAL_SRC_BVH_LEVEL],
6715
inst->components_read(RT_LOGICAL_SRC_BVH_LEVEL));
6716
const fs_reg &trace_ray_control =
6717
inst->src[RT_LOGICAL_SRC_TRACE_RAY_CONTROL].file == BRW_IMMEDIATE_VALUE ?
6718
inst->src[RT_LOGICAL_SRC_TRACE_RAY_CONTROL] :
6719
bld.move_to_vgrf(inst->src[RT_LOGICAL_SRC_TRACE_RAY_CONTROL],
6720
inst->components_read(RT_LOGICAL_SRC_TRACE_RAY_CONTROL));
6721
const fs_reg &synchronous_src = inst->src[RT_LOGICAL_SRC_SYNCHRONOUS];
6722
assert(synchronous_src.file == BRW_IMMEDIATE_VALUE);
6723
const bool synchronous = synchronous_src.ud;
6725
const unsigned mlen = 1;
6726
const fs_builder ubld = bld.exec_all().group(8, 0);
6727
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
6728
ubld.MOV(header, brw_imm_ud(0));
6729
ubld.group(2, 0).MOV(header, retype(globals_addr, BRW_REGISTER_TYPE_UD));
6731
ubld.group(1, 0).MOV(byte_offset(header, 16), brw_imm_ud(synchronous));
6733
const unsigned ex_mlen = inst->exec_size / 8;
6734
fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD);
6735
if (bvh_level.file == BRW_IMMEDIATE_VALUE &&
6736
trace_ray_control.file == BRW_IMMEDIATE_VALUE) {
6737
bld.MOV(payload, brw_imm_ud(SET_BITS(trace_ray_control.ud, 9, 8) |
6738
(bvh_level.ud & 0x7)));
6740
bld.SHL(payload, trace_ray_control, brw_imm_ud(8));
6741
bld.OR(payload, payload, bvh_level);
6744
/* When doing synchronous traversal, the HW implicitly computes the
6745
* stack_id using the following formula :
6747
* EUID[3:0] & THREAD_ID[2:0] & SIMD_LANE_ID[3:0]
6749
* Only in the asynchronous case we need to set the stack_id given from the
6753
bld.AND(subscript(payload, BRW_REGISTER_TYPE_UW, 1),
6754
retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UW),
6758
/* Update the original instruction. */
6759
inst->opcode = SHADER_OPCODE_SEND;
6761
inst->ex_mlen = ex_mlen;
6762
inst->header_size = 0; /* HW docs require has_header = false */
6763
inst->send_has_side_effects = true;
6764
inst->send_is_volatile = false;
6766
/* Set up SFID and descriptors */
6767
inst->sfid = GEN_RT_SFID_RAY_TRACE_ACCELERATOR;
6768
inst->desc = brw_rt_trace_ray_desc(devinfo, inst->exec_size);
6769
inst->resize_sources(4);
6770
inst->src[0] = brw_imm_ud(0); /* desc */
6771
inst->src[1] = brw_imm_ud(0); /* ex_desc */
6772
inst->src[2] = header;
6773
inst->src[3] = payload;
6777
fs_visitor::lower_logical_sends()
6779
bool progress = false;
6781
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
6782
const fs_builder ibld(this, block, inst);
6784
switch (inst->opcode) {
6785
case FS_OPCODE_FB_WRITE_LOGICAL:
6786
assert(stage == MESA_SHADER_FRAGMENT);
6787
lower_fb_write_logical_send(ibld, inst,
6788
brw_wm_prog_data(prog_data),
6789
(const brw_wm_prog_key *)key,
6793
case FS_OPCODE_FB_READ_LOGICAL:
6794
lower_fb_read_logical_send(ibld, inst);
6797
case SHADER_OPCODE_TEX_LOGICAL:
6798
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TEX);
6801
case SHADER_OPCODE_TXD_LOGICAL:
6802
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXD);
6805
case SHADER_OPCODE_TXF_LOGICAL:
6806
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF);
6809
case SHADER_OPCODE_TXL_LOGICAL:
6810
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXL);
6813
case SHADER_OPCODE_TXS_LOGICAL:
6814
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXS);
6817
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
6818
lower_sampler_logical_send(ibld, inst,
6819
SHADER_OPCODE_IMAGE_SIZE_LOGICAL);
6822
case FS_OPCODE_TXB_LOGICAL:
6823
lower_sampler_logical_send(ibld, inst, FS_OPCODE_TXB);
6826
case SHADER_OPCODE_TXF_CMS_LOGICAL:
6827
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS);
6830
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
6831
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
6832
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS_W);
6835
case SHADER_OPCODE_TXF_UMS_LOGICAL:
6836
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_UMS);
6839
case SHADER_OPCODE_TXF_MCS_LOGICAL:
6840
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_MCS);
6843
case SHADER_OPCODE_LOD_LOGICAL:
6844
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_LOD);
6847
case SHADER_OPCODE_TG4_LOGICAL:
6848
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4);
6851
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
6852
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4_OFFSET);
6855
case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
6856
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_SAMPLEINFO);
6859
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
6860
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
6861
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
6862
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
6863
case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
6864
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
6865
if (devinfo->has_lsc) {
6866
lower_lsc_surface_logical_send(ibld, inst);
6869
case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
6870
case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
6871
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
6872
case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
6873
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
6874
lower_surface_logical_send(ibld, inst);
6877
case SHADER_OPCODE_OWORD_BLOCK_READ_LOGICAL:
6878
case SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
6879
case SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL:
6880
lower_surface_block_logical_send(ibld, inst);
6883
case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
6884
case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
6885
case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
6886
case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
6887
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
6888
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL:
6889
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
6890
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
6891
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
6892
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
6893
if (devinfo->has_lsc) {
6894
lower_lsc_a64_logical_send(ibld, inst);
6897
case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL:
6898
case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
6899
case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL:
6900
lower_a64_logical_send(ibld, inst);
6903
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
6904
if (devinfo->has_lsc && !compiler->indirect_ubos_use_sampler)
6905
lower_lsc_varying_pull_constant_logical_send(ibld, inst);
6907
lower_varying_pull_constant_logical_send(ibld, inst);
6910
case SHADER_OPCODE_RCP:
6911
case SHADER_OPCODE_RSQ:
6912
case SHADER_OPCODE_SQRT:
6913
case SHADER_OPCODE_EXP2:
6914
case SHADER_OPCODE_LOG2:
6915
case SHADER_OPCODE_SIN:
6916
case SHADER_OPCODE_COS:
6917
case SHADER_OPCODE_POW:
6918
case SHADER_OPCODE_INT_QUOTIENT:
6919
case SHADER_OPCODE_INT_REMAINDER:
6920
/* The math opcodes are overloaded for the send-like and
6921
* expression-like instructions which seems kind of icky. Gfx6+ has
6922
* a native (but rather quirky) MATH instruction so we don't need to
6923
* do anything here. On Gfx4-5 we'll have to lower the Gfx6-like
6924
* logical instructions (which we can easily recognize because they
6925
* have mlen = 0) into send-like virtual instructions.
6927
if (devinfo->ver < 6 && inst->mlen == 0) {
6928
lower_math_logical_send(ibld, inst);
6935
case SHADER_OPCODE_BTD_SPAWN_LOGICAL:
6936
case SHADER_OPCODE_BTD_RETIRE_LOGICAL:
6937
lower_btd_logical_send(ibld, inst);
6940
case RT_OPCODE_TRACE_RAY_LOGICAL:
6941
lower_trace_ray_logical_send(ibld, inst);
6952
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
6958
is_mixed_float_with_fp32_dst(const fs_inst *inst)
6960
/* This opcode sometimes uses :W type on the source even if the operand is
6961
* a :HF, because in gfx7 there is no support for :HF, and thus it uses :W.
6963
if (inst->opcode == BRW_OPCODE_F16TO32)
6966
if (inst->dst.type != BRW_REGISTER_TYPE_F)
6969
for (int i = 0; i < inst->sources; i++) {
6970
if (inst->src[i].type == BRW_REGISTER_TYPE_HF)
6978
is_mixed_float_with_packed_fp16_dst(const fs_inst *inst)
6980
/* This opcode sometimes uses :W type on the destination even if the
6981
* destination is a :HF, because in gfx7 there is no support for :HF, and
6984
if (inst->opcode == BRW_OPCODE_F32TO16 &&
6985
inst->dst.stride == 1)
6988
if (inst->dst.type != BRW_REGISTER_TYPE_HF ||
6989
inst->dst.stride != 1)
6992
for (int i = 0; i < inst->sources; i++) {
6993
if (inst->src[i].type == BRW_REGISTER_TYPE_F)
7001
* Get the closest allowed SIMD width for instruction \p inst accounting for
7002
* some common regioning and execution control restrictions that apply to FPU
7003
* instructions. These restrictions don't necessarily have any relevance to
7004
* instructions not executed by the FPU pipeline like extended math, control
7005
* flow or send message instructions.
7007
* For virtual opcodes it's really up to the instruction -- In some cases
7008
* (e.g. where a virtual instruction unrolls into a simple sequence of FPU
7009
* instructions) it may simplify virtual instruction lowering if we can
7010
* enforce FPU-like regioning restrictions already on the virtual instruction,
7011
* in other cases (e.g. virtual send-like instructions) this may be
7012
* excessively restrictive.
7015
get_fpu_lowered_simd_width(const struct intel_device_info *devinfo,
7016
const fs_inst *inst)
7018
/* Maximum execution size representable in the instruction controls. */
7019
unsigned max_width = MIN2(32, inst->exec_size);
7021
/* According to the PRMs:
7022
* "A. In Direct Addressing mode, a source cannot span more than 2
7023
* adjacent GRF registers.
7024
* B. A destination cannot span more than 2 adjacent GRF registers."
7026
* Look for the source or destination with the largest register region
7027
* which is the one that is going to limit the overall execution size of
7028
* the instruction due to this rule.
7030
unsigned reg_count = DIV_ROUND_UP(inst->size_written, REG_SIZE);
7032
for (unsigned i = 0; i < inst->sources; i++)
7033
reg_count = MAX2(reg_count, DIV_ROUND_UP(inst->size_read(i), REG_SIZE));
7035
/* Calculate the maximum execution size of the instruction based on the
7036
* factor by which it goes over the hardware limit of 2 GRFs.
7039
max_width = MIN2(max_width, inst->exec_size / DIV_ROUND_UP(reg_count, 2));
7041
/* According to the IVB PRMs:
7042
* "When destination spans two registers, the source MUST span two
7043
* registers. The exception to the above rule:
7045
* - When source is scalar, the source registers are not incremented.
7046
* - When source is packed integer Word and destination is packed
7047
* integer DWord, the source register is not incremented but the
7048
* source sub register is incremented."
7050
* The hardware specs from Gfx4 to Gfx7.5 mention similar regioning
7051
* restrictions. The code below intentionally doesn't check whether the
7052
* destination type is integer because empirically the hardware doesn't
7053
* seem to care what the actual type is as long as it's dword-aligned.
7055
if (devinfo->ver < 8) {
7056
for (unsigned i = 0; i < inst->sources; i++) {
7057
/* IVB implements DF scalars as <0;2,1> regions. */
7058
const bool is_scalar_exception = is_uniform(inst->src[i]) &&
7059
(devinfo->platform == INTEL_PLATFORM_HSW || type_sz(inst->src[i].type) != 8);
7060
const bool is_packed_word_exception =
7061
type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 &&
7062
type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1;
7064
/* We check size_read(i) against size_written instead of REG_SIZE
7065
* because we want to properly handle SIMD32. In SIMD32, you can end
7066
* up with writes to 4 registers and a source that reads 2 registers
7067
* and we may still need to lower all the way to SIMD8 in that case.
7069
if (inst->size_written > REG_SIZE &&
7070
inst->size_read(i) != 0 &&
7071
inst->size_read(i) < inst->size_written &&
7072
!is_scalar_exception && !is_packed_word_exception) {
7073
const unsigned reg_count = DIV_ROUND_UP(inst->size_written, REG_SIZE);
7074
max_width = MIN2(max_width, inst->exec_size / reg_count);
7079
if (devinfo->ver < 6) {
7080
/* From the G45 PRM, Volume 4 Page 361:
7082
* "Operand Alignment Rule: With the exceptions listed below, a
7083
* source/destination operand in general should be aligned to even
7084
* 256-bit physical register with a region size equal to two 256-bit
7085
* physical registers."
7087
* Normally we enforce this by allocating virtual registers to the
7088
* even-aligned class. But we need to handle payload registers.
7090
for (unsigned i = 0; i < inst->sources; i++) {
7091
if (inst->src[i].file == FIXED_GRF && (inst->src[i].nr & 1) &&
7092
inst->size_read(i) > REG_SIZE) {
7093
max_width = MIN2(max_width, 8);
7098
/* From the IVB PRMs:
7099
* "When an instruction is SIMD32, the low 16 bits of the execution mask
7100
* are applied for both halves of the SIMD32 instruction. If different
7101
* execution mask channels are required, split the instruction into two
7102
* SIMD16 instructions."
7104
* There is similar text in the HSW PRMs. Gfx4-6 don't even implement
7105
* 32-wide control flow support in hardware and will behave similarly.
7107
if (devinfo->ver < 8 && !inst->force_writemask_all)
7108
max_width = MIN2(max_width, 16);
7110
/* From the IVB PRMs (applies to HSW too):
7111
* "Instructions with condition modifiers must not use SIMD32."
7113
* From the BDW PRMs (applies to later hardware too):
7114
* "Ternary instruction with condition modifiers must not use SIMD32."
7116
if (inst->conditional_mod && (devinfo->ver < 8 || inst->is_3src(devinfo)))
7117
max_width = MIN2(max_width, 16);
7119
/* From the IVB PRMs (applies to other devices that don't have the
7120
* intel_device_info::supports_simd16_3src flag set):
7121
* "In Align16 access mode, SIMD16 is not allowed for DW operations and
7122
* SIMD8 is not allowed for DF operations."
7124
if (inst->is_3src(devinfo) && !devinfo->supports_simd16_3src)
7125
max_width = MIN2(max_width, inst->exec_size / reg_count);
7127
/* Pre-Gfx8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
7128
* the 8-bit quarter of the execution mask signals specified in the
7129
* instruction control fields) for the second compressed half of any
7130
* single-precision instruction (for double-precision instructions
7131
* it's hardwired to use NibCtrl+1, at least on HSW), which means that
7132
* the EU will apply the wrong execution controls for the second
7133
* sequential GRF write if the number of channels per GRF is not exactly
7134
* eight in single-precision mode (or four in double-float mode).
7136
* In this situation we calculate the maximum size of the split
7137
* instructions so they only ever write to a single register.
7139
if (devinfo->ver < 8 && inst->size_written > REG_SIZE &&
7140
!inst->force_writemask_all) {
7141
const unsigned channels_per_grf = inst->exec_size /
7142
DIV_ROUND_UP(inst->size_written, REG_SIZE);
7143
const unsigned exec_type_size = get_exec_type_size(inst);
7144
assert(exec_type_size);
7146
/* The hardware shifts exactly 8 channels per compressed half of the
7147
* instruction in single-precision mode and exactly 4 in double-precision.
7149
if (channels_per_grf != (exec_type_size == 8 ? 4 : 8))
7150
max_width = MIN2(max_width, channels_per_grf);
7152
/* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
7153
* because HW applies the same channel enable signals to both halves of
7154
* the compressed instruction which will be just wrong under
7155
* non-uniform control flow.
7157
if (devinfo->verx10 == 70 &&
7158
(exec_type_size == 8 || type_sz(inst->dst.type) == 8))
7159
max_width = MIN2(max_width, 4);
7162
/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
7165
* "No SIMD16 in mixed mode when destination is f32. Instruction
7166
* execution size must be no more than 8."
7168
* FIXME: the simulator doesn't seem to complain if we don't do this and
7169
* empirical testing with existing CTS tests show that they pass just fine
7170
* without implementing this, however, since our interpretation of the PRM
7171
* is that conversion MOVs between HF and F are still mixed-float
7172
* instructions (and therefore subject to this restriction) we decided to
7173
* split them to be safe. Might be useful to do additional investigation to
7174
* lift the restriction if we can ensure that it is safe though, since these
7175
* conversions are common when half-float types are involved since many
7176
* instructions do not support HF types and conversions from/to F are
7179
if (is_mixed_float_with_fp32_dst(inst))
7180
max_width = MIN2(max_width, 8);
7182
/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
7185
* "No SIMD16 in mixed mode when destination is packed f16 for both
7186
* Align1 and Align16."
7188
if (is_mixed_float_with_packed_fp16_dst(inst))
7189
max_width = MIN2(max_width, 8);
7191
/* Only power-of-two execution sizes are representable in the instruction
7194
return 1 << util_logbase2(max_width);
7198
* Get the maximum allowed SIMD width for instruction \p inst accounting for
7199
* various payload size restrictions that apply to sampler message
7202
* This is only intended to provide a maximum theoretical bound for the
7203
* execution size of the message based on the number of argument components
7204
* alone, which in most cases will determine whether the SIMD8 or SIMD16
7205
* variant of the message can be used, though some messages may have
7206
* additional restrictions not accounted for here (e.g. pre-ILK hardware uses
7207
* the message length to determine the exact SIMD width and argument count,
7208
* which makes a number of sampler message combinations impossible to
7212
get_sampler_lowered_simd_width(const struct intel_device_info *devinfo,
7213
const fs_inst *inst)
7215
/* If we have a min_lod parameter on anything other than a simple sample
7216
* message, it will push it over 5 arguments and we have to fall back to
7219
if (inst->opcode != SHADER_OPCODE_TEX &&
7220
inst->components_read(TEX_LOGICAL_SRC_MIN_LOD))
7223
/* Calculate the number of coordinate components that have to be present
7224
* assuming that additional arguments follow the texel coordinates in the
7225
* message payload. On IVB+ there is no need for padding, on ILK-SNB we
7226
* need to pad to four or three components depending on the message,
7227
* pre-ILK we need to pad to at most three components.
7229
const unsigned req_coord_components =
7230
(devinfo->ver >= 7 ||
7231
!inst->components_read(TEX_LOGICAL_SRC_COORDINATE)) ? 0 :
7232
(devinfo->ver >= 5 && inst->opcode != SHADER_OPCODE_TXF_LOGICAL &&
7233
inst->opcode != SHADER_OPCODE_TXF_CMS_LOGICAL) ? 4 :
7236
/* On Gfx9+ the LOD argument is for free if we're able to use the LZ
7237
* variant of the TXL or TXF message.
7239
const bool implicit_lod = devinfo->ver >= 9 &&
7240
(inst->opcode == SHADER_OPCODE_TXL ||
7241
inst->opcode == SHADER_OPCODE_TXF) &&
7242
inst->src[TEX_LOGICAL_SRC_LOD].is_zero();
7244
/* Calculate the total number of argument components that need to be passed
7245
* to the sampler unit.
7247
const unsigned num_payload_components =
7248
MAX2(inst->components_read(TEX_LOGICAL_SRC_COORDINATE),
7249
req_coord_components) +
7250
inst->components_read(TEX_LOGICAL_SRC_SHADOW_C) +
7251
(implicit_lod ? 0 : inst->components_read(TEX_LOGICAL_SRC_LOD)) +
7252
inst->components_read(TEX_LOGICAL_SRC_LOD2) +
7253
inst->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX) +
7254
(inst->opcode == SHADER_OPCODE_TG4_OFFSET_LOGICAL ?
7255
inst->components_read(TEX_LOGICAL_SRC_TG4_OFFSET) : 0) +
7256
inst->components_read(TEX_LOGICAL_SRC_MCS);
7258
/* SIMD16 messages with more than five arguments exceed the maximum message
7259
* size supported by the sampler, regardless of whether a header is
7262
return MIN2(inst->exec_size,
7263
num_payload_components > MAX_SAMPLER_MESSAGE_SIZE / 2 ? 8 : 16);
7267
* Get the closest native SIMD width supported by the hardware for instruction
7268
* \p inst. The instruction will be left untouched by
7269
* fs_visitor::lower_simd_width() if the returned value is equal to the
7270
* original execution size.
7273
get_lowered_simd_width(const struct intel_device_info *devinfo,
7274
const fs_inst *inst)
7276
switch (inst->opcode) {
7277
case BRW_OPCODE_MOV:
7278
case BRW_OPCODE_SEL:
7279
case BRW_OPCODE_NOT:
7280
case BRW_OPCODE_AND:
7282
case BRW_OPCODE_XOR:
7283
case BRW_OPCODE_SHR:
7284
case BRW_OPCODE_SHL:
7285
case BRW_OPCODE_ASR:
7286
case BRW_OPCODE_ROR:
7287
case BRW_OPCODE_ROL:
7288
case BRW_OPCODE_CMPN:
7289
case BRW_OPCODE_CSEL:
7290
case BRW_OPCODE_F32TO16:
7291
case BRW_OPCODE_F16TO32:
7292
case BRW_OPCODE_BFREV:
7293
case BRW_OPCODE_BFE:
7294
case BRW_OPCODE_ADD:
7295
case BRW_OPCODE_MUL:
7296
case BRW_OPCODE_AVG:
7297
case BRW_OPCODE_FRC:
7298
case BRW_OPCODE_RNDU:
7299
case BRW_OPCODE_RNDD:
7300
case BRW_OPCODE_RNDE:
7301
case BRW_OPCODE_RNDZ:
7302
case BRW_OPCODE_LZD:
7303
case BRW_OPCODE_FBH:
7304
case BRW_OPCODE_FBL:
7305
case BRW_OPCODE_CBIT:
7306
case BRW_OPCODE_SAD2:
7307
case BRW_OPCODE_MAD:
7308
case BRW_OPCODE_LRP:
7309
case BRW_OPCODE_ADD3:
7310
case FS_OPCODE_PACK:
7311
case SHADER_OPCODE_SEL_EXEC:
7312
case SHADER_OPCODE_CLUSTER_BROADCAST:
7313
case SHADER_OPCODE_MOV_RELOC_IMM:
7314
return get_fpu_lowered_simd_width(devinfo, inst);
7316
case BRW_OPCODE_CMP: {
7317
/* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
7318
* when the destination is a GRF the dependency-clear bit on the flag
7319
* register is cleared early.
7321
* Suggested workarounds are to disable coissuing CMP instructions
7322
* or to split CMP(16) instructions into two CMP(8) instructions.
7324
* We choose to split into CMP(8) instructions since disabling
7325
* coissuing would affect CMP instructions not otherwise affected by
7328
const unsigned max_width = (devinfo->verx10 == 70 &&
7329
!inst->dst.is_null() ? 8 : ~0);
7330
return MIN2(max_width, get_fpu_lowered_simd_width(devinfo, inst));
7332
case BRW_OPCODE_BFI1:
7333
case BRW_OPCODE_BFI2:
7334
/* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
7336
* "Force BFI instructions to be executed always in SIMD8."
7338
return MIN2(devinfo->platform == INTEL_PLATFORM_HSW ? 8 : ~0u,
7339
get_fpu_lowered_simd_width(devinfo, inst));
7342
assert(inst->src[0].file == BAD_FILE || inst->exec_size <= 16);
7343
return inst->exec_size;
7345
case SHADER_OPCODE_RCP:
7346
case SHADER_OPCODE_RSQ:
7347
case SHADER_OPCODE_SQRT:
7348
case SHADER_OPCODE_EXP2:
7349
case SHADER_OPCODE_LOG2:
7350
case SHADER_OPCODE_SIN:
7351
case SHADER_OPCODE_COS: {
7352
/* Unary extended math instructions are limited to SIMD8 on Gfx4 and
7353
* Gfx6. Extended Math Function is limited to SIMD8 with half-float.
7355
if (devinfo->ver == 6 || devinfo->verx10 == 40)
7356
return MIN2(8, inst->exec_size);
7357
if (inst->dst.type == BRW_REGISTER_TYPE_HF)
7358
return MIN2(8, inst->exec_size);
7359
return MIN2(16, inst->exec_size);
7362
case SHADER_OPCODE_POW: {
7363
/* SIMD16 is only allowed on Gfx7+. Extended Math Function is limited
7364
* to SIMD8 with half-float
7366
if (devinfo->ver < 7)
7367
return MIN2(8, inst->exec_size);
7368
if (inst->dst.type == BRW_REGISTER_TYPE_HF)
7369
return MIN2(8, inst->exec_size);
7370
return MIN2(16, inst->exec_size);
7373
case SHADER_OPCODE_USUB_SAT:
7374
case SHADER_OPCODE_ISUB_SAT:
7375
return get_fpu_lowered_simd_width(devinfo, inst);
7377
case SHADER_OPCODE_INT_QUOTIENT:
7378
case SHADER_OPCODE_INT_REMAINDER:
7379
/* Integer division is limited to SIMD8 on all generations. */
7380
return MIN2(8, inst->exec_size);
7382
case FS_OPCODE_LINTERP:
7383
case SHADER_OPCODE_GET_BUFFER_SIZE:
7384
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
7385
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
7386
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
7387
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
7388
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
7389
return MIN2(16, inst->exec_size);
7391
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
7392
/* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
7393
* message used to implement varying pull constant loads, so expand it
7394
* to SIMD16. An alternative with longer message payload length but
7395
* shorter return payload would be to use the SIMD8 sampler message that
7396
* takes (header, u, v, r) as parameters instead of (header, u).
7398
return (devinfo->ver == 4 ? 16 : MIN2(16, inst->exec_size));
7400
case FS_OPCODE_DDX_COARSE:
7401
case FS_OPCODE_DDX_FINE:
7402
case FS_OPCODE_DDY_COARSE:
7403
case FS_OPCODE_DDY_FINE:
7404
/* The implementation of this virtual opcode may require emitting
7405
* compressed Align16 instructions, which are severely limited on some
7408
* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
7409
* Region Restrictions):
7411
* "In Align16 access mode, SIMD16 is not allowed for DW operations
7412
* and SIMD8 is not allowed for DF operations."
7414
* In this context, "DW operations" means "operations acting on 32-bit
7415
* values", so it includes operations on floats.
7417
* Gfx4 has a similar restriction. From the i965 PRM, section 11.5.3
7418
* (Instruction Compression -> Rules and Restrictions):
7420
* "A compressed instruction must be in Align1 access mode. Align16
7421
* mode instructions cannot be compressed."
7423
* Similar text exists in the g45 PRM.
7425
* Empirically, compressed align16 instructions using odd register
7426
* numbers don't appear to work on Sandybridge either.
7428
return (devinfo->ver == 4 || devinfo->ver == 6 ||
7429
(devinfo->verx10 == 70) ?
7430
MIN2(8, inst->exec_size) : MIN2(16, inst->exec_size));
7432
case SHADER_OPCODE_MULH:
7433
/* MULH is lowered to the MUL/MACH sequence using the accumulator, which
7434
* is 8-wide on Gfx7+.
7436
return (devinfo->ver >= 7 ? 8 :
7437
get_fpu_lowered_simd_width(devinfo, inst));
7439
case FS_OPCODE_FB_WRITE_LOGICAL:
7440
/* Gfx6 doesn't support SIMD16 depth writes but we cannot handle them
7443
assert(devinfo->ver != 6 ||
7444
inst->src[FB_WRITE_LOGICAL_SRC_SRC_DEPTH].file == BAD_FILE ||
7445
inst->exec_size == 8);
7446
/* Dual-source FB writes are unsupported in SIMD16 mode. */
7447
return (inst->src[FB_WRITE_LOGICAL_SRC_COLOR1].file != BAD_FILE ?
7448
8 : MIN2(16, inst->exec_size));
7450
case FS_OPCODE_FB_READ_LOGICAL:
7451
return MIN2(16, inst->exec_size);
7453
case SHADER_OPCODE_TEX_LOGICAL:
7454
case SHADER_OPCODE_TXF_CMS_LOGICAL:
7455
case SHADER_OPCODE_TXF_UMS_LOGICAL:
7456
case SHADER_OPCODE_TXF_MCS_LOGICAL:
7457
case SHADER_OPCODE_LOD_LOGICAL:
7458
case SHADER_OPCODE_TG4_LOGICAL:
7459
case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
7460
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
7461
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
7462
return get_sampler_lowered_simd_width(devinfo, inst);
7464
/* On gfx12 parameters are fixed to 16-bit values and therefore they all
7465
* always fit regardless of the execution size.
7467
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
7468
return MIN2(16, inst->exec_size);
7470
case SHADER_OPCODE_TXD_LOGICAL:
7471
/* TXD is unsupported in SIMD16 mode. */
7474
case SHADER_OPCODE_TXL_LOGICAL:
7475
case FS_OPCODE_TXB_LOGICAL:
7476
/* Only one execution size is representable pre-ILK depending on whether
7477
* the shadow reference argument is present.
7479
if (devinfo->ver == 4)
7480
return inst->src[TEX_LOGICAL_SRC_SHADOW_C].file == BAD_FILE ? 16 : 8;
7482
return get_sampler_lowered_simd_width(devinfo, inst);
7484
case SHADER_OPCODE_TXF_LOGICAL:
7485
case SHADER_OPCODE_TXS_LOGICAL:
7486
/* Gfx4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
7487
* messages. Use SIMD16 instead.
7489
if (devinfo->ver == 4)
7492
return get_sampler_lowered_simd_width(devinfo, inst);
7494
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
7495
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
7496
case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
7499
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
7500
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
7501
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
7502
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
7503
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
7504
case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
7505
case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
7506
case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
7507
return MIN2(16, inst->exec_size);
7509
case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
7510
case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
7511
case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
7512
case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
7513
return devinfo->ver <= 8 ? 8 : MIN2(16, inst->exec_size);
7515
case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL:
7516
case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
7517
case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL:
7518
assert(inst->exec_size <= 16);
7519
return inst->exec_size;
7521
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
7522
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT16_LOGICAL:
7523
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
7524
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
7525
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
7526
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
7529
case SHADER_OPCODE_URB_READ_SIMD8:
7530
case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
7531
case SHADER_OPCODE_URB_WRITE_SIMD8:
7532
case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
7533
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
7534
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
7535
return MIN2(8, inst->exec_size);
7537
case SHADER_OPCODE_QUAD_SWIZZLE: {
7538
const unsigned swiz = inst->src[1].ud;
7539
return (is_uniform(inst->src[0]) ?
7540
get_fpu_lowered_simd_width(devinfo, inst) :
7541
devinfo->ver < 11 && type_sz(inst->src[0].type) == 4 ? 8 :
7542
swiz == BRW_SWIZZLE_XYXY || swiz == BRW_SWIZZLE_ZWZW ? 4 :
7543
get_fpu_lowered_simd_width(devinfo, inst));
7545
case SHADER_OPCODE_MOV_INDIRECT: {
7546
/* From IVB and HSW PRMs:
7548
* "2.When the destination requires two registers and the sources are
7549
* indirect, the sources must use 1x1 regioning mode.
7551
* In case of DF instructions in HSW/IVB, the exec_size is limited by
7552
* the EU decompression logic not handling VxH indirect addressing
7555
const unsigned max_size = (devinfo->ver >= 8 ? 2 : 1) * REG_SIZE;
7556
/* Prior to Broadwell, we only have 8 address subregisters. */
7557
return MIN3(devinfo->ver >= 8 ? 16 : 8,
7558
max_size / (inst->dst.stride * type_sz(inst->dst.type)),
7562
case SHADER_OPCODE_LOAD_PAYLOAD: {
7563
const unsigned reg_count =
7564
DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE);
7566
if (reg_count > 2) {
7567
/* Only LOAD_PAYLOAD instructions with per-channel destination region
7568
* can be easily lowered (which excludes headers and heterogeneous
7571
assert(!inst->header_size);
7572
for (unsigned i = 0; i < inst->sources; i++)
7573
assert(type_sz(inst->dst.type) == type_sz(inst->src[i].type) ||
7574
inst->src[i].file == BAD_FILE);
7576
return inst->exec_size / DIV_ROUND_UP(reg_count, 2);
7578
return inst->exec_size;
7582
return inst->exec_size;
7587
* Return true if splitting out the group of channels of instruction \p inst
7588
* given by lbld.group() requires allocating a temporary for the i-th source
7589
* of the lowered instruction.
7592
needs_src_copy(const fs_builder &lbld, const fs_inst *inst, unsigned i)
7594
return !(is_periodic(inst->src[i], lbld.dispatch_width()) ||
7595
(inst->components_read(i) == 1 &&
7596
lbld.dispatch_width() <= inst->exec_size)) ||
7597
(inst->flags_written(lbld.shader->devinfo) &
7598
flag_mask(inst->src[i], type_sz(inst->src[i].type)));
7602
* Extract the data that would be consumed by the channel group given by
7603
* lbld.group() from the i-th source region of instruction \p inst and return
7604
* it as result in packed form.
7607
emit_unzip(const fs_builder &lbld, fs_inst *inst, unsigned i)
7609
assert(lbld.group() >= inst->group);
7611
/* Specified channel group from the source region. */
7612
const fs_reg src = horiz_offset(inst->src[i], lbld.group() - inst->group);
7614
if (needs_src_copy(lbld, inst, i)) {
7615
/* Builder of the right width to perform the copy avoiding uninitialized
7616
* data if the lowered execution size is greater than the original
7617
* execution size of the instruction.
7619
const fs_builder cbld = lbld.group(MIN2(lbld.dispatch_width(),
7620
inst->exec_size), 0);
7621
const fs_reg tmp = lbld.vgrf(inst->src[i].type, inst->components_read(i));
7623
for (unsigned k = 0; k < inst->components_read(i); ++k)
7624
cbld.MOV(offset(tmp, lbld, k), offset(src, inst->exec_size, k));
7628
} else if (is_periodic(inst->src[i], lbld.dispatch_width())) {
7629
/* The source is invariant for all dispatch_width-wide groups of the
7632
return inst->src[i];
7635
/* We can just point the lowered instruction at the right channel group
7636
* from the original region.
7643
* Return true if splitting out the group of channels of instruction \p inst
7644
* given by lbld.group() requires allocating a temporary for the destination
7645
* of the lowered instruction and copying the data back to the original
7646
* destination region.
7649
needs_dst_copy(const fs_builder &lbld, const fs_inst *inst)
7651
/* If the instruction writes more than one component we'll have to shuffle
7652
* the results of multiple lowered instructions in order to make sure that
7653
* they end up arranged correctly in the original destination region.
7655
if (inst->size_written > inst->dst.component_size(inst->exec_size))
7658
/* If the lowered execution size is larger than the original the result of
7659
* the instruction won't fit in the original destination, so we'll have to
7660
* allocate a temporary in any case.
7662
if (lbld.dispatch_width() > inst->exec_size)
7665
for (unsigned i = 0; i < inst->sources; i++) {
7666
/* If we already made a copy of the source for other reasons there won't
7667
* be any overlap with the destination.
7669
if (needs_src_copy(lbld, inst, i))
7672
/* In order to keep the logic simple we emit a copy whenever the
7673
* destination region doesn't exactly match an overlapping source, which
7674
* may point at the source and destination not being aligned group by
7675
* group which could cause one of the lowered instructions to overwrite
7676
* the data read from the same source by other lowered instructions.
7678
if (regions_overlap(inst->dst, inst->size_written,
7679
inst->src[i], inst->size_read(i)) &&
7680
!inst->dst.equals(inst->src[i]))
7688
* Insert data from a packed temporary into the channel group given by
7689
* lbld.group() of the destination region of instruction \p inst and return
7690
* the temporary as result. Any copy instructions that are required for
7691
* unzipping the previous value (in the case of partial writes) will be
7692
* inserted using \p lbld_before and any copy instructions required for
7693
* zipping up the destination of \p inst will be inserted using \p lbld_after.
7696
emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after,
7699
assert(lbld_before.dispatch_width() == lbld_after.dispatch_width());
7700
assert(lbld_before.group() == lbld_after.group());
7701
assert(lbld_after.group() >= inst->group);
7703
/* Specified channel group from the destination region. */
7704
const fs_reg dst = horiz_offset(inst->dst, lbld_after.group() - inst->group);
7705
const unsigned dst_size = inst->size_written /
7706
inst->dst.component_size(inst->exec_size);
7708
if (needs_dst_copy(lbld_after, inst)) {
7709
const fs_reg tmp = lbld_after.vgrf(inst->dst.type, dst_size);
7711
if (inst->predicate) {
7712
/* Handle predication by copying the original contents of
7713
* the destination into the temporary before emitting the
7714
* lowered instruction.
7716
const fs_builder gbld_before =
7717
lbld_before.group(MIN2(lbld_before.dispatch_width(),
7718
inst->exec_size), 0);
7719
for (unsigned k = 0; k < dst_size; ++k) {
7720
gbld_before.MOV(offset(tmp, lbld_before, k),
7721
offset(dst, inst->exec_size, k));
7725
const fs_builder gbld_after =
7726
lbld_after.group(MIN2(lbld_after.dispatch_width(),
7727
inst->exec_size), 0);
7728
for (unsigned k = 0; k < dst_size; ++k) {
7729
/* Use a builder of the right width to perform the copy avoiding
7730
* uninitialized data if the lowered execution size is greater than
7731
* the original execution size of the instruction.
7733
gbld_after.MOV(offset(dst, inst->exec_size, k),
7734
offset(tmp, lbld_after, k));
7740
/* No need to allocate a temporary for the lowered instruction, just
7741
* take the right group of channels from the original region.
7748
fs_visitor::lower_simd_width()
7750
bool progress = false;
7752
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
7753
const unsigned lower_width = get_lowered_simd_width(devinfo, inst);
7755
if (lower_width != inst->exec_size) {
7756
/* Builder matching the original instruction. We may also need to
7757
* emit an instruction of width larger than the original, set the
7758
* execution size of the builder to the highest of both for now so
7759
* we're sure that both cases can be handled.
7761
const unsigned max_width = MAX2(inst->exec_size, lower_width);
7762
const fs_builder ibld = bld.at(block, inst)
7763
.exec_all(inst->force_writemask_all)
7764
.group(max_width, inst->group / max_width);
7766
/* Split the copies in chunks of the execution width of either the
7767
* original or the lowered instruction, whichever is lower.
7769
const unsigned n = DIV_ROUND_UP(inst->exec_size, lower_width);
7770
const unsigned dst_size = inst->size_written /
7771
inst->dst.component_size(inst->exec_size);
7773
assert(!inst->writes_accumulator && !inst->mlen);
7775
/* Inserting the zip, unzip, and duplicated instructions in all of
7776
* the right spots is somewhat tricky. All of the unzip and any
7777
* instructions from the zip which unzip the destination prior to
7778
* writing need to happen before all of the per-group instructions
7779
* and the zip instructions need to happen after. In order to sort
7780
* this all out, we insert the unzip instructions before \p inst,
7781
* insert the per-group instructions after \p inst (i.e. before
7782
* inst->next), and insert the zip instructions before the
7783
* instruction after \p inst. Since we are inserting instructions
7784
* after \p inst, inst->next is a moving target and we need to save
7785
* it off here so that we insert the zip instructions in the right
7788
* Since we're inserting split instructions after after_inst, the
7789
* instructions will end up in the reverse order that we insert them.
7790
* However, certain render target writes require that the low group
7791
* instructions come before the high group. From the Ivy Bridge PRM
7792
* Vol. 4, Pt. 1, Section 3.9.11:
7794
* "If multiple SIMD8 Dual Source messages are delivered by the
7795
* pixel shader thread, each SIMD8_DUALSRC_LO message must be
7796
* issued before the SIMD8_DUALSRC_HI message with the same Slot
7797
* Group Select setting."
7799
* And, from Section 3.9.11.1 of the same PRM:
7801
* "When SIMD32 or SIMD16 PS threads send render target writes
7802
* with multiple SIMD8 and SIMD16 messages, the following must
7805
* All the slots (as described above) must have a corresponding
7806
* render target write irrespective of the slot's validity. A slot
7807
* is considered valid when at least one sample is enabled. For
7808
* example, a SIMD16 PS thread must send two SIMD8 render target
7809
* writes to cover all the slots.
7811
* PS thread must send SIMD render target write messages with
7812
* increasing slot numbers. For example, SIMD16 thread has
7813
* Slot[15:0] and if two SIMD8 render target writes are used, the
7814
* first SIMD8 render target write must send Slot[7:0] and the
7815
* next one must send Slot[15:8]."
7817
* In order to make low group instructions come before high group
7818
* instructions (this is required for some render target writes), we
7819
* split from the highest group to lowest.
7821
exec_node *const after_inst = inst->next;
7822
for (int i = n - 1; i >= 0; i--) {
7823
/* Emit a copy of the original instruction with the lowered width.
7824
* If the EOT flag was set throw it away except for the last
7825
* instruction to avoid killing the thread prematurely.
7827
fs_inst split_inst = *inst;
7828
split_inst.exec_size = lower_width;
7829
split_inst.eot = inst->eot && i == int(n - 1);
7831
/* Select the correct channel enables for the i-th group, then
7832
* transform the sources and destination and emit the lowered
7835
const fs_builder lbld = ibld.group(lower_width, i);
7837
for (unsigned j = 0; j < inst->sources; j++)
7838
split_inst.src[j] = emit_unzip(lbld.at(block, inst), inst, j);
7840
split_inst.dst = emit_zip(lbld.at(block, inst),
7841
lbld.at(block, after_inst), inst);
7842
split_inst.size_written =
7843
split_inst.dst.component_size(lower_width) * dst_size;
7845
lbld.at(block, inst->next).emit(split_inst);
7848
inst->remove(block);
7854
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
7860
* Transform barycentric vectors into the interleaved form expected by the PLN
7861
* instruction and returned by the Gfx7+ PI shared function.
7863
* For channels 0-15 in SIMD16 mode they are expected to be laid out as
7864
* follows in the register file:
7871
* There is no need to handle SIMD32 here -- This is expected to be run after
7872
* SIMD lowering, since SIMD lowering relies on vectors having the standard
7876
fs_visitor::lower_barycentrics()
7878
const bool has_interleaved_layout = devinfo->has_pln || devinfo->ver >= 7;
7879
bool progress = false;
7881
if (stage != MESA_SHADER_FRAGMENT || !has_interleaved_layout)
7884
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
7885
if (inst->exec_size < 16)
7888
const fs_builder ibld(this, block, inst);
7889
const fs_builder ubld = ibld.exec_all().group(8, 0);
7891
switch (inst->opcode) {
7892
case FS_OPCODE_LINTERP : {
7893
assert(inst->exec_size == 16);
7894
const fs_reg tmp = ibld.vgrf(inst->src[0].type, 2);
7897
for (unsigned i = 0; i < ARRAY_SIZE(srcs); i++)
7898
srcs[i] = horiz_offset(offset(inst->src[0], ibld, i % 2),
7901
ubld.LOAD_PAYLOAD(tmp, srcs, ARRAY_SIZE(srcs), ARRAY_SIZE(srcs));
7907
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
7908
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
7909
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: {
7910
assert(inst->exec_size == 16);
7911
const fs_reg tmp = ibld.vgrf(inst->dst.type, 2);
7913
for (unsigned i = 0; i < 2; i++) {
7914
for (unsigned g = 0; g < inst->exec_size / 8; g++) {
7915
fs_inst *mov = ibld.at(block, inst->next).group(8, g)
7916
.MOV(horiz_offset(offset(inst->dst, ibld, i),
7918
offset(tmp, ubld, 2 * g + i));
7919
mov->predicate = inst->predicate;
7920
mov->predicate_inverse = inst->predicate_inverse;
7921
mov->flag_subreg = inst->flag_subreg;
7935
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
7941
* Lower a derivative instruction as the floating-point difference of two
7942
* swizzles of the source, specified as \p swz0 and \p swz1.
7945
lower_derivative(fs_visitor *v, bblock_t *block, fs_inst *inst,
7946
unsigned swz0, unsigned swz1)
7948
const fs_builder ibld(v, block, inst);
7949
const fs_reg tmp0 = ibld.vgrf(inst->src[0].type);
7950
const fs_reg tmp1 = ibld.vgrf(inst->src[0].type);
7952
ibld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp0, inst->src[0], brw_imm_ud(swz0));
7953
ibld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp1, inst->src[0], brw_imm_ud(swz1));
7955
inst->resize_sources(2);
7956
inst->src[0] = negate(tmp0);
7957
inst->src[1] = tmp1;
7958
inst->opcode = BRW_OPCODE_ADD;
7964
* Lower derivative instructions on platforms where codegen cannot implement
7965
* them efficiently (i.e. XeHP).
7968
fs_visitor::lower_derivatives()
7970
bool progress = false;
7972
if (devinfo->verx10 < 125)
7975
foreach_block_and_inst(block, fs_inst, inst, cfg) {
7976
if (inst->opcode == FS_OPCODE_DDX_COARSE)
7977
progress |= lower_derivative(this, block, inst,
7978
BRW_SWIZZLE_XXXX, BRW_SWIZZLE_YYYY);
7980
else if (inst->opcode == FS_OPCODE_DDX_FINE)
7981
progress |= lower_derivative(this, block, inst,
7982
BRW_SWIZZLE_XXZZ, BRW_SWIZZLE_YYWW);
7984
else if (inst->opcode == FS_OPCODE_DDY_COARSE)
7985
progress |= lower_derivative(this, block, inst,
7986
BRW_SWIZZLE_XXXX, BRW_SWIZZLE_ZZZZ);
7988
else if (inst->opcode == FS_OPCODE_DDY_FINE)
7989
progress |= lower_derivative(this, block, inst,
7990
BRW_SWIZZLE_XYXY, BRW_SWIZZLE_ZWZW);
7994
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
8000
fs_visitor::dump_instructions() const
8002
dump_instructions(NULL);
8006
fs_visitor::dump_instructions(const char *name) const
8008
FILE *file = stderr;
8009
if (name && geteuid() != 0) {
8010
file = fopen(name, "w");
8016
const register_pressure &rp = regpressure_analysis.require();
8017
unsigned ip = 0, max_pressure = 0;
8018
foreach_block_and_inst(block, backend_instruction, inst, cfg) {
8019
max_pressure = MAX2(max_pressure, rp.regs_live_at_ip[ip]);
8020
fprintf(file, "{%3d} %4d: ", rp.regs_live_at_ip[ip], ip);
8021
dump_instruction(inst, file);
8024
fprintf(file, "Maximum %3d registers live at once.\n", max_pressure);
8027
foreach_in_list(backend_instruction, inst, &instructions) {
8028
fprintf(file, "%4d: ", ip++);
8029
dump_instruction(inst, file);
8033
if (file != stderr) {
8039
fs_visitor::dump_instruction(const backend_instruction *be_inst) const
8041
dump_instruction(be_inst, stderr);
8045
fs_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) const
8047
const fs_inst *inst = (const fs_inst *)be_inst;
8049
if (inst->predicate) {
8050
fprintf(file, "(%cf%d.%d) ",
8051
inst->predicate_inverse ? '-' : '+',
8052
inst->flag_subreg / 2,
8053
inst->flag_subreg % 2);
8056
fprintf(file, "%s", brw_instruction_name(devinfo, inst->opcode));
8058
fprintf(file, ".sat");
8059
if (inst->conditional_mod) {
8060
fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
8061
if (!inst->predicate &&
8062
(devinfo->ver < 5 || (inst->opcode != BRW_OPCODE_SEL &&
8063
inst->opcode != BRW_OPCODE_CSEL &&
8064
inst->opcode != BRW_OPCODE_IF &&
8065
inst->opcode != BRW_OPCODE_WHILE))) {
8066
fprintf(file, ".f%d.%d", inst->flag_subreg / 2,
8067
inst->flag_subreg % 2);
8070
fprintf(file, "(%d) ", inst->exec_size);
8073
fprintf(file, "(mlen: %d) ", inst->mlen);
8076
if (inst->ex_mlen) {
8077
fprintf(file, "(ex_mlen: %d) ", inst->ex_mlen);
8081
fprintf(file, "(EOT) ");
8084
switch (inst->dst.file) {
8086
fprintf(file, "vgrf%d", inst->dst.nr);
8089
fprintf(file, "g%d", inst->dst.nr);
8092
fprintf(file, "m%d", inst->dst.nr);
8095
fprintf(file, "(null)");
8098
fprintf(file, "***u%d***", inst->dst.nr);
8101
fprintf(file, "***attr%d***", inst->dst.nr);
8104
switch (inst->dst.nr) {
8106
fprintf(file, "null");
8108
case BRW_ARF_ADDRESS:
8109
fprintf(file, "a0.%d", inst->dst.subnr);
8111
case BRW_ARF_ACCUMULATOR:
8112
fprintf(file, "acc%d", inst->dst.subnr);
8115
fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
8118
fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
8123
unreachable("not reached");
8126
if (inst->dst.offset ||
8127
(inst->dst.file == VGRF &&
8128
alloc.sizes[inst->dst.nr] * REG_SIZE != inst->size_written)) {
8129
const unsigned reg_size = (inst->dst.file == UNIFORM ? 4 : REG_SIZE);
8130
fprintf(file, "+%d.%d", inst->dst.offset / reg_size,
8131
inst->dst.offset % reg_size);
8134
if (inst->dst.stride != 1)
8135
fprintf(file, "<%u>", inst->dst.stride);
8136
fprintf(file, ":%s, ", brw_reg_type_to_letters(inst->dst.type));
8138
for (int i = 0; i < inst->sources; i++) {
8139
if (inst->src[i].negate)
8141
if (inst->src[i].abs)
8143
switch (inst->src[i].file) {
8145
fprintf(file, "vgrf%d", inst->src[i].nr);
8148
fprintf(file, "g%d", inst->src[i].nr);
8151
fprintf(file, "***m%d***", inst->src[i].nr);
8154
fprintf(file, "attr%d", inst->src[i].nr);
8157
fprintf(file, "u%d", inst->src[i].nr);
8160
fprintf(file, "(null)");
8163
switch (inst->src[i].type) {
8164
case BRW_REGISTER_TYPE_HF:
8165
fprintf(file, "%-ghf", _mesa_half_to_float(inst->src[i].ud & 0xffff));
8167
case BRW_REGISTER_TYPE_F:
8168
fprintf(file, "%-gf", inst->src[i].f);
8170
case BRW_REGISTER_TYPE_DF:
8171
fprintf(file, "%fdf", inst->src[i].df);
8173
case BRW_REGISTER_TYPE_W:
8174
case BRW_REGISTER_TYPE_D:
8175
fprintf(file, "%dd", inst->src[i].d);
8177
case BRW_REGISTER_TYPE_UW:
8178
case BRW_REGISTER_TYPE_UD:
8179
fprintf(file, "%uu", inst->src[i].ud);
8181
case BRW_REGISTER_TYPE_Q:
8182
fprintf(file, "%" PRId64 "q", inst->src[i].d64);
8184
case BRW_REGISTER_TYPE_UQ:
8185
fprintf(file, "%" PRIu64 "uq", inst->src[i].u64);
8187
case BRW_REGISTER_TYPE_VF:
8188
fprintf(file, "[%-gF, %-gF, %-gF, %-gF]",
8189
brw_vf_to_float((inst->src[i].ud >> 0) & 0xff),
8190
brw_vf_to_float((inst->src[i].ud >> 8) & 0xff),
8191
brw_vf_to_float((inst->src[i].ud >> 16) & 0xff),
8192
brw_vf_to_float((inst->src[i].ud >> 24) & 0xff));
8194
case BRW_REGISTER_TYPE_V:
8195
case BRW_REGISTER_TYPE_UV:
8196
fprintf(file, "%08x%s", inst->src[i].ud,
8197
inst->src[i].type == BRW_REGISTER_TYPE_V ? "V" : "UV");
8200
fprintf(file, "???");
8205
switch (inst->src[i].nr) {
8207
fprintf(file, "null");
8209
case BRW_ARF_ADDRESS:
8210
fprintf(file, "a0.%d", inst->src[i].subnr);
8212
case BRW_ARF_ACCUMULATOR:
8213
fprintf(file, "acc%d", inst->src[i].subnr);
8216
fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
8219
fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
8225
if (inst->src[i].offset ||
8226
(inst->src[i].file == VGRF &&
8227
alloc.sizes[inst->src[i].nr] * REG_SIZE != inst->size_read(i))) {
8228
const unsigned reg_size = (inst->src[i].file == UNIFORM ? 4 : REG_SIZE);
8229
fprintf(file, "+%d.%d", inst->src[i].offset / reg_size,
8230
inst->src[i].offset % reg_size);
8233
if (inst->src[i].abs)
8236
if (inst->src[i].file != IMM) {
8238
if (inst->src[i].file == ARF || inst->src[i].file == FIXED_GRF) {
8239
unsigned hstride = inst->src[i].hstride;
8240
stride = (hstride == 0 ? 0 : (1 << (hstride - 1)));
8242
stride = inst->src[i].stride;
8245
fprintf(file, "<%u>", stride);
8247
fprintf(file, ":%s", brw_reg_type_to_letters(inst->src[i].type));
8250
if (i < inst->sources - 1 && inst->src[i + 1].file != BAD_FILE)
8251
fprintf(file, ", ");
8256
if (inst->force_writemask_all)
8257
fprintf(file, "NoMask ");
8259
if (inst->exec_size != dispatch_width)
8260
fprintf(file, "group%d ", inst->group);
8262
fprintf(file, "\n");
8266
fs_visitor::setup_fs_payload_gfx6()
8268
assert(stage == MESA_SHADER_FRAGMENT);
8269
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
8270
const unsigned payload_width = MIN2(16, dispatch_width);
8271
assert(dispatch_width % payload_width == 0);
8272
assert(devinfo->ver >= 6);
8274
/* R0: PS thread payload header. */
8277
for (unsigned j = 0; j < dispatch_width / payload_width; j++) {
8278
/* R1: masks, pixel X/Y coordinates. */
8279
payload.subspan_coord_reg[j] = payload.num_regs++;
8282
for (unsigned j = 0; j < dispatch_width / payload_width; j++) {
8283
/* R3-26: barycentric interpolation coordinates. These appear in the
8284
* same order that they appear in the brw_barycentric_mode enum. Each
8285
* set of coordinates occupies 2 registers if dispatch width == 8 and 4
8286
* registers if dispatch width == 16. Coordinates only appear if they
8287
* were enabled using the "Barycentric Interpolation Mode" bits in
8290
for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
8291
if (prog_data->barycentric_interp_modes & (1 << i)) {
8292
payload.barycentric_coord_reg[i][j] = payload.num_regs;
8293
payload.num_regs += payload_width / 4;
8297
/* R27-28: interpolated depth if uses source depth */
8298
if (prog_data->uses_src_depth) {
8299
payload.source_depth_reg[j] = payload.num_regs;
8300
payload.num_regs += payload_width / 8;
8303
/* R29-30: interpolated W set if GFX6_WM_USES_SOURCE_W. */
8304
if (prog_data->uses_src_w) {
8305
payload.source_w_reg[j] = payload.num_regs;
8306
payload.num_regs += payload_width / 8;
8309
/* R31: MSAA position offsets. */
8310
if (prog_data->uses_pos_offset) {
8311
payload.sample_pos_reg[j] = payload.num_regs;
8315
/* R32-33: MSAA input coverage mask */
8316
if (prog_data->uses_sample_mask) {
8317
assert(devinfo->ver >= 7);
8318
payload.sample_mask_in_reg[j] = payload.num_regs;
8319
payload.num_regs += payload_width / 8;
8322
/* R66: Source Depth and/or W Attribute Vertex Deltas */
8323
if (prog_data->uses_depth_w_coefficients) {
8324
payload.depth_w_coef_reg[j] = payload.num_regs;
8329
if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
8330
source_depth_to_render_target = true;
8335
fs_visitor::setup_vs_payload()
8337
/* R0: thread header, R1: urb handles */
8338
payload.num_regs = 2;
8342
fs_visitor::setup_gs_payload()
8344
assert(stage == MESA_SHADER_GEOMETRY);
8346
struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
8347
struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data);
8349
/* R0: thread header, R1: output URB handles */
8350
payload.num_regs = 2;
8352
if (gs_prog_data->include_primitive_id) {
8353
/* R2: Primitive ID 0..7 */
8357
/* Always enable VUE handles so we can safely use pull model if needed.
8359
* The push model for a GS uses a ton of register space even for trivial
8360
* scenarios with just a few inputs, so just make things easier and a bit
8361
* safer by always having pull model available.
8363
gs_prog_data->base.include_vue_handles = true;
8365
/* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
8366
payload.num_regs += nir->info.gs.vertices_in;
8368
/* Use a maximum of 24 registers for push-model inputs. */
8369
const unsigned max_push_components = 24;
8371
/* If pushing our inputs would take too many registers, reduce the URB read
8372
* length (which is in HWords, or 8 registers), and resort to pulling.
8374
* Note that the GS reads <URB Read Length> HWords for every vertex - so we
8375
* have to multiply by VerticesIn to obtain the total storage requirement.
8377
if (8 * vue_prog_data->urb_read_length * nir->info.gs.vertices_in >
8378
max_push_components) {
8379
vue_prog_data->urb_read_length =
8380
ROUND_DOWN_TO(max_push_components / nir->info.gs.vertices_in, 8) / 8;
8385
fs_visitor::setup_cs_payload()
8387
assert(devinfo->ver >= 7);
8388
/* TODO: Fill out uses_btd_stack_ids automatically */
8389
payload.num_regs = 1 + brw_cs_prog_data(prog_data)->uses_btd_stack_ids;
8392
brw::register_pressure::register_pressure(const fs_visitor *v)
8394
const fs_live_variables &live = v->live_analysis.require();
8395
const unsigned num_instructions = v->cfg->num_blocks ?
8396
v->cfg->blocks[v->cfg->num_blocks - 1]->end_ip + 1 : 0;
8398
regs_live_at_ip = new unsigned[num_instructions]();
8400
for (unsigned reg = 0; reg < v->alloc.count; reg++) {
8401
for (int ip = live.vgrf_start[reg]; ip <= live.vgrf_end[reg]; ip++)
8402
regs_live_at_ip[ip] += v->alloc.sizes[reg];
8406
brw::register_pressure::~register_pressure()
8408
delete[] regs_live_at_ip;
8412
fs_visitor::invalidate_analysis(brw::analysis_dependency_class c)
8414
backend_shader::invalidate_analysis(c);
8415
live_analysis.invalidate(c);
8416
regpressure_analysis.invalidate(c);
8420
fs_visitor::optimize()
8422
/* Start by validating the shader we currently have. */
8425
/* bld is the common builder object pointing at the end of the program we
8426
* used to translate it into i965 IR. For the optimization and lowering
8427
* passes coming next, any code added after the end of the program without
8428
* having explicitly called fs_builder::at() clearly points at a mistake.
8429
* Ideally optimization passes wouldn't be part of the visitor so they
8430
* wouldn't have access to bld at all, but they do, so just in case some
8431
* pass forgets to ask for a location explicitly set it to NULL here to
8432
* make it trip. The dispatch width is initialized to a bogus value to
8433
* make sure that optimizations set the execution controls explicitly to
8434
* match the code they are manipulating instead of relying on the defaults.
8436
bld = fs_builder(this, 64);
8438
assign_constant_locations();
8439
lower_constant_loads();
8443
#define OPT(pass, args...) ({ \
8445
bool this_progress = pass(args); \
8447
if (INTEL_DEBUG(DEBUG_OPTIMIZER) && this_progress) { \
8448
char filename[64]; \
8449
snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
8450
stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
8452
backend_shader::dump_instructions(filename); \
8457
progress = progress || this_progress; \
8461
if (INTEL_DEBUG(DEBUG_OPTIMIZER)) {
8463
snprintf(filename, 64, "%s%d-%s-00-00-start",
8464
stage_abbrev, dispatch_width, nir->info.name);
8466
backend_shader::dump_instructions(filename);
8469
bool progress = false;
8473
OPT(split_virtual_grfs);
8475
/* Before anything else, eliminate dead code. The results of some NIR
8476
* instructions may effectively be calculated twice. Once when the
8477
* instruction is encountered, and again when the user of that result is
8478
* encountered. Wipe those away before algebraic optimizations and
8479
* especially copy propagation can mix things up.
8481
OPT(dead_code_eliminate);
8483
OPT(remove_extra_rounding_modes);
8490
OPT(remove_duplicate_mrf_writes);
8494
OPT(opt_copy_propagation);
8495
OPT(opt_predicated_break, this);
8496
OPT(opt_cmod_propagation);
8497
OPT(dead_code_eliminate);
8498
OPT(opt_peephole_sel);
8499
OPT(dead_control_flow_eliminate, this);
8500
OPT(opt_register_renaming);
8501
OPT(opt_saturate_propagation);
8502
OPT(register_coalesce);
8503
OPT(compute_to_mrf);
8504
OPT(eliminate_find_live_channel);
8506
OPT(compact_virtual_grfs);
8512
if (OPT(lower_pack)) {
8513
OPT(register_coalesce);
8514
OPT(dead_code_eliminate);
8517
OPT(lower_simd_width);
8518
OPT(lower_barycentrics);
8519
OPT(lower_logical_sends);
8521
/* After logical SEND lowering. */
8522
OPT(fixup_nomask_control_flow);
8525
OPT(opt_copy_propagation);
8526
/* Only run after logical send lowering because it's easier to implement
8527
* in terms of physical sends.
8529
if (OPT(opt_zero_samples))
8530
OPT(opt_copy_propagation);
8531
/* Run after logical send lowering to give it a chance to CSE the
8532
* LOAD_PAYLOAD instructions created to construct the payloads of
8533
* e.g. texturing messages in cases where it wasn't possible to CSE the
8534
* whole logical instruction.
8537
OPT(register_coalesce);
8538
OPT(compute_to_mrf);
8539
OPT(dead_code_eliminate);
8540
OPT(remove_duplicate_mrf_writes);
8541
OPT(opt_peephole_sel);
8544
OPT(opt_redundant_halt);
8546
if (OPT(lower_load_payload)) {
8547
OPT(split_virtual_grfs);
8549
/* Lower 64 bit MOVs generated by payload lowering. */
8550
if (!devinfo->has_64bit_float && !devinfo->has_64bit_int)
8553
OPT(register_coalesce);
8554
OPT(lower_simd_width);
8555
OPT(compute_to_mrf);
8556
OPT(dead_code_eliminate);
8559
OPT(opt_combine_constants);
8560
if (OPT(lower_integer_multiplication)) {
8561
/* If lower_integer_multiplication made progress, it may have produced
8562
* some 32x32-bit MULs in the process of lowering 64-bit MULs. Run it
8563
* one more time to clean those up if they exist.
8565
OPT(lower_integer_multiplication);
8569
if (devinfo->ver <= 5 && OPT(lower_minmax)) {
8570
OPT(opt_cmod_propagation);
8572
OPT(opt_copy_propagation);
8573
OPT(dead_code_eliminate);
8577
OPT(lower_derivatives);
8578
OPT(lower_regioning);
8580
OPT(opt_copy_propagation);
8581
OPT(dead_code_eliminate);
8582
OPT(lower_simd_width);
8585
OPT(fixup_sends_duplicate_payload);
8587
lower_uniform_pull_constant_loads();
8593
* From the Skylake PRM Vol. 2a docs for sends:
8595
* "It is required that the second block of GRFs does not overlap with the
8598
* There are plenty of cases where we may accidentally violate this due to
8599
* having, for instance, both sources be the constant 0. This little pass
8600
* just adds a new vgrf for the second payload and copies it over.
8603
fs_visitor::fixup_sends_duplicate_payload()
8605
bool progress = false;
8607
foreach_block_and_inst_safe (block, fs_inst, inst, cfg) {
8608
if (inst->opcode == SHADER_OPCODE_SEND && inst->ex_mlen > 0 &&
8609
regions_overlap(inst->src[2], inst->mlen * REG_SIZE,
8610
inst->src[3], inst->ex_mlen * REG_SIZE)) {
8611
fs_reg tmp = fs_reg(VGRF, alloc.allocate(inst->ex_mlen),
8612
BRW_REGISTER_TYPE_UD);
8613
/* Sadly, we've lost all notion of channels and bit sizes at this
8614
* point. Just WE_all it.
8616
const fs_builder ibld = bld.at(block, inst).exec_all().group(16, 0);
8617
fs_reg copy_src = retype(inst->src[3], BRW_REGISTER_TYPE_UD);
8618
fs_reg copy_dst = tmp;
8619
for (unsigned i = 0; i < inst->ex_mlen; i += 2) {
8620
if (inst->ex_mlen == i + 1) {
8621
/* Only one register left; do SIMD8 */
8622
ibld.group(8, 0).MOV(copy_dst, copy_src);
8624
ibld.MOV(copy_dst, copy_src);
8626
copy_src = offset(copy_src, ibld, 1);
8627
copy_dst = offset(copy_dst, ibld, 1);
8635
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
8641
* Three source instruction must have a GRF/MRF destination register.
8642
* ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
8645
fs_visitor::fixup_3src_null_dest()
8647
bool progress = false;
8649
foreach_block_and_inst_safe (block, fs_inst, inst, cfg) {
8650
if (inst->is_3src(devinfo) && inst->dst.is_null()) {
8651
inst->dst = fs_reg(VGRF, alloc.allocate(dispatch_width / 8),
8658
invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL |
8659
DEPENDENCY_VARIABLES);
8663
needs_dummy_fence(const intel_device_info *devinfo, fs_inst *inst)
8665
/* This workaround is about making sure that any instruction writing
8666
* through UGM has completed before we hit EOT.
8668
* The workaround talks about UGM writes or atomic message but what is
8669
* important is anything that hasn't completed. Usually any SEND
8670
* instruction that has a destination register will be read by something
8671
* else so we don't need to care about those as they will be synchronized
8672
* by other parts of the shader or optimized away. What is left are
8673
* instructions that don't have a destination register.
8675
if (inst->sfid != GFX12_SFID_UGM)
8678
return inst->dst.file == BAD_FILE;
8683
* We need to emit UGM fence message before EOT, if shader has any UGM write
8684
* or atomic message.
8686
* TODO/FINISHME: According to Curro we could avoid the fence in some cases.
8687
* We probably need a better criteria in needs_dummy_fence().
8690
fs_visitor::emit_dummy_memory_fence_before_eot()
8692
bool progress = false;
8693
bool has_ugm_write_or_atomic = false;
8695
if (!intel_device_info_is_dg2(devinfo))
8698
foreach_block_and_inst_safe (block, fs_inst, inst, cfg) {
8700
if (needs_dummy_fence(devinfo, inst))
8701
has_ugm_write_or_atomic = true;
8705
if (!has_ugm_write_or_atomic)
8708
const fs_builder ibld(this, block, inst);
8709
const fs_builder ubld = ibld.exec_all().group(1, 0);
8711
fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_UD);
8712
fs_inst *dummy_fence = ubld.emit(SHADER_OPCODE_MEMORY_FENCE,
8713
dst, brw_vec8_grf(0, 0),
8714
/* commit enable */ brw_imm_ud(1),
8715
/* bti */ brw_imm_ud(0));
8716
dummy_fence->sfid = GFX12_SFID_UGM;
8717
dummy_fence->desc = lsc_fence_msg_desc(devinfo, LSC_FENCE_TILE,
8718
LSC_FLUSH_TYPE_NONE_6, false);
8719
ubld.emit(FS_OPCODE_SCHEDULING_FENCE, ubld.null_reg_ud(), dst);
8721
/* TODO: remove this break if we ever have shader with multiple EOT. */
8726
invalidate_analysis(DEPENDENCY_INSTRUCTIONS |
8727
DEPENDENCY_VARIABLES);
8732
* Find the first instruction in the program that might start a region of
8733
* divergent control flow due to a HALT jump. There is no
8734
* find_halt_control_flow_region_end(), the region of divergence extends until
8735
* the only SHADER_OPCODE_HALT_TARGET in the program.
8737
static const fs_inst *
8738
find_halt_control_flow_region_start(const fs_visitor *v)
8740
foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
8741
if (inst->opcode == BRW_OPCODE_HALT ||
8742
inst->opcode == SHADER_OPCODE_HALT_TARGET)
8750
* Work around the Gfx12 hardware bug filed as Wa_1407528679. EU fusion
8751
* can cause a BB to be executed with all channels disabled, which will lead
8752
* to the execution of any NoMask instructions in it, even though any
8753
* execution-masked instructions will be correctly shot down. This may break
8754
* assumptions of some NoMask SEND messages whose descriptor depends on data
8755
* generated by live invocations of the shader.
8757
* This avoids the problem by predicating certain instructions on an ANY
8758
* horizontal predicate that makes sure that their execution is omitted when
8759
* all channels of the program are disabled.
8762
fs_visitor::fixup_nomask_control_flow()
8764
if (devinfo->ver != 12)
8767
const brw_predicate pred = dispatch_width > 16 ? BRW_PREDICATE_ALIGN1_ANY32H :
8768
dispatch_width > 8 ? BRW_PREDICATE_ALIGN1_ANY16H :
8769
BRW_PREDICATE_ALIGN1_ANY8H;
8770
const fs_inst *halt_start = find_halt_control_flow_region_start(this);
8772
bool progress = false;
8774
const fs_live_variables &live_vars = live_analysis.require();
8776
/* Scan the program backwards in order to be able to easily determine
8777
* whether the flag register is live at any point.
8779
foreach_block_reverse_safe(block, cfg) {
8780
BITSET_WORD flag_liveout = live_vars.block_data[block->num]
8782
STATIC_ASSERT(ARRAY_SIZE(live_vars.block_data[0].flag_liveout) == 1);
8784
foreach_inst_in_block_reverse_safe(fs_inst, inst, block) {
8785
if (!inst->predicate && inst->exec_size >= 8)
8786
flag_liveout &= ~inst->flags_written(devinfo);
8788
switch (inst->opcode) {
8791
/* Note that this doesn't handle BRW_OPCODE_HALT since only
8792
* the first one in the program closes the region of divergent
8793
* control flow due to any HALT instructions -- Instead this is
8794
* handled with the halt_start check below.
8799
case BRW_OPCODE_WHILE:
8800
case BRW_OPCODE_ENDIF:
8801
case SHADER_OPCODE_HALT_TARGET:
8806
/* Note that the vast majority of NoMask SEND instructions in the
8807
* program are harmless while executed in a block with all
8808
* channels disabled, since any instructions with side effects we
8809
* could hit here should be execution-masked.
8811
* The main concern is NoMask SEND instructions where the message
8812
* descriptor or header depends on data generated by live
8813
* invocations of the shader (RESINFO and
8814
* FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD with a dynamically
8815
* computed surface index seem to be the only examples right now
8816
* where this could easily lead to GPU hangs). Unfortunately we
8817
* have no straightforward way to detect that currently, so just
8818
* predicate any NoMask SEND instructions we find under control
8821
* If this proves to have a measurable performance impact it can
8822
* be easily extended with a whitelist of messages we know we can
8823
* safely omit the predication for.
8825
if (depth && inst->force_writemask_all &&
8826
is_send(inst) && !inst->predicate) {
8827
/* We need to load the execution mask into the flag register by
8828
* using a builder with channel group matching the whole shader
8829
* (rather than the default which is derived from the original
8830
* instruction), in order to avoid getting a right-shifted
8833
const fs_builder ubld = fs_builder(this, block, inst)
8834
.exec_all().group(dispatch_width, 0);
8835
const fs_reg flag = retype(brw_flag_reg(0, 0),
8836
BRW_REGISTER_TYPE_UD);
8838
/* Due to the lack of flag register allocation we need to save
8839
* and restore the flag register if it's live.
8841
const bool save_flag = flag_liveout &
8842
flag_mask(flag, dispatch_width / 8);
8843
const fs_reg tmp = ubld.group(1, 0).vgrf(flag.type);
8846
ubld.group(1, 0).MOV(tmp, flag);
8848
ubld.emit(FS_OPCODE_LOAD_LIVE_CHANNELS);
8850
set_predicate(pred, inst);
8851
inst->flag_subreg = 0;
8854
ubld.group(1, 0).at(block, inst->next).MOV(flag, tmp);
8861
if (inst == halt_start)
8864
flag_liveout |= inst->flags_read(devinfo);
8869
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
8875
fs_visitor::allocate_registers(bool allow_spilling)
8879
static const enum instruction_scheduler_mode pre_modes[] = {
8881
SCHEDULE_PRE_NON_LIFO,
8886
static const char *scheduler_mode_name[] = {
8893
bool spill_all = allow_spilling && INTEL_DEBUG(DEBUG_SPILL_FS);
8895
/* Before we schedule anything, stash off the instruction order as an array
8896
* of fs_inst *. This way, we can reset it between scheduling passes to
8897
* prevent dependencies between the different scheduling modes.
8899
int num_insts = cfg->last_block()->end_ip + 1;
8900
fs_inst **inst_arr = ralloc_array(mem_ctx, fs_inst *, num_insts);
8903
foreach_block_and_inst(block, fs_inst, inst, cfg) {
8904
assert(ip >= block->start_ip && ip <= block->end_ip);
8905
inst_arr[ip++] = inst;
8907
assert(ip == num_insts);
8909
/* Try each scheduling heuristic to see if it can successfully register
8910
* allocate without spilling. They should be ordered by decreasing
8911
* performance but increasing likelihood of allocating.
8913
for (unsigned i = 0; i < ARRAY_SIZE(pre_modes); i++) {
8915
/* Unless we're the first pass, reset back to the original order */
8917
foreach_block (block, cfg) {
8918
block->instructions.make_empty();
8920
assert(ip == block->start_ip);
8921
for (; ip <= block->end_ip; ip++)
8922
block->instructions.push_tail(inst_arr[ip]);
8924
assert(ip == num_insts);
8926
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
8929
if (pre_modes[i] != SCHEDULE_NONE)
8930
schedule_instructions(pre_modes[i]);
8931
this->shader_stats.scheduler_mode = scheduler_mode_name[i];
8934
assign_regs_trivial();
8939
bool can_spill = allow_spilling &&
8940
(i == ARRAY_SIZE(pre_modes) - 1);
8942
/* We should only spill registers on the last scheduling. */
8943
assert(!spilled_any_registers);
8945
allocated = assign_regs(can_spill, spill_all);
8951
fail("Failure to register allocate. Reduce number of "
8952
"live scalar values to avoid this.");
8953
} else if (spilled_any_registers) {
8954
brw_shader_perf_log(compiler, log_data,
8955
"%s shader triggered register spilling. "
8956
"Try reducing the number of live scalar "
8957
"values to improve performance.\n",
8961
/* This must come after all optimization and register allocation, since
8962
* it inserts dead code that happens to have side effects, and it does
8963
* so based on the actual physical registers in use.
8965
insert_gfx4_send_dependency_workarounds();
8970
opt_bank_conflicts();
8972
schedule_instructions(SCHEDULE_POST);
8974
if (last_scratch > 0) {
8975
ASSERTED unsigned max_scratch_size = 2 * 1024 * 1024;
8977
/* Take the max of any previously compiled variant of the shader. In the
8978
* case of bindless shaders with return parts, this will also take the
8981
prog_data->total_scratch = MAX2(brw_get_scratch_size(last_scratch),
8982
prog_data->total_scratch);
8984
if (gl_shader_stage_is_compute(stage)) {
8985
if (devinfo->platform == INTEL_PLATFORM_HSW) {
8986
/* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
8987
* field documentation, Haswell supports a minimum of 2kB of
8988
* scratch space for compute shaders, unlike every other stage
8991
prog_data->total_scratch = MAX2(prog_data->total_scratch, 2048);
8992
} else if (devinfo->ver <= 7) {
8993
/* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
8994
* field documentation, platforms prior to Haswell measure scratch
8995
* size linearly with a range of [1kB, 12kB] and 1kB granularity.
8997
prog_data->total_scratch = ALIGN(last_scratch, 1024);
8998
max_scratch_size = 12 * 1024;
9002
/* We currently only support up to 2MB of scratch space. If we
9003
* need to support more eventually, the documentation suggests
9004
* that we could allocate a larger buffer, and partition it out
9005
* ourselves. We'd just have to undo the hardware's address
9006
* calculation by subtracting (FFTID * Per Thread Scratch Space)
9007
* and then add FFTID * (Larger Per Thread Scratch Space).
9009
* See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
9010
* Thread Group Tracking > Local Memory/Scratch Space.
9012
assert(prog_data->total_scratch < max_scratch_size);
9019
fs_visitor::run_vs()
9021
assert(stage == MESA_SHADER_VERTEX);
9036
assign_curb_setup();
9037
assign_vs_urb_setup();
9039
fixup_3src_null_dest();
9040
emit_dummy_memory_fence_before_eot();
9041
allocate_registers(true /* allow_spilling */);
9047
fs_visitor::set_tcs_invocation_id()
9049
struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
9050
struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
9052
const bool dg2_plus =
9053
devinfo->ver > 12 || intel_device_info_is_dg2(devinfo);
9054
const unsigned instance_id_mask =
9055
dg2_plus ? INTEL_MASK(7, 0) :
9056
(devinfo->ver >= 11) ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
9057
const unsigned instance_id_shift =
9058
dg2_plus ? 0 : (devinfo->ver >= 11) ? 16 : 17;
9060
/* Get instance number from g0.2 bits:
9065
fs_reg t = bld.vgrf(BRW_REGISTER_TYPE_UD);
9066
bld.AND(t, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)),
9067
brw_imm_ud(instance_id_mask));
9069
invocation_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
9071
if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH) {
9072
/* gl_InvocationID is just the thread number */
9073
bld.SHR(invocation_id, t, brw_imm_ud(instance_id_shift));
9077
assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH);
9079
fs_reg channels_uw = bld.vgrf(BRW_REGISTER_TYPE_UW);
9080
fs_reg channels_ud = bld.vgrf(BRW_REGISTER_TYPE_UD);
9081
bld.MOV(channels_uw, fs_reg(brw_imm_uv(0x76543210)));
9082
bld.MOV(channels_ud, channels_uw);
9084
if (tcs_prog_data->instances == 1) {
9085
invocation_id = channels_ud;
9087
fs_reg instance_times_8 = bld.vgrf(BRW_REGISTER_TYPE_UD);
9088
bld.SHR(instance_times_8, t, brw_imm_ud(instance_id_shift - 3));
9089
bld.ADD(invocation_id, instance_times_8, channels_ud);
9094
fs_visitor::run_tcs()
9096
assert(stage == MESA_SHADER_TESS_CTRL);
9098
struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data);
9099
struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
9100
struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key;
9102
assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH ||
9103
vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH);
9105
if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) {
9106
/* r1-r4 contain the ICP handles. */
9107
payload.num_regs = 5;
9109
assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH);
9110
assert(tcs_key->input_vertices > 0);
9111
/* r1 contains output handles, r2 may contain primitive ID, then the
9112
* ICP handles occupy the next 1-32 registers.
9114
payload.num_regs = 2 + tcs_prog_data->include_primitive_id +
9115
tcs_key->input_vertices;
9118
/* Initialize gl_InvocationID */
9119
set_tcs_invocation_id();
9121
const bool fix_dispatch_mask =
9122
vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH &&
9123
(nir->info.tess.tcs_vertices_out % 8) != 0;
9125
/* Fix the disptach mask */
9126
if (fix_dispatch_mask) {
9127
bld.CMP(bld.null_reg_ud(), invocation_id,
9128
brw_imm_ud(nir->info.tess.tcs_vertices_out), BRW_CONDITIONAL_L);
9129
bld.IF(BRW_PREDICATE_NORMAL);
9134
if (fix_dispatch_mask) {
9135
bld.emit(BRW_OPCODE_ENDIF);
9138
/* Emit EOT write; set TR DS Cache bit */
9140
fs_reg(get_tcs_output_urb_handle()),
9141
fs_reg(brw_imm_ud(WRITEMASK_X << 16)),
9142
fs_reg(brw_imm_ud(0)),
9144
fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 3);
9145
bld.LOAD_PAYLOAD(payload, srcs, 3, 2);
9147
fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
9148
bld.null_reg_ud(), payload);
9159
assign_curb_setup();
9160
assign_tcs_urb_setup();
9162
fixup_3src_null_dest();
9163
emit_dummy_memory_fence_before_eot();
9164
allocate_registers(true /* allow_spilling */);
9170
fs_visitor::run_tes()
9172
assert(stage == MESA_SHADER_TESS_EVAL);
9174
/* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
9175
payload.num_regs = 5;
9188
assign_curb_setup();
9189
assign_tes_urb_setup();
9191
fixup_3src_null_dest();
9192
emit_dummy_memory_fence_before_eot();
9193
allocate_registers(true /* allow_spilling */);
9199
fs_visitor::run_gs()
9201
assert(stage == MESA_SHADER_GEOMETRY);
9205
this->final_gs_vertex_count = vgrf(glsl_type::uint_type);
9207
if (gs_compile->control_data_header_size_bits > 0) {
9208
/* Create a VGRF to store accumulated control data bits. */
9209
this->control_data_bits = vgrf(glsl_type::uint_type);
9211
/* If we're outputting more than 32 control data bits, then EmitVertex()
9212
* will set control_data_bits to 0 after emitting the first vertex.
9213
* Otherwise, we need to initialize it to 0 here.
9215
if (gs_compile->control_data_header_size_bits <= 32) {
9216
const fs_builder abld = bld.annotate("initialize control data bits");
9217
abld.MOV(this->control_data_bits, brw_imm_ud(0u));
9223
emit_gs_thread_end();
9232
assign_curb_setup();
9233
assign_gs_urb_setup();
9235
fixup_3src_null_dest();
9236
emit_dummy_memory_fence_before_eot();
9237
allocate_registers(true /* allow_spilling */);
9242
/* From the SKL PRM, Volume 16, Workarounds:
9244
* 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
9245
* only header phases (R0-R2)
9247
* WA: Enable a non-header phase (e.g. push constant) when dispatch would
9248
* have been header only.
9250
* Instead of enabling push constants one can alternatively enable one of the
9251
* inputs. Here one simply chooses "layer" which shouldn't impose much
9255
gfx9_ps_header_only_workaround(struct brw_wm_prog_data *wm_prog_data)
9257
if (wm_prog_data->num_varying_inputs)
9260
if (wm_prog_data->base.curb_read_length)
9263
wm_prog_data->urb_setup[VARYING_SLOT_LAYER] = 0;
9264
wm_prog_data->num_varying_inputs = 1;
9266
brw_compute_urb_setup_index(wm_prog_data);
9270
fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
9272
struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data);
9273
brw_wm_prog_key *wm_key = (brw_wm_prog_key *) this->key;
9275
assert(stage == MESA_SHADER_FRAGMENT);
9277
if (devinfo->ver >= 6)
9278
setup_fs_payload_gfx6();
9280
setup_fs_payload_gfx4();
9284
} else if (do_rep_send) {
9285
assert(dispatch_width == 16);
9286
emit_repclear_shader();
9288
if (nir->info.inputs_read > 0 ||
9289
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
9290
(nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) {
9291
if (devinfo->ver < 6)
9292
emit_interpolation_setup_gfx4();
9294
emit_interpolation_setup_gfx6();
9297
/* We handle discards by keeping track of the still-live pixels in f0.1.
9298
* Initialize it with the dispatched pixels.
9300
if (wm_prog_data->uses_kill) {
9301
const unsigned lower_width = MIN2(dispatch_width, 16);
9302
for (unsigned i = 0; i < dispatch_width / lower_width; i++) {
9303
const fs_reg dispatch_mask =
9304
devinfo->ver >= 6 ? brw_vec1_grf((i ? 2 : 1), 7) :
9306
bld.exec_all().group(1, 0)
9307
.MOV(sample_mask_reg(bld.group(lower_width, i)),
9308
retype(dispatch_mask, BRW_REGISTER_TYPE_UW));
9312
if (nir->info.writes_memory)
9313
wm_prog_data->has_side_effects = true;
9320
if (wm_key->emit_alpha_test)
9329
assign_curb_setup();
9331
if (devinfo->ver == 9)
9332
gfx9_ps_header_only_workaround(wm_prog_data);
9336
fixup_3src_null_dest();
9337
emit_dummy_memory_fence_before_eot();
9339
allocate_registers(allow_spilling);
9346
fs_visitor::run_cs(bool allow_spilling)
9348
assert(gl_shader_stage_is_compute(stage));
9352
if (devinfo->platform == INTEL_PLATFORM_HSW && prog_data->total_shared > 0) {
9353
/* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
9354
const fs_builder abld = bld.exec_all().group(1, 0);
9355
abld.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW),
9356
suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW), 1));
9364
emit_cs_terminate();
9370
assign_curb_setup();
9372
fixup_3src_null_dest();
9373
emit_dummy_memory_fence_before_eot();
9374
allocate_registers(allow_spilling);
9380
fs_visitor::run_bs(bool allow_spilling)
9382
assert(stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE);
9384
/* R0: thread header, R1: stack IDs, R2: argument addresses */
9385
payload.num_regs = 3;
9392
/* TODO(RT): Perhaps rename this? */
9393
emit_cs_terminate();
9399
assign_curb_setup();
9401
fixup_3src_null_dest();
9402
emit_dummy_memory_fence_before_eot();
9403
allocate_registers(allow_spilling);
9409
fs_visitor::run_task(bool allow_spilling)
9411
assert(stage == MESA_SHADER_TASK);
9413
/* Task Shader Payloads (SIMD8 and SIMD16)
9416
* R1: Local_ID.X[0-7 or 0-15]
9417
* R2: Inline Parameter
9419
* Task Shader Payloads (SIMD32)
9422
* R1: Local_ID.X[0-15]
9423
* R2: Local_ID.X[16-31]
9424
* R3: Inline Parameter
9426
* Local_ID.X values are 16 bits.
9428
* Inline parameter is optional but always present since we use it to pass
9429
* the address to descriptors.
9431
payload.num_regs = dispatch_width == 32 ? 4 : 3;
9438
emit_cs_terminate();
9444
assign_curb_setup();
9446
fixup_3src_null_dest();
9447
emit_dummy_memory_fence_before_eot();
9448
allocate_registers(allow_spilling);
9454
fs_visitor::run_mesh(bool allow_spilling)
9456
assert(stage == MESA_SHADER_MESH);
9458
/* Mesh Shader Payloads (SIMD8 and SIMD16)
9461
* R1: Local_ID.X[0-7 or 0-15]
9462
* R2: Inline Parameter
9464
* Mesh Shader Payloads (SIMD32)
9467
* R1: Local_ID.X[0-15]
9468
* R2: Local_ID.X[16-31]
9469
* R3: Inline Parameter
9471
* Local_ID.X values are 16 bits.
9473
* Inline parameter is optional but always present since we use it to pass
9474
* the address to descriptors.
9476
payload.num_regs = dispatch_width == 32 ? 4 : 3;
9483
emit_cs_terminate();
9489
assign_curb_setup();
9491
fixup_3src_null_dest();
9492
emit_dummy_memory_fence_before_eot();
9493
allocate_registers(allow_spilling);
9499
is_used_in_not_interp_frag_coord(nir_ssa_def *def)
9501
nir_foreach_use(src, def) {
9502
if (src->parent_instr->type != nir_instr_type_intrinsic)
9505
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(src->parent_instr);
9506
if (intrin->intrinsic != nir_intrinsic_load_frag_coord)
9510
nir_foreach_if_use(src, def)
9517
* Return a bitfield where bit n is set if barycentric interpolation mode n
9518
* (see enum brw_barycentric_mode) is needed by the fragment shader.
9520
* We examine the load_barycentric intrinsics rather than looking at input
9521
* variables so that we catch interpolateAtCentroid() messages too, which
9522
* also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
9525
brw_compute_barycentric_interp_modes(const struct intel_device_info *devinfo,
9526
const nir_shader *shader)
9528
unsigned barycentric_interp_modes = 0;
9530
nir_foreach_function(f, shader) {
9534
nir_foreach_block(block, f->impl) {
9535
nir_foreach_instr(instr, block) {
9536
if (instr->type != nir_instr_type_intrinsic)
9539
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
9540
switch (intrin->intrinsic) {
9541
case nir_intrinsic_load_barycentric_pixel:
9542
case nir_intrinsic_load_barycentric_centroid:
9543
case nir_intrinsic_load_barycentric_sample:
9549
/* Ignore WPOS; it doesn't require interpolation. */
9550
assert(intrin->dest.is_ssa);
9551
if (!is_used_in_not_interp_frag_coord(&intrin->dest.ssa))
9554
enum glsl_interp_mode interp = (enum glsl_interp_mode)
9555
nir_intrinsic_interp_mode(intrin);
9556
nir_intrinsic_op bary_op = intrin->intrinsic;
9557
enum brw_barycentric_mode bary =
9558
brw_barycentric_mode(interp, bary_op);
9560
barycentric_interp_modes |= 1 << bary;
9562
if (devinfo->needs_unlit_centroid_workaround &&
9563
bary_op == nir_intrinsic_load_barycentric_centroid)
9564
barycentric_interp_modes |= 1 << centroid_to_pixel(bary);
9569
return barycentric_interp_modes;
9573
brw_compute_flat_inputs(struct brw_wm_prog_data *prog_data,
9574
const nir_shader *shader)
9576
prog_data->flat_inputs = 0;
9578
nir_foreach_shader_in_variable(var, shader) {
9580
if (var->data.interpolation != INTERP_MODE_FLAT)
9583
if (var->data.per_primitive)
9586
unsigned slots = glsl_count_attribute_slots(var->type, false);
9587
for (unsigned s = 0; s < slots; s++) {
9588
int input_index = prog_data->urb_setup[var->data.location + s];
9590
if (input_index >= 0)
9591
prog_data->flat_inputs |= 1 << input_index;
9597
computed_depth_mode(const nir_shader *shader)
9599
if (shader->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
9600
switch (shader->info.fs.depth_layout) {
9601
case FRAG_DEPTH_LAYOUT_NONE:
9602
case FRAG_DEPTH_LAYOUT_ANY:
9603
return BRW_PSCDEPTH_ON;
9604
case FRAG_DEPTH_LAYOUT_GREATER:
9605
return BRW_PSCDEPTH_ON_GE;
9606
case FRAG_DEPTH_LAYOUT_LESS:
9607
return BRW_PSCDEPTH_ON_LE;
9608
case FRAG_DEPTH_LAYOUT_UNCHANGED:
9609
return BRW_PSCDEPTH_OFF;
9612
return BRW_PSCDEPTH_OFF;
9616
* Move load_interpolated_input with simple (payload-based) barycentric modes
9617
* to the top of the program so we don't emit multiple PLNs for the same input.
9619
* This works around CSE not being able to handle non-dominating cases
9625
* interpolate the same exact input
9628
* This should be replaced by global value numbering someday.
9631
brw_nir_move_interpolation_to_top(nir_shader *nir)
9633
bool progress = false;
9635
nir_foreach_function(f, nir) {
9639
nir_block *top = nir_start_block(f->impl);
9640
exec_node *cursor_node = NULL;
9642
nir_foreach_block(block, f->impl) {
9646
nir_foreach_instr_safe(instr, block) {
9647
if (instr->type != nir_instr_type_intrinsic)
9650
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
9651
if (intrin->intrinsic != nir_intrinsic_load_interpolated_input)
9653
nir_intrinsic_instr *bary_intrinsic =
9654
nir_instr_as_intrinsic(intrin->src[0].ssa->parent_instr);
9655
nir_intrinsic_op op = bary_intrinsic->intrinsic;
9657
/* Leave interpolateAtSample/Offset() where they are. */
9658
if (op == nir_intrinsic_load_barycentric_at_sample ||
9659
op == nir_intrinsic_load_barycentric_at_offset)
9662
nir_instr *move[3] = {
9663
&bary_intrinsic->instr,
9664
intrin->src[1].ssa->parent_instr,
9668
for (unsigned i = 0; i < ARRAY_SIZE(move); i++) {
9669
if (move[i]->block != top) {
9670
move[i]->block = top;
9671
exec_node_remove(&move[i]->node);
9673
exec_node_insert_after(cursor_node, &move[i]->node);
9675
exec_list_push_head(&top->instr_list, &move[i]->node);
9677
cursor_node = &move[i]->node;
9683
nir_metadata_preserve(f->impl, nir_metadata_block_index |
9684
nir_metadata_dominance);
9691
brw_nir_demote_sample_qualifiers_instr(nir_builder *b,
9693
UNUSED void *cb_data)
9695
if (instr->type != nir_instr_type_intrinsic)
9698
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
9699
if (intrin->intrinsic != nir_intrinsic_load_barycentric_sample &&
9700
intrin->intrinsic != nir_intrinsic_load_barycentric_at_sample)
9703
b->cursor = nir_before_instr(instr);
9704
nir_ssa_def *centroid =
9705
nir_load_barycentric(b, nir_intrinsic_load_barycentric_centroid,
9706
nir_intrinsic_interp_mode(intrin));
9707
nir_ssa_def_rewrite_uses(&intrin->dest.ssa, centroid);
9708
nir_instr_remove(instr);
9713
* Demote per-sample barycentric intrinsics to centroid.
9715
* Useful when rendering to a non-multisampled buffer.
9718
brw_nir_demote_sample_qualifiers(nir_shader *nir)
9720
return nir_shader_instructions_pass(nir,
9721
brw_nir_demote_sample_qualifiers_instr,
9722
nir_metadata_block_index |
9723
nir_metadata_dominance,
9728
brw_nir_populate_wm_prog_data(const nir_shader *shader,
9729
const struct intel_device_info *devinfo,
9730
const struct brw_wm_prog_key *key,
9731
struct brw_wm_prog_data *prog_data,
9732
const struct brw_mue_map *mue_map)
9734
/* key->alpha_test_func means simulating alpha testing via discards,
9735
* so the shader definitely kills pixels.
9737
prog_data->uses_kill = shader->info.fs.uses_discard ||
9738
shader->info.fs.uses_demote ||
9739
key->emit_alpha_test;
9740
prog_data->uses_omask = !key->ignore_sample_mask_out &&
9741
(shader->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK));
9742
prog_data->color_outputs_written = key->color_outputs_valid;
9743
prog_data->computed_depth_mode = computed_depth_mode(shader);
9744
prog_data->computed_stencil =
9745
shader->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL);
9747
prog_data->persample_dispatch =
9748
key->multisample_fbo &&
9749
(key->persample_interp ||
9750
BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
9751
BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS) ||
9752
shader->info.fs.uses_sample_qualifier ||
9753
shader->info.outputs_read);
9755
if (devinfo->ver >= 6) {
9756
prog_data->uses_sample_mask =
9757
BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
9759
/* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
9761
* "MSDISPMODE_PERSAMPLE is required in order to select
9764
* So we can only really get sample positions if we are doing real
9765
* per-sample dispatch. If we need gl_SamplePosition and we don't have
9766
* persample dispatch, we hard-code it to 0.5.
9768
prog_data->uses_pos_offset = prog_data->persample_dispatch &&
9769
(BITSET_TEST(shader->info.system_values_read,
9770
SYSTEM_VALUE_SAMPLE_POS) ||
9771
BITSET_TEST(shader->info.system_values_read,
9772
SYSTEM_VALUE_SAMPLE_POS_OR_CENTER));
9775
prog_data->has_render_target_reads = shader->info.outputs_read != 0ull;
9777
prog_data->early_fragment_tests = shader->info.fs.early_fragment_tests;
9778
prog_data->post_depth_coverage = shader->info.fs.post_depth_coverage;
9779
prog_data->inner_coverage = shader->info.fs.inner_coverage;
9781
prog_data->barycentric_interp_modes =
9782
brw_compute_barycentric_interp_modes(devinfo, shader);
9784
prog_data->per_coarse_pixel_dispatch =
9785
key->coarse_pixel &&
9786
!prog_data->uses_omask &&
9787
!prog_data->persample_dispatch &&
9788
!prog_data->uses_sample_mask &&
9789
(prog_data->computed_depth_mode == BRW_PSCDEPTH_OFF) &&
9790
!prog_data->computed_stencil;
9792
prog_data->uses_src_w =
9793
BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_FRAG_COORD);
9794
prog_data->uses_src_depth =
9795
BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) &&
9796
!prog_data->per_coarse_pixel_dispatch;
9797
prog_data->uses_depth_w_coefficients =
9798
BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) &&
9799
prog_data->per_coarse_pixel_dispatch;
9801
calculate_urb_setup(devinfo, key, prog_data, shader, mue_map);
9802
brw_compute_flat_inputs(prog_data, shader);
9806
* Pre-gfx6, the register file of the EUs was shared between threads,
9807
* and each thread used some subset allocated on a 16-register block
9808
* granularity. The unit states wanted these block counts.
9811
brw_register_blocks(int reg_count)
9813
return ALIGN(reg_count, 16) / 16 - 1;
9817
brw_compile_fs(const struct brw_compiler *compiler,
9819
struct brw_compile_fs_params *params)
9821
struct nir_shader *nir = params->nir;
9822
const struct brw_wm_prog_key *key = params->key;
9823
struct brw_wm_prog_data *prog_data = params->prog_data;
9824
bool allow_spilling = params->allow_spilling;
9825
const bool debug_enabled =
9826
INTEL_DEBUG(params->debug_flag ? params->debug_flag : DEBUG_WM);
9828
prog_data->base.stage = MESA_SHADER_FRAGMENT;
9829
prog_data->base.ray_queries = nir->info.ray_queries;
9830
prog_data->base.total_scratch = 0;
9832
const struct intel_device_info *devinfo = compiler->devinfo;
9833
const unsigned max_subgroup_size = compiler->devinfo->ver >= 6 ? 32 : 16;
9835
brw_nir_apply_key(nir, compiler, &key->base, max_subgroup_size, true);
9836
brw_nir_lower_fs_inputs(nir, devinfo, key);
9837
brw_nir_lower_fs_outputs(nir);
9839
if (devinfo->ver < 6)
9840
brw_setup_vue_interpolation(params->vue_map, nir, prog_data);
9842
/* From the SKL PRM, Volume 7, "Alpha Coverage":
9843
* "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
9844
* hardware, regardless of the state setting for this feature."
9846
if (devinfo->ver > 6 && key->alpha_to_coverage) {
9847
/* Run constant fold optimization in order to get the correct source
9848
* offset to determine render target 0 store instruction in
9849
* emit_alpha_to_coverage pass.
9851
NIR_PASS_V(nir, nir_opt_constant_folding);
9852
NIR_PASS_V(nir, brw_nir_lower_alpha_to_coverage);
9855
if (!key->multisample_fbo)
9856
NIR_PASS_V(nir, brw_nir_demote_sample_qualifiers);
9857
NIR_PASS_V(nir, brw_nir_move_interpolation_to_top);
9858
brw_postprocess_nir(nir, compiler, true, debug_enabled,
9859
key->base.robust_buffer_access);
9861
brw_nir_populate_wm_prog_data(nir, compiler->devinfo, key, prog_data,
9864
fs_visitor *v8 = NULL, *v16 = NULL, *v32 = NULL;
9865
cfg_t *simd8_cfg = NULL, *simd16_cfg = NULL, *simd32_cfg = NULL;
9866
float throughput = 0;
9867
bool has_spilled = false;
9869
v8 = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
9870
&prog_data->base, nir, 8,
9872
if (!v8->run_fs(allow_spilling, false /* do_rep_send */)) {
9873
params->error_str = ralloc_strdup(mem_ctx, v8->fail_msg);
9876
} else if (!INTEL_DEBUG(DEBUG_NO8)) {
9877
simd8_cfg = v8->cfg;
9878
prog_data->base.dispatch_grf_start_reg = v8->payload.num_regs;
9879
prog_data->reg_blocks_8 = brw_register_blocks(v8->grf_used);
9880
const performance &perf = v8->performance_analysis.require();
9881
throughput = MAX2(throughput, perf.throughput);
9882
has_spilled = v8->spilled_any_registers;
9883
allow_spilling = false;
9886
/* Limit dispatch width to simd8 with dual source blending on gfx8.
9887
* See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1917
9889
if (devinfo->ver == 8 && prog_data->dual_src_blend &&
9890
!INTEL_DEBUG(DEBUG_NO8)) {
9891
assert(!params->use_rep_send);
9892
v8->limit_dispatch_width(8, "gfx8 workaround: "
9893
"using SIMD8 when dual src blending.\n");
9896
if (key->coarse_pixel) {
9897
if (prog_data->dual_src_blend) {
9898
v8->limit_dispatch_width(8, "SIMD16 coarse pixel shading cannot"
9899
" use SIMD8 messages.\n");
9901
v8->limit_dispatch_width(16, "SIMD32 not supported with coarse"
9902
" pixel shading.\n");
9905
if (nir->info.ray_queries > 0)
9906
v8->limit_dispatch_width(16, "SIMD32 with ray queries.\n");
9909
v8->max_dispatch_width >= 16 &&
9910
(!INTEL_DEBUG(DEBUG_NO16) || params->use_rep_send)) {
9911
/* Try a SIMD16 compile */
9912
v16 = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
9913
&prog_data->base, nir, 16,
9915
v16->import_uniforms(v8);
9916
if (!v16->run_fs(allow_spilling, params->use_rep_send)) {
9917
brw_shader_perf_log(compiler, params->log_data,
9918
"SIMD16 shader failed to compile: %s\n",
9921
simd16_cfg = v16->cfg;
9922
prog_data->dispatch_grf_start_reg_16 = v16->payload.num_regs;
9923
prog_data->reg_blocks_16 = brw_register_blocks(v16->grf_used);
9924
const performance &perf = v16->performance_analysis.require();
9925
throughput = MAX2(throughput, perf.throughput);
9926
has_spilled = v16->spilled_any_registers;
9927
allow_spilling = false;
9931
const bool simd16_failed = v16 && !simd16_cfg;
9933
/* Currently, the compiler only supports SIMD32 on SNB+ */
9935
v8->max_dispatch_width >= 32 && !params->use_rep_send &&
9936
devinfo->ver >= 6 && !simd16_failed &&
9937
!INTEL_DEBUG(DEBUG_NO32)) {
9938
/* Try a SIMD32 compile */
9939
v32 = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
9940
&prog_data->base, nir, 32,
9942
v32->import_uniforms(v8);
9943
if (!v32->run_fs(allow_spilling, false)) {
9944
brw_shader_perf_log(compiler, params->log_data,
9945
"SIMD32 shader failed to compile: %s\n",
9948
const performance &perf = v32->performance_analysis.require();
9950
if (!INTEL_DEBUG(DEBUG_DO32) && throughput >= perf.throughput) {
9951
brw_shader_perf_log(compiler, params->log_data,
9952
"SIMD32 shader inefficient\n");
9954
simd32_cfg = v32->cfg;
9955
prog_data->dispatch_grf_start_reg_32 = v32->payload.num_regs;
9956
prog_data->reg_blocks_32 = brw_register_blocks(v32->grf_used);
9957
throughput = MAX2(throughput, perf.throughput);
9962
/* When the caller requests a repclear shader, they want SIMD16-only */
9963
if (params->use_rep_send)
9966
/* Prior to Iron Lake, the PS had a single shader offset with a jump table
9967
* at the top to select the shader. We've never implemented that.
9968
* Instead, we just give them exactly one shader and we pick the widest one
9971
if (compiler->devinfo->ver < 5) {
9972
if (simd32_cfg || simd16_cfg)
9978
/* If computed depth is enabled SNB only allows SIMD8. */
9979
if (compiler->devinfo->ver == 6 &&
9980
prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF)
9981
assert(simd16_cfg == NULL && simd32_cfg == NULL);
9983
if (compiler->devinfo->ver <= 5 && !simd8_cfg) {
9984
/* Iron lake and earlier only have one Dispatch GRF start field. Make
9985
* the data available in the base prog data struct for convenience.
9988
prog_data->base.dispatch_grf_start_reg =
9989
prog_data->dispatch_grf_start_reg_16;
9990
} else if (simd32_cfg) {
9991
prog_data->base.dispatch_grf_start_reg =
9992
prog_data->dispatch_grf_start_reg_32;
9996
if (prog_data->persample_dispatch) {
9997
/* Starting with SandyBridge (where we first get MSAA), the different
9998
* pixel dispatch combinations are grouped into classifications A
9999
* through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On most hardware
10000
* generations, the only configurations supporting persample dispatch
10001
* are those in which only one dispatch width is enabled.
10003
* The Gfx12 hardware spec has a similar dispatch grouping table, but
10004
* the following conflicting restriction applies (from the page on
10005
* "Structure_3DSTATE_PS_BODY"), so we need to keep the SIMD16 shader:
10007
* "SIMD32 may only be enabled if SIMD16 or (dual)SIMD8 is also
10010
if (simd32_cfg || simd16_cfg)
10012
if (simd32_cfg && devinfo->ver < 12)
10016
fs_generator g(compiler, params->log_data, mem_ctx, &prog_data->base,
10017
v8->runtime_check_aads_emit, MESA_SHADER_FRAGMENT);
10019
if (unlikely(debug_enabled)) {
10020
g.enable_debug(ralloc_asprintf(mem_ctx, "%s fragment shader %s",
10022
nir->info.label : "unnamed",
10026
struct brw_compile_stats *stats = params->stats;
10029
prog_data->dispatch_8 = true;
10030
g.generate_code(simd8_cfg, 8, v8->shader_stats,
10031
v8->performance_analysis.require(), stats);
10032
stats = stats ? stats + 1 : NULL;
10036
prog_data->dispatch_16 = true;
10037
prog_data->prog_offset_16 = g.generate_code(
10038
simd16_cfg, 16, v16->shader_stats,
10039
v16->performance_analysis.require(), stats);
10040
stats = stats ? stats + 1 : NULL;
10044
prog_data->dispatch_32 = true;
10045
prog_data->prog_offset_32 = g.generate_code(
10046
simd32_cfg, 32, v32->shader_stats,
10047
v32->performance_analysis.require(), stats);
10048
stats = stats ? stats + 1 : NULL;
10051
g.add_const_data(nir->constant_data, nir->constant_data_size);
10057
return g.get_assembly();
10061
fs_visitor::emit_work_group_id_setup()
10063
assert(gl_shader_stage_uses_workgroup(stage));
10065
fs_reg id = bld.vgrf(BRW_REGISTER_TYPE_UD, 3);
10067
struct brw_reg r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
10070
if (gl_shader_stage_is_compute(stage)) {
10071
struct brw_reg r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD));
10072
struct brw_reg r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD));
10073
bld.MOV(offset(id, bld, 1), r0_6);
10074
bld.MOV(offset(id, bld, 2), r0_7);
10076
/* Task/Mesh have a single Workgroup ID dimension in the HW. */
10077
bld.MOV(offset(id, bld, 1), brw_imm_ud(0));
10078
bld.MOV(offset(id, bld, 2), brw_imm_ud(0));
10085
brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data,
10088
assert(cs_prog_data->push.per_thread.size % REG_SIZE == 0);
10089
assert(cs_prog_data->push.cross_thread.size % REG_SIZE == 0);
10090
return cs_prog_data->push.per_thread.size * threads +
10091
cs_prog_data->push.cross_thread.size;
10095
fill_push_const_block_info(struct brw_push_const_block *block, unsigned dwords)
10097
block->dwords = dwords;
10098
block->regs = DIV_ROUND_UP(dwords, 8);
10099
block->size = block->regs * 32;
10103
cs_fill_push_const_info(const struct intel_device_info *devinfo,
10104
struct brw_cs_prog_data *cs_prog_data)
10106
const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
10107
int subgroup_id_index = get_subgroup_id_param_index(devinfo, prog_data);
10108
bool cross_thread_supported = devinfo->verx10 >= 75;
10110
/* The thread ID should be stored in the last param dword */
10111
assert(subgroup_id_index == -1 ||
10112
subgroup_id_index == (int)prog_data->nr_params - 1);
10114
unsigned cross_thread_dwords, per_thread_dwords;
10115
if (!cross_thread_supported) {
10116
cross_thread_dwords = 0u;
10117
per_thread_dwords = prog_data->nr_params;
10118
} else if (subgroup_id_index >= 0) {
10119
/* Fill all but the last register with cross-thread payload */
10120
cross_thread_dwords = 8 * (subgroup_id_index / 8);
10121
per_thread_dwords = prog_data->nr_params - cross_thread_dwords;
10122
assert(per_thread_dwords > 0 && per_thread_dwords <= 8);
10124
/* Fill all data using cross-thread payload */
10125
cross_thread_dwords = prog_data->nr_params;
10126
per_thread_dwords = 0u;
10129
fill_push_const_block_info(&cs_prog_data->push.cross_thread, cross_thread_dwords);
10130
fill_push_const_block_info(&cs_prog_data->push.per_thread, per_thread_dwords);
10132
assert(cs_prog_data->push.cross_thread.dwords % 8 == 0 ||
10133
cs_prog_data->push.per_thread.size == 0);
10134
assert(cs_prog_data->push.cross_thread.dwords +
10135
cs_prog_data->push.per_thread.dwords ==
10136
prog_data->nr_params);
10140
filter_simd(const nir_instr *instr, const void * /* options */)
10142
if (instr->type != nir_instr_type_intrinsic)
10145
switch (nir_instr_as_intrinsic(instr)->intrinsic) {
10146
case nir_intrinsic_load_simd_width_intel:
10147
case nir_intrinsic_load_subgroup_id:
10155
static nir_ssa_def *
10156
lower_simd(nir_builder *b, nir_instr *instr, void *options)
10158
uintptr_t simd_width = (uintptr_t)options;
10160
switch (nir_instr_as_intrinsic(instr)->intrinsic) {
10161
case nir_intrinsic_load_simd_width_intel:
10162
return nir_imm_int(b, simd_width);
10164
case nir_intrinsic_load_subgroup_id:
10165
/* If the whole workgroup fits in one thread, we can lower subgroup_id
10166
* to a constant zero.
10168
if (!b->shader->info.workgroup_size_variable) {
10169
unsigned local_workgroup_size = b->shader->info.workgroup_size[0] *
10170
b->shader->info.workgroup_size[1] *
10171
b->shader->info.workgroup_size[2];
10172
if (local_workgroup_size <= simd_width)
10173
return nir_imm_int(b, 0);
10183
brw_nir_lower_simd(nir_shader *nir, unsigned dispatch_width)
10185
nir_shader_lower_instructions(nir, filter_simd, lower_simd,
10186
(void *)(uintptr_t)dispatch_width);
10190
brw_compile_cs(const struct brw_compiler *compiler,
10192
struct brw_compile_cs_params *params)
10194
const nir_shader *nir = params->nir;
10195
const struct brw_cs_prog_key *key = params->key;
10196
struct brw_cs_prog_data *prog_data = params->prog_data;
10198
const bool debug_enabled =
10199
INTEL_DEBUG(params->debug_flag ? params->debug_flag : DEBUG_CS);
10201
prog_data->base.stage = MESA_SHADER_COMPUTE;
10202
prog_data->base.total_shared = nir->info.shared_size;
10203
prog_data->base.ray_queries = nir->info.ray_queries;
10204
prog_data->base.total_scratch = 0;
10206
if (!nir->info.workgroup_size_variable) {
10207
prog_data->local_size[0] = nir->info.workgroup_size[0];
10208
prog_data->local_size[1] = nir->info.workgroup_size[1];
10209
prog_data->local_size[2] = nir->info.workgroup_size[2];
10212
const unsigned required_dispatch_width =
10213
brw_required_dispatch_width(&nir->info, key->base.subgroup_size_type);
10215
fs_visitor *v[3] = {0};
10216
const char *error[3] = {0};
10218
for (unsigned simd = 0; simd < 3; simd++) {
10219
if (!brw_simd_should_compile(mem_ctx, simd, compiler->devinfo, prog_data,
10220
required_dispatch_width, &error[simd]))
10223
const unsigned dispatch_width = 8u << simd;
10225
nir_shader *shader = nir_shader_clone(mem_ctx, nir);
10226
brw_nir_apply_key(shader, compiler, &key->base,
10227
dispatch_width, true /* is_scalar */);
10229
NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width);
10231
/* Clean up after the local index and ID calculations. */
10232
NIR_PASS_V(shader, nir_opt_constant_folding);
10233
NIR_PASS_V(shader, nir_opt_dce);
10235
brw_postprocess_nir(shader, compiler, true, debug_enabled,
10236
key->base.robust_buffer_access);
10238
v[simd] = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
10239
&prog_data->base, shader, dispatch_width,
10242
if (prog_data->prog_mask) {
10243
unsigned first = ffs(prog_data->prog_mask) - 1;
10244
v[simd]->import_uniforms(v[first]);
10247
const bool allow_spilling = !prog_data->prog_mask ||
10248
nir->info.workgroup_size_variable;
10250
if (v[simd]->run_cs(allow_spilling)) {
10251
/* We should always be able to do SIMD32 for compute shaders. */
10252
assert(v[simd]->max_dispatch_width >= 32);
10254
cs_fill_push_const_info(compiler->devinfo, prog_data);
10256
brw_simd_mark_compiled(simd, prog_data, v[simd]->spilled_any_registers);
10258
error[simd] = ralloc_strdup(mem_ctx, v[simd]->fail_msg);
10260
brw_shader_perf_log(compiler, params->log_data,
10261
"SIMD%u shader failed to compile: %s\n",
10262
dispatch_width, v[simd]->fail_msg);
10267
const int selected_simd = brw_simd_select(prog_data);
10268
if (selected_simd < 0) {
10269
params->error_str = ralloc_asprintf(mem_ctx, "Can't compile shader: %s, %s and %s.\n",
10270
error[0], error[1], error[2]);;
10274
assert(selected_simd < 3);
10275
fs_visitor *selected = v[selected_simd];
10277
if (!nir->info.workgroup_size_variable)
10278
prog_data->prog_mask = 1 << selected_simd;
10280
const unsigned *ret = NULL;
10282
fs_generator g(compiler, params->log_data, mem_ctx, &prog_data->base,
10283
selected->runtime_check_aads_emit, MESA_SHADER_COMPUTE);
10284
if (unlikely(debug_enabled)) {
10285
char *name = ralloc_asprintf(mem_ctx, "%s compute shader %s",
10287
nir->info.label : "unnamed",
10289
g.enable_debug(name);
10292
struct brw_compile_stats *stats = params->stats;
10293
for (unsigned simd = 0; simd < 3; simd++) {
10294
if (prog_data->prog_mask & (1u << simd)) {
10296
prog_data->prog_offset[simd] =
10297
g.generate_code(v[simd]->cfg, 8u << simd, v[simd]->shader_stats,
10298
v[simd]->performance_analysis.require(), stats);
10299
stats = stats ? stats + 1 : NULL;
10303
g.add_const_data(nir->constant_data, nir->constant_data_size);
10305
ret = g.get_assembly();
10314
struct brw_cs_dispatch_info
10315
brw_cs_get_dispatch_info(const struct intel_device_info *devinfo,
10316
const struct brw_cs_prog_data *prog_data,
10317
const unsigned *override_local_size)
10319
struct brw_cs_dispatch_info info = {};
10321
const unsigned *sizes =
10322
override_local_size ? override_local_size :
10323
prog_data->local_size;
10326
override_local_size ? brw_simd_select_for_workgroup_size(devinfo, prog_data, sizes) :
10327
brw_simd_select(prog_data);
10328
assert(simd >= 0 && simd < 3);
10330
info.group_size = sizes[0] * sizes[1] * sizes[2];
10331
info.simd_size = 8u << simd;
10332
info.threads = DIV_ROUND_UP(info.group_size, info.simd_size);
10334
const uint32_t remainder = info.group_size & (info.simd_size - 1);
10336
info.right_mask = ~0u >> (32 - remainder);
10338
info.right_mask = ~0u >> (32 - info.simd_size);
10344
compile_single_bs(const struct brw_compiler *compiler, void *log_data,
10346
const struct brw_bs_prog_key *key,
10347
struct brw_bs_prog_data *prog_data,
10348
nir_shader *shader,
10350
struct brw_compile_stats *stats,
10354
const bool debug_enabled = INTEL_DEBUG(DEBUG_RT);
10356
prog_data->base.stage = shader->info.stage;
10357
prog_data->max_stack_size = MAX2(prog_data->max_stack_size,
10358
shader->scratch_size);
10360
const unsigned max_dispatch_width = 16;
10361
brw_nir_apply_key(shader, compiler, &key->base, max_dispatch_width, true);
10362
brw_postprocess_nir(shader, compiler, true, debug_enabled,
10363
key->base.robust_buffer_access);
10365
fs_visitor *v = NULL, *v8 = NULL, *v16 = NULL;
10366
bool has_spilled = false;
10368
uint8_t simd_size = 0;
10369
if (!INTEL_DEBUG(DEBUG_NO8)) {
10370
v8 = new fs_visitor(compiler, log_data, mem_ctx, &key->base,
10371
&prog_data->base, shader,
10373
const bool allow_spilling = true;
10374
if (!v8->run_bs(allow_spilling)) {
10376
*error_str = ralloc_strdup(mem_ctx, v8->fail_msg);
10382
if (v8->spilled_any_registers)
10383
has_spilled = true;
10387
if (!has_spilled && !INTEL_DEBUG(DEBUG_NO16)) {
10388
v16 = new fs_visitor(compiler, log_data, mem_ctx, &key->base,
10389
&prog_data->base, shader,
10390
16, debug_enabled);
10391
const bool allow_spilling = (v == NULL);
10392
if (!v16->run_bs(allow_spilling)) {
10393
brw_shader_perf_log(compiler, log_data,
10394
"SIMD16 shader failed to compile: %s\n",
10397
assert(v8 == NULL);
10399
*error_str = ralloc_asprintf(
10400
mem_ctx, "SIMD8 disabled and couldn't generate SIMD16: %s",
10409
if (v16->spilled_any_registers)
10410
has_spilled = true;
10414
if (unlikely(v == NULL)) {
10415
assert(INTEL_DEBUG(DEBUG_NO8 | DEBUG_NO16));
10417
*error_str = ralloc_strdup(mem_ctx,
10418
"Cannot satisfy INTEL_DEBUG flags SIMD restrictions");
10425
int offset = g->generate_code(v->cfg, simd_size, v->shader_stats,
10426
v->performance_analysis.require(), stats);
10428
*prog_offset = offset;
10430
assert(offset == 0);
10439
brw_bsr(const struct intel_device_info *devinfo,
10440
uint32_t offset, uint8_t simd_size, uint8_t local_arg_offset)
10442
assert(offset % 64 == 0);
10443
assert(simd_size == 8 || simd_size == 16);
10444
assert(local_arg_offset % 8 == 0);
10447
SET_BITS(simd_size == 8, 4, 4) |
10448
SET_BITS(local_arg_offset / 8, 2, 0);
10452
brw_compile_bs(const struct brw_compiler *compiler,
10454
struct brw_compile_bs_params *params)
10456
nir_shader *shader = params->nir;
10457
struct brw_bs_prog_data *prog_data = params->prog_data;
10458
unsigned num_resume_shaders = params->num_resume_shaders;
10459
nir_shader **resume_shaders = params->resume_shaders;
10460
const bool debug_enabled = INTEL_DEBUG(DEBUG_RT);
10462
prog_data->base.stage = shader->info.stage;
10463
prog_data->base.ray_queries = shader->info.ray_queries;
10464
prog_data->base.total_scratch = 0;
10466
prog_data->max_stack_size = 0;
10468
fs_generator g(compiler, params->log_data, mem_ctx, &prog_data->base,
10469
false, shader->info.stage);
10470
if (unlikely(debug_enabled)) {
10471
char *name = ralloc_asprintf(mem_ctx, "%s %s shader %s",
10472
shader->info.label ?
10473
shader->info.label : "unnamed",
10474
gl_shader_stage_name(shader->info.stage),
10475
shader->info.name);
10476
g.enable_debug(name);
10479
prog_data->simd_size =
10480
compile_single_bs(compiler, params->log_data, mem_ctx,
10481
params->key, prog_data,
10482
shader, &g, params->stats, NULL, ¶ms->error_str);
10483
if (prog_data->simd_size == 0)
10486
uint64_t *resume_sbt = ralloc_array(mem_ctx, uint64_t, num_resume_shaders);
10487
for (unsigned i = 0; i < num_resume_shaders; i++) {
10488
if (INTEL_DEBUG(DEBUG_RT)) {
10489
char *name = ralloc_asprintf(mem_ctx, "%s %s resume(%u) shader %s",
10490
shader->info.label ?
10491
shader->info.label : "unnamed",
10492
gl_shader_stage_name(shader->info.stage),
10493
i, shader->info.name);
10494
g.enable_debug(name);
10497
/* TODO: Figure out shader stats etc. for resume shaders */
10499
uint8_t simd_size =
10500
compile_single_bs(compiler, params->log_data, mem_ctx, params->key,
10501
prog_data, resume_shaders[i], &g, NULL, &offset,
10502
¶ms->error_str);
10503
if (simd_size == 0)
10506
assert(offset > 0);
10507
resume_sbt[i] = brw_bsr(compiler->devinfo, offset, simd_size, 0);
10510
/* We only have one constant data so we want to make sure they're all the
10513
for (unsigned i = 0; i < num_resume_shaders; i++) {
10514
assert(resume_shaders[i]->constant_data_size ==
10515
shader->constant_data_size);
10516
assert(memcmp(resume_shaders[i]->constant_data,
10517
shader->constant_data,
10518
shader->constant_data_size) == 0);
10521
g.add_const_data(shader->constant_data, shader->constant_data_size);
10522
g.add_resume_sbt(num_resume_shaders, resume_sbt);
10524
return g.get_assembly();
10528
* Test the dispatch mask packing assumptions of
10529
* brw_stage_has_packed_dispatch(). Call this from e.g. the top of
10530
* fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
10531
* executed with an unexpected dispatch mask.
10534
brw_fs_test_dispatch_packing(const fs_builder &bld)
10536
const gl_shader_stage stage = bld.shader->stage;
10538
if (brw_stage_has_packed_dispatch(bld.shader->devinfo, stage,
10539
bld.shader->stage_prog_data)) {
10540
const fs_builder ubld = bld.exec_all().group(1, 0);
10541
const fs_reg tmp = component(bld.vgrf(BRW_REGISTER_TYPE_UD), 0);
10542
const fs_reg mask = (stage == MESA_SHADER_FRAGMENT ? brw_vmask_reg() :
10545
ubld.ADD(tmp, mask, brw_imm_ud(1));
10546
ubld.AND(tmp, mask, tmp);
10548
/* This will loop forever if the dispatch mask doesn't have the expected
10549
* form '2^n-1', in which case tmp will be non-zero.
10551
bld.emit(BRW_OPCODE_DO);
10552
bld.CMP(bld.null_reg_ud(), tmp, brw_imm_ud(0), BRW_CONDITIONAL_NZ);
10553
set_predicate(BRW_PREDICATE_NORMAL, bld.emit(BRW_OPCODE_WHILE));
10558
fs_visitor::workgroup_size() const
10560
assert(gl_shader_stage_uses_workgroup(stage));
10561
const struct brw_cs_prog_data *cs = brw_cs_prog_data(prog_data);
10562
return cs->local_size[0] * cs->local_size[1] * cs->local_size[2];
added
removed
src/intel/compiler/brw_fs.cpp
