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<?xml version="1.0" encoding="UTF-8"?>
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Copyright © 2020 Google, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice (including the next
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paragraph) shall be included in all copies or substantial portions of the
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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Cat4 Instructions: SFU (aka EFU) instructions
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<bitset name="#instruction-cat4" extends="#instruction">
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{SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {DST_HALF}{DST}, {SRC}
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<field name="SRC" low="0" high="15" type="#multisrc">
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<pattern low="16" high="31">xxxxxxxxxxxxxxxx</pattern>
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<field name="DST" low="32" high="39" type="#reg-gpr"/>
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<field name="REPEAT" low="40" high="41" type="#rptN"/>
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<field name="SAT" pos="42" type="bool" display="(sat)"/>
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<field name="SRC_R" pos="43" type="bool" display="(r)"/>
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<field name="SS" pos="44" type="bool" display="(ss)"/>
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<field name="UL" pos="45" type="bool" display="(ul)"/>
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<field name="DST_CONV" pos="46" type="bool">
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Destination register is opposite precision as source, ie.
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if {FULL} is true then destination is half precision, and
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<derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/>
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<pattern low="47" high="51">xxxxx</pattern>
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<field name="FULL" pos="52" type="bool">
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<doc>Full precision source registers</doc>
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<field name="JP" pos="59" type="bool" display="(jp)"/>
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<field name="SY" pos="60" type="bool" display="(sy)"/>
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<pattern low="61" high="63">100</pattern> <!-- cat4 -->
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<map name="SRC">src->srcs[0]</map>
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((src->dsts[0]->num >> 2) == 62) ? 0 :
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!!((src->srcs[0]->flags ^ src->dsts[0]->flags) & IR3_REG_HALF)
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<map name="FULL">!(src->srcs[0]->flags & IR3_REG_HALF)</map>
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<map name="SRC_R">!!(src->srcs[0]->flags & IR3_REG_R)</map>
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<bitset name="rcp" extends="#instruction-cat4">
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<pattern low="53" high="58">000000</pattern> <!-- OPC -->
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<bitset name="rsq" extends="#instruction-cat4">
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<pattern low="53" high="58">000001</pattern> <!-- OPC -->
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<bitset name="log2" extends="#instruction-cat4">
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<pattern low="53" high="58">000010</pattern> <!-- OPC -->
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<bitset name="exp2" extends="#instruction-cat4">
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<pattern low="53" high="58">000011</pattern> <!-- OPC -->
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<bitset name="sin" extends="#instruction-cat4">
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<pattern low="53" high="58">000100</pattern> <!-- OPC -->
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<bitset name="cos" extends="#instruction-cat4">
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<pattern low="53" high="58">000101</pattern> <!-- OPC -->
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<bitset name="sqrt" extends="#instruction-cat4">
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<pattern low="53" high="58">000110</pattern> <!-- OPC -->
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NOTE that these are 8+opc from their highp equivs, so it's possible
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that the high order bit in the opc field has been repurposed for
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half-precision use? But note that other ops (rcp/lsin/cos/sqrt)
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still use the same opc as highp
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<bitset name="hrsq" extends="#instruction-cat4">
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<pattern low="53" high="58">001001</pattern> <!-- OPC -->
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<bitset name="hlog2" extends="#instruction-cat4">
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<pattern low="53" high="58">001010</pattern> <!-- OPC -->
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<bitset name="hexp2" extends="#instruction-cat4">
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<pattern low="53" high="58">001011</pattern> <!-- OPC -->