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* Copyright (c) 2019 Zodiac Inflight Innovations
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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* Jonathan Marek <jonathan@marek.ca>
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#include "etnaviv_compiler_nir.h"
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#include "util/register_allocate.h"
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/* use "r63.z" for depth reg, it will wrap around to r0.z by reg_get_base
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* (fs registers are offset by 1 to avoid reserving r0)
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#define REG_FRAG_DEPTH ((ETNA_MAX_TEMPS - 1) * NUM_REG_TYPES + REG_TYPE_VIRT_SCALAR_Z)
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/* precomputed by register_allocate */
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static unsigned int *q_values[] = {
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(unsigned int[]) {1, 2, 3, 4, 2, 2, 3, },
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(unsigned int[]) {3, 5, 6, 6, 5, 5, 6, },
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(unsigned int[]) {3, 4, 4, 4, 4, 4, 4, },
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(unsigned int[]) {1, 1, 1, 1, 1, 1, 1, },
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(unsigned int[]) {1, 2, 2, 2, 1, 2, 2, },
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(unsigned int[]) {2, 3, 3, 3, 2, 3, 3, },
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(unsigned int[]) {2, 2, 2, 2, 2, 2, 2, },
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static inline int reg_get_class(int virt_reg)
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switch (reg_get_type(virt_reg)) {
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return REG_CLASS_VEC4;
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case REG_TYPE_VIRT_VEC3_XYZ:
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case REG_TYPE_VIRT_VEC3_XYW:
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case REG_TYPE_VIRT_VEC3_XZW:
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case REG_TYPE_VIRT_VEC3_YZW:
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return REG_CLASS_VIRT_VEC3;
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case REG_TYPE_VIRT_VEC2_XY:
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case REG_TYPE_VIRT_VEC2_XZ:
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case REG_TYPE_VIRT_VEC2_XW:
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case REG_TYPE_VIRT_VEC2_YZ:
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case REG_TYPE_VIRT_VEC2_YW:
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case REG_TYPE_VIRT_VEC2_ZW:
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return REG_CLASS_VIRT_VEC2;
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case REG_TYPE_VIRT_SCALAR_X:
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case REG_TYPE_VIRT_SCALAR_Y:
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case REG_TYPE_VIRT_SCALAR_Z:
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case REG_TYPE_VIRT_SCALAR_W:
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return REG_CLASS_VIRT_SCALAR;
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case REG_TYPE_VIRT_VEC2T_XY:
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case REG_TYPE_VIRT_VEC2T_ZW:
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return REG_CLASS_VIRT_VEC2T;
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case REG_TYPE_VIRT_VEC2C_XY:
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case REG_TYPE_VIRT_VEC2C_YZ:
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case REG_TYPE_VIRT_VEC2C_ZW:
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return REG_CLASS_VIRT_VEC2C;
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case REG_TYPE_VIRT_VEC3C_XYZ:
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case REG_TYPE_VIRT_VEC3C_YZW:
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return REG_CLASS_VIRT_VEC3C;
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etna_ra_setup(void *mem_ctx)
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struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, ETNA_MAX_TEMPS *
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NUM_REG_TYPES, false);
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/* classes always be created from index 0, so equal to the class enum
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* which represents a register with (c+1) components
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struct ra_class *classes[NUM_REG_CLASSES];
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for (int c = 0; c < NUM_REG_CLASSES; c++)
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classes[c] = ra_alloc_reg_class(regs);
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/* add each register of each class */
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for (int r = 0; r < NUM_REG_TYPES * ETNA_MAX_TEMPS; r++)
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ra_class_add_reg(classes[reg_get_class(r)], r);
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for (int r = 0; r < ETNA_MAX_TEMPS; r++) {
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for (int i = 0; i < NUM_REG_TYPES; i++) {
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for (int j = 0; j < i; j++) {
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if (reg_writemask[i] & reg_writemask[j]) {
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ra_add_reg_conflict(regs, NUM_REG_TYPES * r + i,
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NUM_REG_TYPES * r + j);
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ra_set_finalize(regs, q_values);
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etna_ra_assign(struct etna_compile *c, nir_shader *shader)
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struct etna_compiler *compiler = c->variant->shader->compiler;
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struct ra_regs *regs = compiler->regs;
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nir_function_impl *impl = nir_shader_get_entrypoint(shader);
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/* liveness and interference */
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nir_index_blocks(impl);
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nir_index_ssa_defs(impl);
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nir_foreach_block(block, impl) {
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nir_foreach_instr(instr, block)
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instr->pass_flags = 0;
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/* this gives an approximation/upper limit on how many nodes are needed
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* (some ssa values do not represent an allocated register)
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unsigned max_nodes = impl->ssa_alloc + impl->reg_alloc;
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unsigned *live_map = ralloc_array(NULL, unsigned, max_nodes);
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memset(live_map, 0xff, sizeof(unsigned) * max_nodes);
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struct live_def *defs = rzalloc_array(NULL, struct live_def, max_nodes);
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unsigned num_nodes = etna_live_defs(impl, defs, live_map);
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struct ra_graph *g = ra_alloc_interference_graph(regs, num_nodes);
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/* set classes from num_components */
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for (unsigned i = 0; i < num_nodes; i++) {
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nir_instr *instr = defs[i].instr;
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nir_dest *dest = defs[i].dest;
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unsigned comp = nir_dest_num_components(*dest) - 1;
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if (instr->type == nir_instr_type_alu &&
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c->specs->has_new_transcendentals) {
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switch (nir_instr_as_alu(instr)->op) {
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assert(dest->is_ssa);
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comp = REG_CLASS_VIRT_VEC2T;
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if (instr->type == nir_instr_type_intrinsic) {
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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/* can't have dst swizzle or sparse writemask on UBO loads */
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if (intr->intrinsic == nir_intrinsic_load_ubo) {
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assert(dest == &intr->dest);
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if (dest->ssa.num_components == 2)
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comp = REG_CLASS_VIRT_VEC2C;
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if (dest->ssa.num_components == 3)
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comp = REG_CLASS_VIRT_VEC3C;
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ra_set_node_class(g, i, ra_get_class_from_index(regs, comp));
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nir_foreach_block(block, impl) {
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nir_foreach_instr(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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nir_dest *dest = dest_for_instr(instr);
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_store_deref: {
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/* don't want outputs to be swizzled
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* TODO: better would be to set the type to X/XY/XYZ/XYZW
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* TODO: what if fragcoord.z is read after writing fragdepth?
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nir_deref_instr *deref = nir_src_as_deref(intr->src[0]);
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unsigned index = live_map[src_index(impl, &intr->src[1])];
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if (shader->info.stage == MESA_SHADER_FRAGMENT &&
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deref->var->data.location == FRAG_RESULT_DEPTH) {
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ra_set_node_reg(g, index, REG_FRAG_DEPTH);
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ra_set_node_class(g, index, ra_get_class_from_index(regs, REG_CLASS_VEC4));
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case nir_intrinsic_load_input:
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reg = nir_intrinsic_base(intr) * NUM_REG_TYPES + (unsigned[]) {
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REG_TYPE_VIRT_SCALAR_X,
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REG_TYPE_VIRT_VEC2_XY,
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REG_TYPE_VIRT_VEC3_XYZ,
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}[nir_dest_num_components(*dest) - 1];
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case nir_intrinsic_load_instance_id:
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reg = c->variant->infile.num_reg * NUM_REG_TYPES + REG_TYPE_VIRT_SCALAR_Y;
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ra_set_node_reg(g, live_map[dest_index(impl, dest)], reg);
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/* add interference for intersecting live ranges */
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for (unsigned i = 0; i < num_nodes; i++) {
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assert(defs[i].live_start < defs[i].live_end);
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for (unsigned j = 0; j < i; j++) {
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if (defs[i].live_start >= defs[j].live_end || defs[j].live_start >= defs[i].live_end)
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ra_add_node_interference(g, i, j);
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/* Allocate registers */
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ASSERTED bool ok = ra_allocate(g);
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c->live_map = live_map;
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c->num_nodes = num_nodes;
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etna_ra_finish(struct etna_compile *c)
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/* TODO: better way to get number of registers used? */
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for (unsigned i = 0; i < c->num_nodes; i++) {
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j = MAX2(j, reg_get_base(c, ra_get_node_reg(c->g, i)) + 1);
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ralloc_free(c->live_map);