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Viewing changes to src/freedreno/registers/adreno/ocmem.xml

  • Committer: mmach
  • Date: 2022-09-22 19:56:13 UTC
  • Revision ID: netbit73@gmail.com-20220922195613-wtik9mmy20tmor0i
2022-09-22 21:17:09

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src/freedreno/registers/adreno/ocmem.xml
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<?xml version="1.0" encoding="UTF-8"?>
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<database xmlns="http://nouveau.freedesktop.org/"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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<import file="freedreno_copyright.xml"/>
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<domain name="OCMEM" width="32">
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        <enum name="ocmem_macro_state">
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                <value name="PASSTHROUGH" value="0"/>
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                <value name="PERI_ON" value="1"/>
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                <value name="CORE_ON" value="2"/>
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                <value name="CLK_OFF" value="4"/>
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        </enum>
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        <reg32 offset="0x00" name="HW_VERSION"/>
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        <reg32 offset="0x04" name="HW_PROFILE">
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                <bitfield name="NUM_PORTS" low="0" high="3" type="uint"/>
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                <bitfield name="NUM_MACROS" low="8" high="13" type="uint"/>
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                <bitfield name="LAST_REGN_HALFSIZE" pos="16" type="boolean"/>
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                <bitfield name="INTERLEAVING" pos="17" type="boolean"/>
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        </reg32>
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        <reg32 offset="0x0c" name="GEN_STATUS"/>
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        <reg32 offset="0x38" name="PSGSC_STATUS"/>
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        <!-- length is 4 for 8084, 3 for 8974/8092, 1 for 8226: -->
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        <array offset="0x3c" name="PSGSC" stride="1" length="4">
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                <reg32 offset="0x0" name="CTL">
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                        <bitfield name="MACRO0_MODE" low="0"  high="2"  type="ocmem_macro_state"/>
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                        <bitfield name="MACRO1_MODE" low="4"  high="6"  type="ocmem_macro_state"/>
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                        <bitfield name="MACRO2_MODE" low="8"  high="10" type="ocmem_macro_state"/>
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                        <bitfield name="MACRO3_MODE" low="12" high="14" type="ocmem_macro_state"/>
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                </reg32>
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        </array>
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        <reg32 offset="0x1000" name="REGION_MODE_CTL">
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                <bitfield name="REG0_THIN" pos="0" type="boolean"/>
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                <bitfield name="REG1_THIN" pos="1" type="boolean"/>
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                <bitfield name="REG2_THIN" pos="2" type="boolean"/>
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                <bitfield name="REG3_THIN" pos="3" type="boolean"/>
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        </reg32>
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        <reg32 offset="0x1004" name="GFX_MPU_START"/>
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        <reg32 offset="0x1008" name="GFX_MPU_END"/>
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</domain>
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</database>