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* Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
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* Copyright © 2018 Google, Inc.
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* Rob Clark <robclark@freedesktop.org>
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#include "pipe/p_state.h"
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#include "util/bitset.h"
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#include "util/format/u_format.h"
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#include "util/u_inlines.h"
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#include "util/u_memory.h"
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#include "util/u_string.h"
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#include "freedreno_program.h"
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#include "fd6_const.h"
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#include "fd6_format.h"
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#include "fd6_program.h"
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#include "fd6_texture.h"
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fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
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const struct ir3_shader_variant *so)
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enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
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uint32_t first_exec_offset = 0;
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uint32_t instrlen = 0;
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uint32_t hw_stack_offset = 0;
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case MESA_SHADER_VERTEX:
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first_exec_offset = REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET;
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instrlen = REG_A6XX_SP_VS_INSTRLEN;
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hw_stack_offset = REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET;
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case MESA_SHADER_TESS_CTRL:
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first_exec_offset = REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET;
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instrlen = REG_A6XX_SP_HS_INSTRLEN;
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hw_stack_offset = REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET;
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case MESA_SHADER_TESS_EVAL:
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first_exec_offset = REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET;
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instrlen = REG_A6XX_SP_DS_INSTRLEN;
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hw_stack_offset = REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET;
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case MESA_SHADER_GEOMETRY:
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first_exec_offset = REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET;
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instrlen = REG_A6XX_SP_GS_INSTRLEN;
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hw_stack_offset = REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET;
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case MESA_SHADER_FRAGMENT:
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first_exec_offset = REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET;
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instrlen = REG_A6XX_SP_FS_INSTRLEN;
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hw_stack_offset = REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET;
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case MESA_SHADER_COMPUTE:
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case MESA_SHADER_KERNEL:
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first_exec_offset = REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET;
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instrlen = REG_A6XX_SP_CS_INSTRLEN;
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hw_stack_offset = REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET;
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case MESA_SHADER_TASK:
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case MESA_SHADER_MESH:
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case MESA_SHADER_RAYGEN:
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case MESA_SHADER_ANY_HIT:
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case MESA_SHADER_CLOSEST_HIT:
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case MESA_SHADER_MISS:
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case MESA_SHADER_INTERSECTION:
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case MESA_SHADER_CALLABLE:
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unreachable("Unsupported shader stage");
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case MESA_SHADER_NONE:
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/* Name should generally match what you get with MESA_SHADER_CAPTURE_PATH: */
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const char *name = so->shader->nir->info.name;
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fd_emit_string5(ring, name, strlen(name));
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uint32_t fibers_per_sp = ctx->screen->info->a6xx.fibers_per_sp;
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uint32_t num_sp_cores = ctx->screen->info->num_sp_cores;
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uint32_t per_fiber_size = ALIGN(so->pvtmem_size, 512);
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if (per_fiber_size > ctx->pvtmem[so->pvtmem_per_wave].per_fiber_size) {
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if (ctx->pvtmem[so->pvtmem_per_wave].bo)
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fd_bo_del(ctx->pvtmem[so->pvtmem_per_wave].bo);
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ctx->pvtmem[so->pvtmem_per_wave].per_fiber_size = per_fiber_size;
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uint32_t total_size =
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ALIGN(per_fiber_size * fibers_per_sp, 1 << 12) * num_sp_cores;
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ctx->pvtmem[so->pvtmem_per_wave].bo = fd_bo_new(
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ctx->screen->dev, total_size, 0,
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"pvtmem_%s_%d", so->pvtmem_per_wave ? "per_wave" : "per_fiber",
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per_fiber_size = ctx->pvtmem[so->pvtmem_per_wave].per_fiber_size;
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uint32_t per_sp_size = ALIGN(per_fiber_size * fibers_per_sp, 1 << 12);
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OUT_PKT4(ring, instrlen, 1);
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OUT_RING(ring, so->instrlen);
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OUT_PKT4(ring, first_exec_offset, 7);
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OUT_RING(ring, 0); /* SP_xS_OBJ_FIRST_EXEC_OFFSET */
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OUT_RELOC(ring, so->bo, 0, 0, 0); /* SP_xS_OBJ_START_LO */
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OUT_RING(ring, A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(per_fiber_size));
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if (so->pvtmem_size > 0) { /* SP_xS_PVT_MEM_ADDR */
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OUT_RELOC(ring, ctx->pvtmem[so->pvtmem_per_wave].bo, 0, 0, 0);
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OUT_RING(ring, A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(per_sp_size) |
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COND(so->pvtmem_per_wave,
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A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT));
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OUT_PKT4(ring, hw_stack_offset, 1);
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OUT_RING(ring, A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(per_sp_size));
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uint32_t shader_preload_size =
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MIN2(so->instrlen, ctx->screen->info->a6xx.instr_cache_size);
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OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
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OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
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CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
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CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
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CP_LOAD_STATE6_0_NUM_UNIT(shader_preload_size));
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OUT_RELOC(ring, so->bo, 0, 0, 0);
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* Build a pre-baked state-obj to disable SO, so that we aren't dynamically
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* building this at draw time whenever we transition from SO enabled->disabled
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setup_stream_out_disable(struct fd_context *ctx)
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if (ctx->screen->info->a6xx.tess_use_shared)
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struct fd_ringbuffer *ring =
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fd_ringbuffer_new_object(ctx->pipe, (1 + sizedw) * 4);
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OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, sizedw);
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OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
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OUT_RING(ring, REG_A6XX_VPC_SO_STREAM_CNTL);
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if (ctx->screen->info->a6xx.tess_use_shared) {
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OUT_RING(ring, REG_A6XX_PC_SO_STREAM_CNTL);
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fd6_context(ctx)->streamout_disable_stateobj = ring;
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setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
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const struct ir3_shader_variant *v,
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struct ir3_shader_linkage *l)
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const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
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/* Note: 64 here comes from the HW layout of the program RAM. The program
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* for stream N is at DWORD 64 * N.
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#define A6XX_SO_PROG_DWORDS 64
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uint32_t prog[A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS] = {};
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BITSET_DECLARE(valid_dwords, A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS) = {0};
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uint32_t ncomp[PIPE_MAX_SO_BUFFERS];
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memset(ncomp, 0, sizeof(ncomp));
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memset(prog, 0, sizeof(prog));
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for (unsigned i = 0; i < strmout->num_outputs; i++) {
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const struct ir3_stream_output *out = &strmout->output[i];
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unsigned k = out->register_index;
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ncomp[out->output_buffer] += out->num_components;
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/* linkage map sorted by order frag shader wants things, so
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* a bit less ideal here..
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for (idx = 0; idx < l->cnt; idx++)
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if (l->var[idx].slot == v->outputs[k].slot)
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debug_assert(idx < l->cnt);
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for (unsigned j = 0; j < out->num_components; j++) {
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unsigned c = j + out->start_component;
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unsigned loc = l->var[idx].loc + c;
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unsigned off = j + out->dst_offset; /* in dwords */
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unsigned dword = out->stream * A6XX_SO_PROG_DWORDS + loc/2;
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prog[dword] |= A6XX_VPC_SO_PROG_B_EN |
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A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
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A6XX_VPC_SO_PROG_B_OFF(off * 4);
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prog[dword] |= A6XX_VPC_SO_PROG_A_EN |
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A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
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A6XX_VPC_SO_PROG_A_OFF(off * 4);
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BITSET_SET(valid_dwords, dword);
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unsigned prog_count = 0;
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BITSET_FOREACH_RANGE (start, end, valid_dwords,
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A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS) {
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prog_count += end - start + 1;
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unsigned sizedw = 10 + (2 * prog_count);
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if (ctx->screen->info->a6xx.tess_use_shared)
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struct fd_ringbuffer *ring =
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fd_ringbuffer_new_object(ctx->pipe, (1 + sizedw) * 4);
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OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, sizedw);
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OUT_RING(ring, REG_A6XX_VPC_SO_STREAM_CNTL);
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A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(0x1) |
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COND(ncomp[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) |
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COND(ncomp[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) |
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COND(ncomp[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) |
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COND(ncomp[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1)));
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OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
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OUT_RING(ring, ncomp[0]);
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OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
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OUT_RING(ring, ncomp[1]);
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OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
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OUT_RING(ring, ncomp[2]);
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OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
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OUT_RING(ring, ncomp[3]);
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BITSET_FOREACH_RANGE (start, end, valid_dwords,
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A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS) {
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OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
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OUT_RING(ring, COND(first, A6XX_VPC_SO_CNTL_RESET) |
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A6XX_VPC_SO_CNTL_ADDR(start));
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for (unsigned i = start; i < end; i++) {
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OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
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OUT_RING(ring, prog[i]);
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if (ctx->screen->info->a6xx.tess_use_shared) {
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/* Possibly not tess_use_shared related, but the combination of
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* tess + xfb fails some tests if we don't emit this.
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OUT_RING(ring, REG_A6XX_PC_SO_STREAM_CNTL);
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OUT_RING(ring, A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE);
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state->streamout_stateobj = ring;
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setup_config_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
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struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 100 * 4);
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OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true,
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.ds_state = true, .gs_state = true,
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.fs_state = true, .cs_state = true,
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.gfx_ibo = true, .cs_ibo = true, ));
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debug_assert(state->vs->constlen >= state->bs->constlen);
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OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
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OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) |
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A6XX_HLSQ_VS_CNTL_ENABLED);
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OUT_RING(ring, COND(state->hs,
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A6XX_HLSQ_HS_CNTL_ENABLED |
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A6XX_HLSQ_HS_CNTL_CONSTLEN(state->hs->constlen)));
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OUT_RING(ring, COND(state->ds,
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A6XX_HLSQ_DS_CNTL_ENABLED |
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A6XX_HLSQ_DS_CNTL_CONSTLEN(state->ds->constlen)));
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OUT_RING(ring, COND(state->gs,
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A6XX_HLSQ_GS_CNTL_ENABLED |
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A6XX_HLSQ_GS_CNTL_CONSTLEN(state->gs->constlen)));
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OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
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OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(state->fs->constlen) |
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A6XX_HLSQ_FS_CNTL_ENABLED);
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OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
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OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
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A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(state->vs)) |
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A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
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A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
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OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
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OUT_RING(ring, COND(state->hs,
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A6XX_SP_HS_CONFIG_ENABLED |
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A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state->hs)) |
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A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
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A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
336
OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
337
OUT_RING(ring, COND(state->ds,
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A6XX_SP_DS_CONFIG_ENABLED |
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A6XX_SP_DS_CONFIG_NIBO(ir3_shader_nibo(state->ds)) |
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A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
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A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
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OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
344
OUT_RING(ring, COND(state->gs,
345
A6XX_SP_GS_CONFIG_ENABLED |
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A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(state->gs)) |
347
A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
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A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
350
OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
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OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
352
A6XX_SP_FS_CONFIG_NIBO(ir3_shader_nibo(state->fs)) |
353
A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
354
A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
356
OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
357
OUT_RING(ring, ir3_shader_nibo(state->fs));
359
state->config_stateobj = ring;
362
static inline uint32_t
363
next_regid(uint32_t reg, uint32_t increment)
366
return reg + increment;
372
fd6_emit_tess_bos(struct fd_screen *screen, struct fd_ringbuffer *ring,
373
const struct ir3_shader_variant *s) assert_dt
375
const struct ir3_const_state *const_state = ir3_const_state(s);
376
const unsigned regid = const_state->offsets.primitive_param + 1;
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if (regid >= s->constlen)
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OUT_PKT7(ring, fd6_stage2opcode(s->type), 7);
383
OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid) |
384
CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
385
CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
386
CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(s->type)) |
387
CP_LOAD_STATE6_0_NUM_UNIT(dwords / 4));
390
OUT_RELOC(ring, screen->tess_bo, FD6_TESS_FACTOR_SIZE, 0, 0);
391
OUT_RELOC(ring, screen->tess_bo, 0, 0, 0);
395
setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
396
struct fd6_program_state *state,
397
const struct ir3_cache_key *cache_key,
398
bool binning_pass) assert_dt
400
const struct ir3_shader_key *key = &cache_key->key;
401
uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
402
uint32_t clip0_regid, clip1_regid;
403
uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
404
uint32_t smask_in_regid, smask_regid;
405
uint32_t stencilref_regid;
406
uint32_t vertex_regid, instance_regid, layer_regid, vs_primitive_regid;
407
uint32_t hs_invocation_regid;
408
uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_rel_patch_regid,
409
ds_rel_patch_regid, ds_primitive_regid;
410
uint32_t ij_regid[IJ_COUNT];
411
uint32_t gs_header_regid;
412
enum a6xx_threadsize fssz;
413
uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
414
uint8_t clip0_loc, clip1_loc;
417
static const struct ir3_shader_variant dummy_fs = {0};
418
const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
419
const struct ir3_shader_variant *hs = state->hs;
420
const struct ir3_shader_variant *ds = state->ds;
421
const struct ir3_shader_variant *gs = state->gs;
422
const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
424
/* binning VS is wrong when GS is present, so use nonbinning VS
425
* TODO: compile both binning VS/GS variants correctly
427
if (binning_pass && state->gs)
430
bool sample_shading = fs->per_samp | key->sample_shading;
432
fssz = fs->info.double_threadsize ? THREAD128 : THREAD64;
434
pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
435
psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
436
clip0_regid = ir3_find_output_regid(vs, VARYING_SLOT_CLIP_DIST0);
437
clip1_regid = ir3_find_output_regid(vs, VARYING_SLOT_CLIP_DIST1);
438
layer_regid = ir3_find_output_regid(vs, VARYING_SLOT_LAYER);
439
vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
440
instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
442
vs_primitive_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
444
vs_primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
446
vs_primitive_regid = regid(63, 0);
448
bool hs_reads_primid = false, ds_reads_primid = false;
450
tess_coord_x_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD);
451
tess_coord_y_regid = next_regid(tess_coord_x_regid, 1);
452
hs_reads_primid = VALIDREG(ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID));
453
ds_reads_primid = VALIDREG(ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID));
454
hs_rel_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_REL_PATCH_ID_IR3);
455
ds_rel_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_REL_PATCH_ID_IR3);
456
ds_primitive_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
457
hs_invocation_regid =
458
ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
460
pos_regid = ir3_find_output_regid(ds, VARYING_SLOT_POS);
461
psize_regid = ir3_find_output_regid(ds, VARYING_SLOT_PSIZ);
462
clip0_regid = ir3_find_output_regid(ds, VARYING_SLOT_CLIP_DIST0);
463
clip1_regid = ir3_find_output_regid(ds, VARYING_SLOT_CLIP_DIST1);
465
tess_coord_x_regid = regid(63, 0);
466
tess_coord_y_regid = regid(63, 0);
467
hs_rel_patch_regid = regid(63, 0);
468
ds_rel_patch_regid = regid(63, 0);
469
ds_primitive_regid = regid(63, 0);
470
hs_invocation_regid = regid(63, 0);
473
bool gs_reads_primid = false;
475
gs_header_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3);
476
gs_reads_primid = VALIDREG(ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID));
477
pos_regid = ir3_find_output_regid(gs, VARYING_SLOT_POS);
478
psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
479
clip0_regid = ir3_find_output_regid(gs, VARYING_SLOT_CLIP_DIST0);
480
clip1_regid = ir3_find_output_regid(gs, VARYING_SLOT_CLIP_DIST1);
481
layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
483
gs_header_regid = regid(63, 0);
486
if (fs->color0_mrt) {
487
color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
488
color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
489
ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
491
color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
492
color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
493
color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
494
color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
495
color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
496
color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
497
color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
498
color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
501
samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
502
smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
503
face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
504
coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
505
zwcoord_regid = next_regid(coord_regid, 2);
506
posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
507
smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
508
stencilref_regid = ir3_find_output_regid(fs, FRAG_RESULT_STENCIL);
509
for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
511
ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
513
/* If we have pre-dispatch texture fetches, then ij_pix should not
514
* be DCE'd, even if not actually used in the shader itself:
516
if (fs->num_sampler_prefetch > 0) {
517
assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
518
/* also, it seems like ij_pix is *required* to be r0.x */
519
assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
522
/* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
523
* end up masking the single sample!!
526
smask_regid = regid(63, 0);
528
/* we could probably divide this up into things that need to be
529
* emitted if frag-prog is dirty vs if vert-prog is dirty..
532
OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
533
OUT_RING(ring, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
534
A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
536
for (int i = 0; i < fs->num_sampler_prefetch; i++) {
537
const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
539
A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
540
A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
541
A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
542
A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
543
A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
544
COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
545
A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
548
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
551
OUT_PKT4(ring, REG_A6XX_SP_MODE_CONTROL, 1);
552
OUT_RING(ring, A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
554
bool fs_has_dual_src_color =
555
!binning_pass && fs->shader->nir->info.fs.color_is_dual_source;
557
OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
559
A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
560
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
561
A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid) |
562
COND(fs_has_dual_src_color,
563
A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
565
OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
568
A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
569
A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vs->info.max_half_reg + 1) |
570
COND(vs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
571
A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(vs)));
573
fd6_emit_shader(ctx, ring, vs);
574
fd6_emit_immediates(ctx->screen, vs, ring);
576
fd6_emit_tess_bos(ctx->screen, ring, hs);
577
fd6_emit_tess_bos(ctx->screen, ring, ds);
580
struct ir3_shader_linkage l = {0};
581
const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
583
bool do_streamout = (last_shader->shader->stream_output.num_outputs > 0);
584
uint8_t clip_mask = last_shader->clip_mask,
585
cull_mask = last_shader->cull_mask;
586
uint8_t clip_cull_mask = clip_mask | cull_mask;
588
clip_mask &= cache_key->clip_plane_enable;
590
/* If we have streamout, link against the real FS, rather than the
591
* dummy FS used for binning pass state, to ensure the OUTLOC's
592
* match. Depending on whether we end up doing sysmem or gmem,
593
* the actual streamout could happen with either the binning pass
594
* or draw pass program, but the same streamout stateobj is used
597
ir3_link_shaders(&l, last_shader, do_streamout ? state->fs : fs, true);
599
bool primid_passthru = l.primid_loc != 0xff;
600
clip0_loc = l.clip0_loc;
601
clip1_loc = l.clip1_loc;
603
OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
604
OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
605
OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
606
OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
607
OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
609
/* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
610
ir3_link_stream_out(&l, last_shader);
612
if (VALIDREG(layer_regid)) {
613
layer_loc = l.max_loc;
614
ir3_link_add(&l, VARYING_SLOT_LAYER, layer_regid, 0x1, l.max_loc);
617
if (VALIDREG(pos_regid)) {
619
ir3_link_add(&l, VARYING_SLOT_POS, pos_regid, 0xf, l.max_loc);
622
if (VALIDREG(psize_regid)) {
623
psize_loc = l.max_loc;
624
ir3_link_add(&l, VARYING_SLOT_PSIZ, psize_regid, 0x1, l.max_loc);
627
/* Handle the case where clip/cull distances aren't read by the FS. Make
628
* sure to avoid adding an output with an empty writemask if the user
629
* disables all the clip distances in the API so that the slot is unused.
631
if (clip0_loc == 0xff && VALIDREG(clip0_regid) &&
632
(clip_cull_mask & 0xf) != 0) {
633
clip0_loc = l.max_loc;
634
ir3_link_add(&l, VARYING_SLOT_CLIP_DIST0, clip0_regid,
635
clip_cull_mask & 0xf, l.max_loc);
638
if (clip1_loc == 0xff && VALIDREG(clip1_regid) &&
639
(clip_cull_mask >> 4) != 0) {
640
clip1_loc = l.max_loc;
641
ir3_link_add(&l, VARYING_SLOT_CLIP_DIST1, clip1_regid,
642
clip_cull_mask >> 4, l.max_loc);
645
/* If we have stream-out, we use the full shader for binning
646
* pass, rather than the optimized binning pass one, so that we
647
* have all the varying outputs available for xfb. So streamout
648
* state should always be derived from the non-binning pass
651
if (do_streamout && !binning_pass) {
652
setup_stream_out(ctx, state, last_shader, &l);
654
if (!fd6_context(ctx)->streamout_disable_stateobj)
655
setup_stream_out_disable(ctx);
658
debug_assert(l.cnt <= 32);
660
OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
662
OUT_PKT4(ring, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
664
OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
666
for (j = 0; j < l.cnt;) {
669
reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
670
reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
673
reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
674
reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
681
OUT_PKT4(ring, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
683
OUT_PKT4(ring, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
685
OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
687
for (j = 0; j < l.cnt;) {
690
reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
691
reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
692
reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
693
reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
699
assert(vs->mergedregs == hs->mergedregs);
700
OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
703
A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) |
704
A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(hs->info.max_half_reg + 1) |
705
A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(hs)));
707
fd6_emit_shader(ctx, ring, hs);
708
fd6_emit_immediates(ctx->screen, hs, ring);
709
fd6_emit_link_map(ctx->screen, vs, hs, ring);
711
OUT_PKT4(ring, REG_A6XX_SP_DS_CTRL_REG0, 1);
714
A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
715
A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(ds->info.max_half_reg + 1) |
716
A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(ds)));
718
fd6_emit_shader(ctx, ring, ds);
719
fd6_emit_immediates(ctx->screen, ds, ring);
720
fd6_emit_link_map(ctx->screen, hs, ds, ring);
722
shader_info *hs_info = &hs->shader->nir->info;
723
OUT_PKT4(ring, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
724
OUT_RING(ring, hs_info->tess.tcs_vertices_out);
726
if (ctx->screen->info->a6xx.tess_use_shared) {
727
unsigned hs_input_size = 6 + (3 * (vs->output_size - 1));
728
unsigned wave_input_size =
729
MIN2(64, DIV_ROUND_UP(hs_input_size * 4,
730
hs_info->tess.tcs_vertices_out));
732
OUT_PKT4(ring, REG_A6XX_PC_HS_INPUT_SIZE, 1);
733
OUT_RING(ring, hs_input_size);
735
OUT_PKT4(ring, REG_A6XX_SP_HS_WAVE_INPUT_SIZE, 1);
736
OUT_RING(ring, wave_input_size);
738
uint32_t hs_input_size =
739
hs_info->tess.tcs_vertices_out * vs->output_size / 4;
741
/* Total attribute slots in HS incoming patch. */
742
OUT_PKT4(ring, REG_A6XX_PC_HS_INPUT_SIZE, 1);
743
OUT_RING(ring, hs_input_size);
745
const uint32_t wavesize = 64;
746
const uint32_t max_wave_input_size = 64;
747
const uint32_t patch_control_points = hs_info->tess.tcs_vertices_out;
749
/* note: if HS is really just the VS extended, then this
750
* should be by MAX2(patch_control_points, hs_info->tess.tcs_vertices_out)
751
* however that doesn't match the blob, and fails some dEQP tests.
753
uint32_t prims_per_wave = wavesize / hs_info->tess.tcs_vertices_out;
754
uint32_t max_prims_per_wave = max_wave_input_size * wavesize /
755
(vs->output_size * patch_control_points);
756
prims_per_wave = MIN2(prims_per_wave, max_prims_per_wave);
758
uint32_t total_size =
759
vs->output_size * patch_control_points * prims_per_wave;
760
uint32_t wave_input_size = DIV_ROUND_UP(total_size, wavesize);
762
OUT_PKT4(ring, REG_A6XX_SP_HS_WAVE_INPUT_SIZE, 1);
763
OUT_RING(ring, wave_input_size);
766
shader_info *ds_info = &ds->shader->nir->info;
767
OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
769
if (ds_info->tess.point_mode)
770
output = TESS_POINTS;
771
else if (ds_info->tess._primitive_mode == TESS_PRIMITIVE_ISOLINES)
773
else if (ds_info->tess.ccw)
774
output = TESS_CCW_TRIS;
776
output = TESS_CW_TRIS;
778
OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(
779
fd6_gl2spacing(ds_info->tess.spacing)) |
780
A6XX_PC_TESS_CNTL_OUTPUT(output));
782
OUT_PKT4(ring, REG_A6XX_VPC_DS_CLIP_CNTL, 1);
783
OUT_RING(ring, A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
784
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
785
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
787
OUT_PKT4(ring, REG_A6XX_VPC_DS_LAYER_CNTL, 1);
788
OUT_RING(ring, 0x0000ffff);
790
OUT_PKT4(ring, REG_A6XX_GRAS_DS_LAYER_CNTL, 1);
793
OUT_PKT4(ring, REG_A6XX_GRAS_DS_CL_CNTL, 1);
794
OUT_RING(ring, A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(clip_mask) |
795
A6XX_GRAS_DS_CL_CNTL_CULL_MASK(cull_mask));
797
OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
798
OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
799
A6XX_VPC_VS_PACK_PSIZELOC(255) |
800
A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
802
OUT_PKT4(ring, REG_A6XX_VPC_DS_PACK, 1);
803
OUT_RING(ring, A6XX_VPC_DS_PACK_POSITIONLOC(pos_loc) |
804
A6XX_VPC_DS_PACK_PSIZELOC(psize_loc) |
805
A6XX_VPC_DS_PACK_STRIDE_IN_VPC(l.max_loc));
807
OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
808
OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_OUT(l.cnt));
810
OUT_PKT4(ring, REG_A6XX_PC_DS_OUT_CNTL, 1);
811
OUT_RING(ring, A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
812
CONDREG(psize_regid, A6XX_PC_DS_OUT_CNTL_PSIZE) |
813
COND(ds_reads_primid, A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID) |
814
A6XX_PC_DS_OUT_CNTL_CLIP_MASK(clip_cull_mask));
816
OUT_PKT4(ring, REG_A6XX_PC_HS_OUT_CNTL, 1);
817
OUT_RING(ring, COND(hs_reads_primid, A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID));
819
OUT_PKT4(ring, REG_A6XX_SP_HS_WAVE_INPUT_SIZE, 1);
823
OUT_PKT4(ring, REG_A6XX_SP_VS_PRIMITIVE_CNTL, 1);
824
OUT_RING(ring, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(l.cnt));
826
bool enable_varyings = fs->total_in > 0;
828
OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
829
OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
830
COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
831
A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
832
A6XX_VPC_CNTL_0_VIEWIDLOC(0xff));
834
OUT_PKT4(ring, REG_A6XX_PC_VS_OUT_CNTL, 1);
835
OUT_RING(ring, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
836
CONDREG(psize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
837
CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
838
A6XX_PC_VS_OUT_CNTL_CLIP_MASK(clip_cull_mask));
840
OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
841
OUT_RING(ring, 0x7); /* XXX */
842
OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
843
A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
844
A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
845
A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
848
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
849
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
850
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(
851
ij_regid[IJ_PERSP_CENTROID]) |
852
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(
853
ij_regid[IJ_LINEAR_CENTROID]));
856
A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
857
A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
858
A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
859
A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
860
OUT_RING(ring, 0xfcfc); /* line length (?), foveation quality */
862
OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL_0, 1);
863
OUT_RING(ring, A6XX_HLSQ_FS_CNTL_0_THREADSIZE(fssz) |
864
COND(enable_varyings, A6XX_HLSQ_FS_CNTL_0_VARYINGS));
866
OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
869
A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
870
COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) | 0x1000000 |
871
A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
872
A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fs->info.max_half_reg + 1) |
873
COND(fs->mergedregs, A6XX_SP_FS_CTRL_REG0_MERGEDREGS) |
874
A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(fs)) |
875
COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
877
OUT_PKT4(ring, REG_A6XX_VPC_VS_LAYER_CNTL, 1);
878
OUT_RING(ring, A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(layer_loc) |
879
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(0xff));
881
bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
882
bool need_size_persamp = false;
883
if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
885
need_size_persamp = true;
890
OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
893
CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
894
CONDREG(ij_regid[IJ_PERSP_CENTROID],
895
A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
896
CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
897
CONDREG(ij_regid[IJ_LINEAR_PIXEL], A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
898
CONDREG(ij_regid[IJ_LINEAR_CENTROID],
899
A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID) |
900
CONDREG(ij_regid[IJ_LINEAR_SAMPLE], A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
901
COND(need_size, A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
902
COND(need_size_persamp, A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
903
COND(fs->fragcoord_compmask != 0,
904
A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
906
OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
909
CONDREG(ij_regid[IJ_PERSP_PIXEL],
910
A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
911
CONDREG(ij_regid[IJ_PERSP_CENTROID],
912
A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
913
CONDREG(ij_regid[IJ_PERSP_SAMPLE],
914
A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
915
CONDREG(ij_regid[IJ_LINEAR_PIXEL],
916
A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
917
CONDREG(ij_regid[IJ_LINEAR_CENTROID],
918
A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID) |
919
CONDREG(ij_regid[IJ_LINEAR_SAMPLE],
920
A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
921
COND(need_size, A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
922
COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
923
COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
924
COND(fs->fragcoord_compmask != 0,
925
A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
928
CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
929
CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
930
CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
931
COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
933
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
934
OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
936
OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL, 1);
938
CONDREG(samp_id_regid, A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID) |
939
A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(
940
sample_shading ? FRAGCOORD_SAMPLE : FRAGCOORD_CENTER));
942
OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
943
OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
945
OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
946
for (i = 0; i < 8; i++) {
947
OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
948
COND(color_regid[i] & HALF_REG_ID,
949
A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
950
if (VALIDREG(color_regid[i])) {
951
state->mrt_components |= 0xf << (i * 4);
955
/* dual source blending has an extra fs output in the 2nd slot */
956
if (fs_has_dual_src_color) {
957
state->mrt_components |= 0xf << 4;
960
OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
961
OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
962
A6XX_VPC_VS_PACK_PSIZELOC(psize_loc) |
963
A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
966
assert(gs->mergedregs == (ds ? ds->mergedregs : vs->mergedregs));
967
OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
970
A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
971
A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(gs->info.max_half_reg + 1) |
972
A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(gs)));
974
fd6_emit_shader(ctx, ring, gs);
975
fd6_emit_immediates(ctx->screen, gs, ring);
977
fd6_emit_link_map(ctx->screen, ds, gs, ring);
979
fd6_emit_link_map(ctx->screen, vs, gs, ring);
981
OUT_PKT4(ring, REG_A6XX_VPC_GS_PACK, 1);
982
OUT_RING(ring, A6XX_VPC_GS_PACK_POSITIONLOC(pos_loc) |
983
A6XX_VPC_GS_PACK_PSIZELOC(psize_loc) |
984
A6XX_VPC_GS_PACK_STRIDE_IN_VPC(l.max_loc));
986
OUT_PKT4(ring, REG_A6XX_VPC_GS_LAYER_CNTL, 1);
987
OUT_RING(ring, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
989
OUT_PKT4(ring, REG_A6XX_GRAS_GS_LAYER_CNTL, 1);
991
CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
993
uint32_t flags_regid =
994
ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
996
OUT_PKT4(ring, REG_A6XX_SP_GS_PRIMITIVE_CNTL, 1);
997
OUT_RING(ring, A6XX_SP_GS_PRIMITIVE_CNTL_OUT(l.cnt) |
998
A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
1000
OUT_PKT4(ring, REG_A6XX_PC_GS_OUT_CNTL, 1);
1002
A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
1003
CONDREG(psize_regid, A6XX_PC_GS_OUT_CNTL_PSIZE) |
1004
CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) |
1005
COND(gs_reads_primid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID) |
1006
A6XX_PC_GS_OUT_CNTL_CLIP_MASK(clip_cull_mask));
1009
switch (gs->shader->nir->info.gs.output_primitive) {
1010
case SHADER_PRIM_POINTS:
1011
output = TESS_POINTS;
1013
case SHADER_PRIM_LINE_STRIP:
1014
output = TESS_LINES;
1016
case SHADER_PRIM_TRIANGLE_STRIP:
1017
output = TESS_CW_TRIS;
1022
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1023
OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(
1024
gs->shader->nir->info.gs.vertices_out - 1) |
1025
A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1026
A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(
1027
gs->shader->nir->info.gs.invocations - 1));
1029
OUT_PKT4(ring, REG_A6XX_GRAS_GS_CL_CNTL, 1);
1030
OUT_RING(ring, A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(clip_mask) |
1031
A6XX_GRAS_GS_CL_CNTL_CULL_MASK(cull_mask));
1033
OUT_PKT4(ring, REG_A6XX_VPC_GS_PARAM, 1);
1034
OUT_RING(ring, 0xff);
1036
OUT_PKT4(ring, REG_A6XX_VPC_GS_CLIP_CNTL, 1);
1037
OUT_RING(ring, A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
1038
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
1039
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
1041
const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
1043
/* Size of per-primitive alloction in ldlw memory in vec4s. */
1044
uint32_t vec4_size = gs->shader->nir->info.gs.vertices_in *
1045
DIV_ROUND_UP(prev->output_size, 4);
1046
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1047
OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1049
OUT_PKT4(ring, REG_A6XX_PC_MULTIVIEW_CNTL, 1);
1052
uint32_t prim_size = prev->output_size;
1055
else if (prim_size == 64)
1057
OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1058
OUT_RING(ring, prim_size);
1060
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1062
OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1065
OUT_PKT4(ring, REG_A6XX_GRAS_VS_LAYER_CNTL, 1);
1067
CONDREG(layer_regid, A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER));
1070
OUT_PKT4(ring, REG_A6XX_VPC_VS_CLIP_CNTL, 1);
1071
OUT_RING(ring, A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
1072
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
1073
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
1075
OUT_PKT4(ring, REG_A6XX_GRAS_VS_CL_CNTL, 1);
1076
OUT_RING(ring, A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(clip_mask) |
1077
A6XX_GRAS_VS_CL_CNTL_CULL_MASK(cull_mask));
1079
OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
1083
fd6_emit_shader(ctx, ring, fs);
1085
OUT_REG(ring, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
1087
uint32_t non_sysval_input_count = 0;
1088
for (uint32_t i = 0; i < vs->inputs_count; i++)
1089
if (!vs->inputs[i].sysval)
1090
non_sysval_input_count++;
1092
OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
1093
OUT_RING(ring, A6XX_VFD_CONTROL_0_FETCH_CNT(non_sysval_input_count) |
1094
A6XX_VFD_CONTROL_0_DECODE_CNT(non_sysval_input_count));
1096
OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(0), non_sysval_input_count);
1097
for (uint32_t i = 0; i < non_sysval_input_count; i++) {
1098
assert(vs->inputs[i].compmask);
1100
A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
1101
A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid));
1104
OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
1105
OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
1106
A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
1107
A6XX_VFD_CONTROL_1_REGID4PRIMID(vs_primitive_regid) |
1110
A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(hs_rel_patch_regid) |
1111
A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
1112
OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(ds_rel_patch_regid) |
1113
A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
1114
A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
1115
A6XX_VFD_CONTROL_3_REGID_DSPRIMID(ds_primitive_regid));
1116
OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
1117
OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
1118
0xfc00); /* VFD_CONTROL_5 */
1119
OUT_RING(ring, COND(primid_passthru,
1120
A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
1123
fd6_emit_immediates(ctx->screen, fs, ring);
1126
static void emit_interp_state(struct fd_ringbuffer *ring,
1127
struct ir3_shader_variant *fs, bool rasterflat,
1128
bool sprite_coord_mode,
1129
uint32_t sprite_coord_enable);
1131
static struct fd_ringbuffer *
1132
create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
1134
struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
1136
emit_interp_state(ring, state->fs, false, false, 0);
1141
/* build the program streaming state which is not part of the pre-
1142
* baked stateobj because of dependency on other gl state (rasterflat
1143
* or sprite-coord-replacement)
1145
struct fd_ringbuffer *
1146
fd6_program_interp_state(struct fd6_emit *emit)
1148
const struct fd6_program_state *state = fd6_emit_get_prog(emit);
1150
if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
1152
return fd_ringbuffer_ref(state->interp_stateobj);
1154
struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
1155
emit->ctx->batch->submit, 18 * 4, FD_RINGBUFFER_STREAMING);
1157
emit_interp_state(ring, state->fs, emit->rasterflat,
1158
emit->sprite_coord_mode, emit->sprite_coord_enable);
1165
emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
1166
bool rasterflat, bool sprite_coord_mode,
1167
uint32_t sprite_coord_enable)
1169
uint32_t vinterp[8], vpsrepl[8];
1171
memset(vinterp, 0, sizeof(vinterp));
1172
memset(vpsrepl, 0, sizeof(vpsrepl));
1174
for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count;) {
1176
/* NOTE: varyings are packed, so if compmask is 0xb
1177
* then first, third, and fourth component occupy
1178
* three consecutive varying slots:
1180
unsigned compmask = fs->inputs[j].compmask;
1182
uint32_t inloc = fs->inputs[j].inloc;
1184
if (fs->inputs[j].flat || (fs->inputs[j].rasterflat && rasterflat)) {
1185
uint32_t loc = inloc;
1187
for (int i = 0; i < 4; i++) {
1188
if (compmask & (1 << i)) {
1189
vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
1195
bool coord_mode = sprite_coord_mode;
1196
if (ir3_point_sprite(fs, j, sprite_coord_enable, &coord_mode)) {
1197
/* mask is two 2-bit fields, where:
1200
* '11' -> 1 - T (flip mode)
1202
unsigned mask = coord_mode ? 0b1101 : 0b1001;
1203
uint32_t loc = inloc;
1204
if (compmask & 0x1) {
1205
vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
1208
if (compmask & 0x2) {
1209
vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
1212
if (compmask & 0x4) {
1214
vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
1217
if (compmask & 0x8) {
1219
vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
1225
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1226
for (int i = 0; i < 8; i++)
1227
OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
1229
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1230
for (int i = 0; i < 8; i++)
1231
OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
1234
static struct ir3_program_state *
1235
fd6_program_create(void *data, struct ir3_shader_variant *bs,
1236
struct ir3_shader_variant *vs, struct ir3_shader_variant *hs,
1237
struct ir3_shader_variant *ds, struct ir3_shader_variant *gs,
1238
struct ir3_shader_variant *fs,
1239
const struct ir3_cache_key *key) in_dt
1241
struct fd_context *ctx = fd_context(data);
1242
struct fd_screen *screen = ctx->screen;
1243
struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
1245
tc_assert_driver_thread(ctx->tc);
1247
/* if we have streamout, use full VS in binning pass, as the
1248
* binning pass VS will have outputs on other than position/psize
1251
state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
1257
state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1258
state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1262
for (unsigned i = 0; i < bs->inputs_count; i++) {
1263
if (vs->inputs[i].sysval)
1265
debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
1271
/* Allocate the fixed-size tess factor BO globally on the screen. This
1272
* lets the program (which ideally we would have shared across contexts,
1273
* though the current ir3_cache impl doesn't do that) bake in the
1276
fd_screen_lock(screen);
1277
if (!screen->tess_bo)
1279
fd_bo_new(screen->dev, FD6_TESS_BO_SIZE, 0, "tessfactor");
1280
fd_screen_unlock(screen);
1283
setup_config_stateobj(ctx, state);
1284
setup_stateobj(state->binning_stateobj, ctx, state, key, true);
1285
setup_stateobj(state->stateobj, ctx, state, key, false);
1286
state->interp_stateobj = create_interp_stateobj(ctx, state);
1288
struct ir3_stream_output_info *stream_output =
1289
&fd6_last_shader(state)->shader->stream_output;
1290
if (stream_output->num_outputs > 0)
1291
state->stream_output = stream_output;
1293
return &state->base;
1297
fd6_program_destroy(void *data, struct ir3_program_state *state)
1299
struct fd6_program_state *so = fd6_program_state(state);
1300
fd_ringbuffer_del(so->stateobj);
1301
fd_ringbuffer_del(so->binning_stateobj);
1302
fd_ringbuffer_del(so->config_stateobj);
1303
fd_ringbuffer_del(so->interp_stateobj);
1304
if (so->streamout_stateobj)
1305
fd_ringbuffer_del(so->streamout_stateobj);
1309
static const struct ir3_cache_funcs cache_funcs = {
1310
.create_state = fd6_program_create,
1311
.destroy_state = fd6_program_destroy,
1315
fd6_prog_init(struct pipe_context *pctx)
1317
struct fd_context *ctx = fd_context(pctx);
1319
ctx->shader_cache = ir3_cache_create(&cache_funcs, ctx);
1321
ir3_prog_init(pctx);
added
removed
src/gallium/drivers/freedreno/a6xx/fd6_program.c
